lib/Target/Mips/MipsSubtarget.h

   1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file declares the Mips specific subclass of TargetSubtargetInfo.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
  14 #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
  15
  16 #include "MCTargetDesc/MipsABIInfo.h"
  17 #include "MipsFrameLowering.h"
  18 #include "MipsISelLowering.h"
  19 #include "MipsInstrInfo.h"
  20 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
  21 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  22 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
  23 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
  24 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
  25 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
  26 #include "llvm/IR/DataLayout.h"
  27 #include "llvm/MC/MCInstrItineraries.h"
  28 #include "llvm/Support/ErrorHandling.h"
  29 #include <string>
  30
  31 #define GET_SUBTARGETINFO_HEADER
  32 #include "MipsGenSubtargetInfo.inc"
  33
  34 namespace llvm {
  35 class StringRef;
  36
  37 class MipsTargetMachine;
  38
  39 class MipsSubtarget : public MipsGenSubtargetInfo {
  40   virtual void anchor();
  41
  42   enum MipsArchEnum {
  43     MipsDefault,
  44     Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
  45     Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
  46   };
  47
  48   enum class CPU { P5600 };
  49
  50   // Used to avoid printing dsp warnings multiple times.
  51   static bool DspWarningPrinted;
  52
  53   // Used to avoid printing msa warnings multiple times.
  54   static bool MSAWarningPrinted;
  55
  56   // Used to avoid printing crc warnings multiple times.
  57   static bool CRCWarningPrinted;
  58
  59   // Used to avoid printing ginv warnings multiple times.
  60   static bool GINVWarningPrinted;
  61
  62   // Used to avoid printing virt warnings multiple times.
  63   static bool VirtWarningPrinted;
  64
  65   // Mips architecture version
  66   MipsArchEnum MipsArchVersion;
  67
  68   // Processor implementation (unused but required to exist by
  69   // tablegen-erated code).
  70   CPU ProcImpl;
  71
  72   // IsLittle - The target is Little Endian
  73   bool IsLittle;
  74
  75   // IsSoftFloat - The target does not support any floating point instructions.
  76   bool IsSoftFloat;
  77
  78   // IsSingleFloat - The target only supports single precision float
  79   // point operations. This enable the target to use all 32 32-bit
  80   // floating point registers instead of only using even ones.
  81   bool IsSingleFloat;
  82
  83   // IsFPXX - MIPS O32 modeless ABI.
  84   bool IsFPXX;
  85
  86   // NoABICalls - Disable SVR4-style position-independent code.
  87   bool NoABICalls;
  88
  89   // Abs2008 - Use IEEE 754-2008 abs.fmt instruction.
  90   bool Abs2008;
  91
  92   // IsFP64bit - The target processor has 64-bit floating point registers.
  93   bool IsFP64bit;
  94
  95   /// Are odd single-precision registers permitted?
  96   /// This corresponds to -modd-spreg and -mno-odd-spreg
  97   bool UseOddSPReg;
  98
  99   // IsNan2008 - IEEE 754-2008 NaN encoding.
 100   bool IsNaN2008bit;
 101
 102   // IsGP64bit - General-purpose registers are 64 bits wide
 103   bool IsGP64bit;
 104
 105   // IsPTR64bit - Pointers are 64 bit wide
 106   bool IsPTR64bit;
 107
 108   // HasVFPU - Processor has a vector floating point unit.
 109   bool HasVFPU;
 110
 111   // CPU supports cnMIPS (Cavium Networks Octeon CPU).
 112   bool HasCnMips;
 113
 114   // isLinux - Target system is Linux. Is false we consider ELFOS for now.
 115   bool IsLinux;
 116
 117   // UseSmallSection - Small section is used.
 118   bool UseSmallSection;
 119
 120   /// Features related to the presence of specific instructions.
 121
 122   // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
 123   bool HasMips3_32;
 124
 125   // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
 126   bool HasMips3_32r2;
 127
 128   // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
 129   bool HasMips4_32;
 130
 131   // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
 132   bool HasMips4_32r2;
 133
 134   // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
 135   bool HasMips5_32r2;
 136
 137   // InMips16 -- can process Mips16 instructions
 138   bool InMips16Mode;
 139
 140   // Mips16 hard float
 141   bool InMips16HardFloat;
 142
 143   // InMicroMips -- can process MicroMips instructions
 144   bool InMicroMipsMode;
 145
 146   // HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE.
 147   bool HasDSP, HasDSPR2, HasDSPR3;
 148
 149   // Allow mixed Mips16 and Mips32 in one source file
 150   bool AllowMixed16_32;
 151
 152   // Optimize for space by compiling all functions as Mips 16 unless
 153   // it needs floating point. Functions needing floating point are
 154   // compiled as Mips32
 155   bool Os16;
 156
 157   // HasMSA -- supports MSA ASE.
 158   bool HasMSA;
 159
 160   // UseTCCInDIV -- Enables the use of trapping in the assembler.
 161   bool UseTCCInDIV;
 162
 163   // Sym32 -- On Mips64 symbols are 32 bits.
 164   bool HasSym32;
 165
 166   // HasEVA -- supports EVA ASE.
 167   bool HasEVA;
 168
 169   // nomadd4 - disables generation of 4-operand madd.s, madd.d and
 170   // related instructions.
 171   bool DisableMadd4;
 172
 173   // HasMT -- support MT ASE.
 174   bool HasMT;
 175
 176   // HasCRC -- supports R6 CRC ASE
 177   bool HasCRC;
 178
 179   // HasVirt -- supports Virtualization ASE
 180   bool HasVirt;
 181
 182   // HasGINV -- supports R6 Global INValidate ASE
 183   bool HasGINV;
 184
 185   // Use hazard variants of the jump register instructions for indirect
 186   // function calls and jump tables.
 187   bool UseIndirectJumpsHazard;
 188
 189   // Disable use of the `jal` instruction.
 190   bool UseLongCalls = false;
 191
 192   // Assume 32-bit GOT.
 193   bool UseXGOT = false;
 194
 195   /// The minimum alignment known to hold of the stack frame on
 196   /// entry to the function and which must be maintained by every function.
 197   Align stackAlignment;
 198
 199   /// The overridden stack alignment.
 200   MaybeAlign StackAlignOverride;
 201
 202   InstrItineraryData InstrItins;
 203
 204   // We can override the determination of whether we are in mips16 mode
 205   // as from the command line
 206   enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
 207
 208   const MipsTargetMachine &TM;
 209
 210   Triple TargetTriple;
 211
 212   const SelectionDAGTargetInfo TSInfo;
 213   std::unique_ptr<const MipsInstrInfo> InstrInfo;
 214   std::unique_ptr<const MipsFrameLowering> FrameLowering;
 215   std::unique_ptr<const MipsTargetLowering> TLInfo;
 216
 217 public:
 218   bool isPositionIndependent() const;
 219   /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
 220   bool enablePostRAScheduler() const override;
 221   void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
 222   CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override;
 223
 224   bool isABI_N64() const;
 225   bool isABI_N32() const;
 226   bool isABI_O32() const;
 227   const MipsABIInfo &getABI() const;
 228   bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
 229
 230   /// This constructor initializes the data members to match that
 231   /// of the specified triple.
 232   MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little,
 233                 const MipsTargetMachine &TM, MaybeAlign StackAlignOverride);
 234
 235   /// ParseSubtargetFeatures - Parses features string setting specified
 236   /// subtarget options.  Definition of function is auto generated by tblgen.
 237   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
 238
 239   bool hasMips1() const { return MipsArchVersion >= Mips1; }
 240   bool hasMips2() const { return MipsArchVersion >= Mips2; }
 241   bool hasMips3() const { return MipsArchVersion >= Mips3; }
 242   bool hasMips4() const { return MipsArchVersion >= Mips4; }
 243   bool hasMips5() const { return MipsArchVersion >= Mips5; }
 244   bool hasMips4_32() const { return HasMips4_32; }
 245   bool hasMips4_32r2() const { return HasMips4_32r2; }
 246   bool hasMips32() const {
 247     return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) ||
 248            hasMips64();
 249   }
 250   bool hasMips32r2() const {
 251     return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||
 252            hasMips64r2();
 253   }
 254   bool hasMips32r3() const {
 255     return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||
 256            hasMips64r2();
 257   }
 258   bool hasMips32r5() const {
 259     return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
 260            hasMips64r5();
 261   }
 262   bool hasMips32r6() const {
 263     return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
 264            hasMips64r6();
 265   }
 266   bool hasMips64() const { return MipsArchVersion >= Mips64; }
 267   bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; }
 268   bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; }
 269   bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; }
 270   bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; }
 271
 272   bool hasCnMips() const { return HasCnMips; }
 273
 274   bool isLittle() const { return IsLittle; }
 275   bool isABICalls() const { return !NoABICalls; }
 276   bool isFPXX() const { return IsFPXX; }
 277   bool isFP64bit() const { return IsFP64bit; }
 278   bool useOddSPReg() const { return UseOddSPReg; }
 279   bool noOddSPReg() const { return !UseOddSPReg; }
 280   bool isNaN2008() const { return IsNaN2008bit; }
 281   bool inAbs2008Mode() const { return Abs2008; }
 282   bool isGP64bit() const { return IsGP64bit; }
 283   bool isGP32bit() const { return !IsGP64bit; }
 284   unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
 285   bool isPTR64bit() const { return IsPTR64bit; }
 286   bool isPTR32bit() const { return !IsPTR64bit; }
 287   bool hasSym32() const {
 288     return (HasSym32 && isABI_N64()) || isABI_N32() || isABI_O32();
 289   }
 290   bool isSingleFloat() const { return IsSingleFloat; }
 291   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
 292   bool hasVFPU() const { return HasVFPU; }
 293   bool inMips16Mode() const { return InMips16Mode; }
 294   bool inMips16ModeDefault() const {
 295     return InMips16Mode;
 296   }
 297   // Hard float for mips16 means essentially to compile as soft float
 298   // but to use a runtime library for soft float that is written with
 299   // native mips32 floating point instructions (those runtime routines
 300   // run in mips32 hard float mode).
 301   bool inMips16HardFloat() const {
 302     return inMips16Mode() && InMips16HardFloat;
 303   }
 304   bool inMicroMipsMode() const { return InMicroMipsMode && !InMips16Mode; }
 305   bool inMicroMips32r6Mode() const {
 306     return inMicroMipsMode() && hasMips32r6();
 307   }
 308   bool hasDSP() const { return HasDSP; }
 309   bool hasDSPR2() const { return HasDSPR2; }
 310   bool hasDSPR3() const { return HasDSPR3; }
 311   bool hasMSA() const { return HasMSA; }
 312   bool disableMadd4() const { return DisableMadd4; }
 313   bool hasEVA() const { return HasEVA; }
 314   bool hasMT() const { return HasMT; }
 315   bool hasCRC() const { return HasCRC; }
 316   bool hasVirt() const { return HasVirt; }
 317   bool hasGINV() const { return HasGINV; }
 318   bool useIndirectJumpsHazard() const {
 319     return UseIndirectJumpsHazard && hasMips32r2();
 320   }
 321   bool useSmallSection() const { return UseSmallSection; }
 322
 323   bool hasStandardEncoding() const { return !InMips16Mode && !InMicroMipsMode; }
 324
 325   bool useSoftFloat() const { return IsSoftFloat; }
 326
 327   bool useLongCalls() const { return UseLongCalls; }
 328
 329   bool useXGOT() const { return UseXGOT; }
 330
 331   bool enableLongBranchPass() const {
 332     return hasStandardEncoding() || inMicroMipsMode() || allowMixed16_32();
 333   }
 334
 335   /// Features related to the presence of specific instructions.
 336   bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
 337   bool hasMTHC1() const { return hasMips32r2(); }
 338
 339   bool allowMixed16_32() const { return inMips16ModeDefault() |
 340                                         AllowMixed16_32; }
 341
 342   bool os16() const { return Os16; }
 343
 344   bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
 345
 346   bool isXRaySupported() const override { return true; }
 347
 348   // for now constant islands are on for the whole compilation unit but we only
 349   // really use them if in addition we are in mips16 mode
 350   static bool useConstantIslands();
 351
 352   Align getStackAlignment() const { return stackAlignment; }
 353
 354   // Grab relocation model
 355   Reloc::Model getRelocationModel() const;
 356
 357   MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
 358                                                  const TargetMachine &TM);
 359
 360   /// Does the system support unaligned memory access.
 361   ///
 362   /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
 363   /// specify which component of the system provides it. Hardware, software, and
 364   /// hybrid implementations are all valid.
 365   bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
 366
 367   // Set helper classes
 368   void setHelperClassesMips16();
 369   void setHelperClassesMipsSE();
 370
 371   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
 372     return &TSInfo;
 373   }
 374   const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
 375   const TargetFrameLowering *getFrameLowering() const override {
 376     return FrameLowering.get();
 377   }
 378   const MipsRegisterInfo *getRegisterInfo() const override {
 379     return &InstrInfo->getRegisterInfo();
 380   }
 381   const MipsTargetLowering *getTargetLowering() const override {
 382     return TLInfo.get();
 383   }
 384   const InstrItineraryData *getInstrItineraryData() const override {
 385     return &InstrItins;
 386   }
 387
 388 protected:
 389   // GlobalISel related APIs.
 390   std::unique_ptr<CallLowering> CallLoweringInfo;
 391   std::unique_ptr<LegalizerInfo> Legalizer;
 392   std::unique_ptr<RegisterBankInfo> RegBankInfo;
 393   std::unique_ptr<InstructionSelector> InstSelector;
 394
 395 public:
 396   const CallLowering *getCallLowering() const override;
 397   const LegalizerInfo *getLegalizerInfo() const override;
 398   const RegisterBankInfo *getRegBankInfo() const override;
 399   InstructionSelector *getInstructionSelector() const override;
 400 };
 401 } // End llvm namespace
 402
 403 #endif