lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp

   1 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This class prints an PPC MCInst to a .s file.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "MCTargetDesc/PPCInstPrinter.h"
  14 #include "MCTargetDesc/PPCMCTargetDesc.h"
  15 #include "MCTargetDesc/PPCPredicates.h"
  16 #include "PPCInstrInfo.h"
  17 #include "llvm/CodeGen/TargetOpcodes.h"
  18 #include "llvm/MC/MCExpr.h"
  19 #include "llvm/MC/MCInst.h"
  20 #include "llvm/MC/MCInstrInfo.h"
  21 #include "llvm/MC/MCRegisterInfo.h"
  22 #include "llvm/MC/MCSubtargetInfo.h"
  23 #include "llvm/MC/MCSymbol.h"
  24 #include "llvm/Support/CommandLine.h"
  25 #include "llvm/Support/raw_ostream.h"
  26 using namespace llvm;
  27
  28 #define DEBUG_TYPE "asm-printer"
  29
  30 // FIXME: Once the integrated assembler supports full register names, tie this
  31 // to the verbose-asm setting.
  32 static cl::opt<bool>
  33 FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
  34              cl::desc("Use full register names when printing assembly"));
  35
  36 // Useful for testing purposes. Prints vs{31-63} as v{0-31} respectively.
  37 static cl::opt<bool>
  38 ShowVSRNumsAsVR("ppc-vsr-nums-as-vr", cl::Hidden, cl::init(false),
  39              cl::desc("Prints full register names with vs{31-63} as v{0-31}"));
  40
  41 // Prints full register names with percent symbol.
  42 static cl::opt<bool>
  43 FullRegNamesWithPercent("ppc-reg-with-percent-prefix", cl::Hidden,
  44                         cl::init(false),
  45                         cl::desc("Prints full register names with percent"));
  46
  47 #define PRINT_ALIAS_INSTR
  48 #include "PPCGenAsmWriter.inc"
  49
  50 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
  51   const char *RegName = getRegisterName(RegNo);
  52   if (RegName[0] == 'q' /* QPX */) {
  53     // The system toolchain on the BG/Q does not understand QPX register names
  54     // in .cfi_* directives, so print the name of the floating-point
  55     // subregister instead.
  56     std::string RN(RegName);
  57
  58     RN[0] = 'f';
  59     OS << RN;
  60
  61     return;
  62   }
  63
  64   OS << RegName;
  65 }
  66
  67 void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
  68                                StringRef Annot, const MCSubtargetInfo &STI) {
  69   // Customize printing of the addis instruction on AIX. When an operand is a
  70   // symbol reference, the instruction syntax is changed to look like a load
  71   // operation, i.e:
  72   //     Transform:  addis $rD, $rA, $src --> addis $rD, $src($rA).
  73   if (TT.isOSAIX() &&
  74       (MI->getOpcode() == PPC::ADDIS8 || MI->getOpcode() == PPC::ADDIS) &&
  75       MI->getOperand(2).isExpr()) {
  76     assert((MI->getOperand(0).isReg() && MI->getOperand(1).isReg()) &&
  77            "The first and the second operand of an addis instruction"
  78            " should be registers.");
  79
  80     assert(isa<MCSymbolRefExpr>(MI->getOperand(2).getExpr()) &&
  81            "The third operand of an addis instruction should be a symbol "
  82            "reference expression if it is an expression at all.");
  83
  84     O << "\taddis ";
  85     printOperand(MI, 0, O);
  86     O << ", ";
  87     printOperand(MI, 2, O);
  88     O << "(";
  89     printOperand(MI, 1, O);
  90     O << ")";
  91     return;
  92   }
  93
  94   // Check for slwi/srwi mnemonics.
  95   if (MI->getOpcode() == PPC::RLWINM) {
  96     unsigned char SH = MI->getOperand(2).getImm();
  97     unsigned char MB = MI->getOperand(3).getImm();
  98     unsigned char ME = MI->getOperand(4).getImm();
  99     bool useSubstituteMnemonic = false;
 100     if (SH <= 31 && MB == 0 && ME == (31-SH)) {
 101       O << "\tslwi "; useSubstituteMnemonic = true;
 102     }
 103     if (SH <= 31 && MB == (32-SH) && ME == 31) {
 104       O << "\tsrwi "; useSubstituteMnemonic = true;
 105       SH = 32-SH;
 106     }
 107     if (useSubstituteMnemonic) {
 108       printOperand(MI, 0, O);
 109       O << ", ";
 110       printOperand(MI, 1, O);
 111       O << ", " << (unsigned int)SH;
 112
 113       printAnnotation(O, Annot);
 114       return;
 115     }
 116   }
 117
 118   if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
 119       MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
 120     O << "\tmr ";
 121     printOperand(MI, 0, O);
 122     O << ", ";
 123     printOperand(MI, 1, O);
 124     printAnnotation(O, Annot);
 125     return;
 126   }
 127
 128   if (MI->getOpcode() == PPC::RLDICR ||
 129       MI->getOpcode() == PPC::RLDICR_32) {
 130     unsigned char SH = MI->getOperand(2).getImm();
 131     unsigned char ME = MI->getOperand(3).getImm();
 132     // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
 133     if (63-SH == ME) {
 134       O << "\tsldi ";
 135       printOperand(MI, 0, O);
 136       O << ", ";
 137       printOperand(MI, 1, O);
 138       O << ", " << (unsigned int)SH;
 139       printAnnotation(O, Annot);
 140       return;
 141     }
 142   }
 143
 144   // dcbt[st] is printed manually here because:
 145   //  1. The assembly syntax is different between embedded and server targets
 146   //  2. We must print the short mnemonics for TH == 0 because the
 147   //     embedded/server syntax default will not be stable across assemblers
 148   //  The syntax for dcbt is:
 149   //    dcbt ra, rb, th [server]
 150   //    dcbt th, ra, rb [embedded]
 151   //  where th can be omitted when it is 0. dcbtst is the same.
 152   if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
 153     unsigned char TH = MI->getOperand(0).getImm();
 154     O << "\tdcbt";
 155     if (MI->getOpcode() == PPC::DCBTST)
 156       O << "st";
 157     if (TH == 16)
 158       O << "t";
 159     O << " ";
 160
 161     bool IsBookE = STI.getFeatureBits()[PPC::FeatureBookE];
 162     if (IsBookE && TH != 0 && TH != 16)
 163       O << (unsigned int) TH << ", ";
 164
 165     printOperand(MI, 1, O);
 166     O << ", ";
 167     printOperand(MI, 2, O);
 168
 169     if (!IsBookE && TH != 0 && TH != 16)
 170       O << ", " << (unsigned int) TH;
 171
 172     printAnnotation(O, Annot);
 173     return;
 174   }
 175
 176   if (MI->getOpcode() == PPC::DCBF) {
 177     unsigned char L = MI->getOperand(0).getImm();
 178     if (!L || L == 1 || L == 3) {
 179       O << "\tdcbf";
 180       if (L == 1 || L == 3)
 181         O << "l";
 182       if (L == 3)
 183         O << "p";
 184       O << " ";
 185
 186       printOperand(MI, 1, O);
 187       O << ", ";
 188       printOperand(MI, 2, O);
 189
 190       printAnnotation(O, Annot);
 191       return;
 192     }
 193   }
 194
 195   if (!printAliasInstr(MI, O))
 196     printInstruction(MI, O);
 197   printAnnotation(O, Annot);
 198 }
 199
 200
 201 void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
 202                                            raw_ostream &O,
 203                                            const char *Modifier) {
 204   unsigned Code = MI->getOperand(OpNo).getImm();
 205
 206   if (StringRef(Modifier) == "cc") {
 207     switch ((PPC::Predicate)Code) {
 208     case PPC::PRED_LT_MINUS:
 209     case PPC::PRED_LT_PLUS:
 210     case PPC::PRED_LT:
 211       O << "lt";
 212       return;
 213     case PPC::PRED_LE_MINUS:
 214     case PPC::PRED_LE_PLUS:
 215     case PPC::PRED_LE:
 216       O << "le";
 217       return;
 218     case PPC::PRED_EQ_MINUS:
 219     case PPC::PRED_EQ_PLUS:
 220     case PPC::PRED_EQ:
 221       O << "eq";
 222       return;
 223     case PPC::PRED_GE_MINUS:
 224     case PPC::PRED_GE_PLUS:
 225     case PPC::PRED_GE:
 226       O << "ge";
 227       return;
 228     case PPC::PRED_GT_MINUS:
 229     case PPC::PRED_GT_PLUS:
 230     case PPC::PRED_GT:
 231       O << "gt";
 232       return;
 233     case PPC::PRED_NE_MINUS:
 234     case PPC::PRED_NE_PLUS:
 235     case PPC::PRED_NE:
 236       O << "ne";
 237       return;
 238     case PPC::PRED_UN_MINUS:
 239     case PPC::PRED_UN_PLUS:
 240     case PPC::PRED_UN:
 241       O << "un";
 242       return;
 243     case PPC::PRED_NU_MINUS:
 244     case PPC::PRED_NU_PLUS:
 245     case PPC::PRED_NU:
 246       O << "nu";
 247       return;
 248     case PPC::PRED_BIT_SET:
 249     case PPC::PRED_BIT_UNSET:
 250       llvm_unreachable("Invalid use of bit predicate code");
 251     }
 252     llvm_unreachable("Invalid predicate code");
 253   }
 254
 255   if (StringRef(Modifier) == "pm") {
 256     switch ((PPC::Predicate)Code) {
 257     case PPC::PRED_LT:
 258     case PPC::PRED_LE:
 259     case PPC::PRED_EQ:
 260     case PPC::PRED_GE:
 261     case PPC::PRED_GT:
 262     case PPC::PRED_NE:
 263     case PPC::PRED_UN:
 264     case PPC::PRED_NU:
 265       return;
 266     case PPC::PRED_LT_MINUS:
 267     case PPC::PRED_LE_MINUS:
 268     case PPC::PRED_EQ_MINUS:
 269     case PPC::PRED_GE_MINUS:
 270     case PPC::PRED_GT_MINUS:
 271     case PPC::PRED_NE_MINUS:
 272     case PPC::PRED_UN_MINUS:
 273     case PPC::PRED_NU_MINUS:
 274       O << "-";
 275       return;
 276     case PPC::PRED_LT_PLUS:
 277     case PPC::PRED_LE_PLUS:
 278     case PPC::PRED_EQ_PLUS:
 279     case PPC::PRED_GE_PLUS:
 280     case PPC::PRED_GT_PLUS:
 281     case PPC::PRED_NE_PLUS:
 282     case PPC::PRED_UN_PLUS:
 283     case PPC::PRED_NU_PLUS:
 284       O << "+";
 285       return;
 286     case PPC::PRED_BIT_SET:
 287     case PPC::PRED_BIT_UNSET:
 288       llvm_unreachable("Invalid use of bit predicate code");
 289     }
 290     llvm_unreachable("Invalid predicate code");
 291   }
 292
 293   assert(StringRef(Modifier) == "reg" &&
 294          "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
 295   printOperand(MI, OpNo+1, O);
 296 }
 297
 298 void PPCInstPrinter::printATBitsAsHint(const MCInst *MI, unsigned OpNo,
 299                                        raw_ostream &O) {
 300   unsigned Code = MI->getOperand(OpNo).getImm();
 301   if (Code == 2)
 302     O << "-";
 303   else if (Code == 3)
 304     O << "+";
 305 }
 306
 307 void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo,
 308                                        raw_ostream &O) {
 309   unsigned int Value = MI->getOperand(OpNo).getImm();
 310   assert(Value <= 1 && "Invalid u1imm argument!");
 311   O << (unsigned int)Value;
 312 }
 313
 314 void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
 315                                        raw_ostream &O) {
 316   unsigned int Value = MI->getOperand(OpNo).getImm();
 317   assert(Value <= 3 && "Invalid u2imm argument!");
 318   O << (unsigned int)Value;
 319 }
 320
 321 void PPCInstPrinter::printU3ImmOperand(const MCInst *MI, unsigned OpNo,
 322                                        raw_ostream &O) {
 323   unsigned int Value = MI->getOperand(OpNo).getImm();
 324   assert(Value <= 8 && "Invalid u3imm argument!");
 325   O << (unsigned int)Value;
 326 }
 327
 328 void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
 329                                        raw_ostream &O) {
 330   unsigned int Value = MI->getOperand(OpNo).getImm();
 331   assert(Value <= 15 && "Invalid u4imm argument!");
 332   O << (unsigned int)Value;
 333 }
 334
 335 void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
 336                                        raw_ostream &O) {
 337   int Value = MI->getOperand(OpNo).getImm();
 338   Value = SignExtend32<5>(Value);
 339   O << (int)Value;
 340 }
 341
 342 void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
 343                                        raw_ostream &O) {
 344   unsigned int Value = MI->getOperand(OpNo).getImm();
 345   assert(Value <= 31 && "Invalid u5imm argument!");
 346   O << (unsigned int)Value;
 347 }
 348
 349 void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
 350                                        raw_ostream &O) {
 351   unsigned int Value = MI->getOperand(OpNo).getImm();
 352   assert(Value <= 63 && "Invalid u6imm argument!");
 353   O << (unsigned int)Value;
 354 }
 355
 356 void PPCInstPrinter::printU7ImmOperand(const MCInst *MI, unsigned OpNo,
 357                                        raw_ostream &O) {
 358   unsigned int Value = MI->getOperand(OpNo).getImm();
 359   assert(Value <= 127 && "Invalid u7imm argument!");
 360   O << (unsigned int)Value;
 361 }
 362
 363 // Operands of BUILD_VECTOR are signed and we use this to print operands
 364 // of XXSPLTIB which are unsigned. So we simply truncate to 8 bits and
 365 // print as unsigned.
 366 void PPCInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
 367                                        raw_ostream &O) {
 368   unsigned char Value = MI->getOperand(OpNo).getImm();
 369   O << (unsigned int)Value;
 370 }
 371
 372 void PPCInstPrinter::printU10ImmOperand(const MCInst *MI, unsigned OpNo,
 373                                         raw_ostream &O) {
 374   unsigned short Value = MI->getOperand(OpNo).getImm();
 375   assert(Value <= 1023 && "Invalid u10imm argument!");
 376   O << (unsigned short)Value;
 377 }
 378
 379 void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo,
 380                                         raw_ostream &O) {
 381   unsigned short Value = MI->getOperand(OpNo).getImm();
 382   assert(Value <= 4095 && "Invalid u12imm argument!");
 383   O << (unsigned short)Value;
 384 }
 385
 386 void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
 387                                         raw_ostream &O) {
 388   if (MI->getOperand(OpNo).isImm())
 389     O << (short)MI->getOperand(OpNo).getImm();
 390   else
 391     printOperand(MI, OpNo, O);
 392 }
 393
 394 void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
 395                                         raw_ostream &O) {
 396   if (MI->getOperand(OpNo).isImm())
 397     O << (unsigned short)MI->getOperand(OpNo).getImm();
 398   else
 399     printOperand(MI, OpNo, O);
 400 }
 401
 402 void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
 403                                         raw_ostream &O) {
 404   if (!MI->getOperand(OpNo).isImm())
 405     return printOperand(MI, OpNo, O);
 406
 407   // Branches can take an immediate operand.  This is used by the branch
 408   // selection pass to print .+8, an eight byte displacement from the PC.
 409   O << ".";
 410   int32_t Imm = SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
 411   if (Imm >= 0)
 412     O << "+";
 413   O << Imm;
 414 }
 415
 416 void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
 417                                            raw_ostream &O) {
 418   if (!MI->getOperand(OpNo).isImm())
 419     return printOperand(MI, OpNo, O);
 420
 421   O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
 422 }
 423
 424
 425 void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
 426                                  raw_ostream &O) {
 427   unsigned CCReg = MI->getOperand(OpNo).getReg();
 428   unsigned RegNo;
 429   switch (CCReg) {
 430   default: llvm_unreachable("Unknown CR register");
 431   case PPC::CR0: RegNo = 0; break;
 432   case PPC::CR1: RegNo = 1; break;
 433   case PPC::CR2: RegNo = 2; break;
 434   case PPC::CR3: RegNo = 3; break;
 435   case PPC::CR4: RegNo = 4; break;
 436   case PPC::CR5: RegNo = 5; break;
 437   case PPC::CR6: RegNo = 6; break;
 438   case PPC::CR7: RegNo = 7; break;
 439   }
 440   O << (0x80 >> RegNo);
 441 }
 442
 443 void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
 444                                     raw_ostream &O) {
 445   printS16ImmOperand(MI, OpNo, O);
 446   O << '(';
 447   if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
 448     O << "0";
 449   else
 450     printOperand(MI, OpNo+1, O);
 451   O << ')';
 452 }
 453
 454 void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
 455                                     raw_ostream &O) {
 456   // When used as the base register, r0 reads constant zero rather than
 457   // the value contained in the register.  For this reason, the darwin
 458   // assembler requires that we print r0 as 0 (no r) when used as the base.
 459   if (MI->getOperand(OpNo).getReg() == PPC::R0)
 460     O << "0";
 461   else
 462     printOperand(MI, OpNo, O);
 463   O << ", ";
 464   printOperand(MI, OpNo+1, O);
 465 }
 466
 467 void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
 468                                   raw_ostream &O) {
 469   // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
 470   // come at the _end_ of the expression.
 471   const MCOperand &Op = MI->getOperand(OpNo);
 472   const MCSymbolRefExpr *RefExp = nullptr;
 473   const MCConstantExpr *ConstExp = nullptr;
 474   if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Op.getExpr())) {
 475     RefExp = cast<MCSymbolRefExpr>(BinExpr->getLHS());
 476     ConstExp = cast<MCConstantExpr>(BinExpr->getRHS());
 477   } else
 478     RefExp = cast<MCSymbolRefExpr>(Op.getExpr());
 479
 480   O << RefExp->getSymbol().getName();
 481   O << '(';
 482   printOperand(MI, OpNo+1, O);
 483   O << ')';
 484   if (RefExp->getKind() != MCSymbolRefExpr::VK_None)
 485     O << '@' << MCSymbolRefExpr::getVariantKindName(RefExp->getKind());
 486   if (ConstExp != nullptr)
 487     O << '+' << ConstExp->getValue();
 488 }
 489
 490 /// showRegistersWithPercentPrefix - Check if this register name should be
 491 /// printed with a percentage symbol as prefix.
 492 bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const {
 493   if (!FullRegNamesWithPercent || TT.isOSDarwin() || TT.getOS() == Triple::AIX)
 494     return false;
 495
 496   switch (RegName[0]) {
 497   default:
 498     return false;
 499   case 'r':
 500   case 'f':
 501   case 'q':
 502   case 'v':
 503   case 'c':
 504     return true;
 505   }
 506 }
 507
 508 /// getVerboseConditionalRegName - This method expands the condition register
 509 /// when requested explicitly or targetting Darwin.
 510 const char *PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum,
 511                                                        unsigned RegEncoding)
 512                                                        const {
 513   if (!TT.isOSDarwin() && !FullRegNames)
 514     return nullptr;
 515   if (RegNum < PPC::CR0EQ || RegNum > PPC::CR7UN)
 516     return nullptr;
 517   const char *CRBits[] = {
 518     "lt", "gt", "eq", "un",
 519     "4*cr1+lt", "4*cr1+gt", "4*cr1+eq", "4*cr1+un",
 520     "4*cr2+lt", "4*cr2+gt", "4*cr2+eq", "4*cr2+un",
 521     "4*cr3+lt", "4*cr3+gt", "4*cr3+eq", "4*cr3+un",
 522     "4*cr4+lt", "4*cr4+gt", "4*cr4+eq", "4*cr4+un",
 523     "4*cr5+lt", "4*cr5+gt", "4*cr5+eq", "4*cr5+un",
 524     "4*cr6+lt", "4*cr6+gt", "4*cr6+eq", "4*cr6+un",
 525     "4*cr7+lt", "4*cr7+gt", "4*cr7+eq", "4*cr7+un"
 526   };
 527   return CRBits[RegEncoding];
 528 }
 529
 530 // showRegistersWithPrefix - This method determines whether registers
 531 // should be number-only or include the prefix.
 532 bool PPCInstPrinter::showRegistersWithPrefix() const {
 533   if (TT.getOS() == Triple::AIX)
 534     return false;
 535   return TT.isOSDarwin() || FullRegNamesWithPercent || FullRegNames;
 536 }
 537
 538 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
 539                                   raw_ostream &O) {
 540   const MCOperand &Op = MI->getOperand(OpNo);
 541   if (Op.isReg()) {
 542     unsigned Reg = Op.getReg();
 543     if (!ShowVSRNumsAsVR)
 544       Reg = PPCInstrInfo::getRegNumForOperand(MII.get(MI->getOpcode()),
 545                                               Reg, OpNo);
 546
 547     const char *RegName;
 548     RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg));
 549     if (RegName == nullptr)
 550      RegName = getRegisterName(Reg);
 551     if (showRegistersWithPercentPrefix(RegName))
 552       O << "%";
 553     if (!showRegistersWithPrefix())
 554       RegName = PPCRegisterInfo::stripRegisterPrefix(RegName);
 555
 556     O << RegName;
 557     return;
 558   }
 559
 560   if (Op.isImm()) {
 561     O << Op.getImm();
 562     return;
 563   }
 564
 565   assert(Op.isExpr() && "unknown operand kind in printOperand");
 566   Op.getExpr()->print(O, &MAI);
 567 }
 568