lib/Target/PowerPC/PPCScheduleA2.td

   1 //===- PPCScheduleA2.td - PPC A2 Scheduling Definitions --*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 // Primary reference:
  10 // A2 Processor User's Manual.
  11 // IBM (as updated in) 2010.
  12
  13 //===----------------------------------------------------------------------===//
  14 // Functional units on the PowerPC A2 chip sets
  15 //
  16 def A2_XU     : FuncUnit; // A2_XU pipeline
  17 def A2_FU     : FuncUnit; // FI pipeline
  18
  19 //
  20 // This file defines the itinerary class data for the PPC A2 processor.
  21 //
  22 //===----------------------------------------------------------------------===//
  23
  24
  25 def PPCA2Itineraries : ProcessorItineraries<
  26   [A2_XU, A2_FU], [], [
  27   InstrItinData<IIC_IntSimple,   [InstrStage<1, [A2_XU]>],
  28                                  [1, 0, 0]>,
  29   InstrItinData<IIC_IntGeneral,  [InstrStage<1, [A2_XU]>],
  30                                  [2, 0, 0]>,
  31   InstrItinData<IIC_IntISEL,     [InstrStage<1, [A2_XU]>],
  32                                  [2, 0, 0, 0]>,
  33   InstrItinData<IIC_IntCompare,  [InstrStage<1, [A2_XU]>],
  34                                  [2, 0, 0]>,
  35   InstrItinData<IIC_IntDivW,     [InstrStage<1, [A2_XU]>],
  36                                  [39, 0, 0]>,
  37   InstrItinData<IIC_IntDivD,     [InstrStage<1, [A2_XU]>],
  38                                  [71, 0, 0]>,
  39   InstrItinData<IIC_IntMulHW,    [InstrStage<1, [A2_XU]>],
  40                                  [5, 0, 0]>,
  41   InstrItinData<IIC_IntMulHWU,   [InstrStage<1, [A2_XU]>],
  42                                  [5, 0, 0]>,
  43   InstrItinData<IIC_IntMulLI,    [InstrStage<1, [A2_XU]>],
  44                                  [6, 0, 0]>,
  45   InstrItinData<IIC_IntRotate,   [InstrStage<1, [A2_XU]>],
  46                                  [2, 0, 0]>,
  47   InstrItinData<IIC_IntRotateD,  [InstrStage<1, [A2_XU]>],
  48                                  [2, 0, 0]>,
  49   InstrItinData<IIC_IntRotateDI, [InstrStage<1, [A2_XU]>],
  50                                  [2, 0, 0]>,
  51   InstrItinData<IIC_IntShift,    [InstrStage<1, [A2_XU]>],
  52                                  [2, 0, 0]>,
  53   InstrItinData<IIC_IntTrapW,    [InstrStage<1, [A2_XU]>],
  54                                  [2, 0]>,
  55   InstrItinData<IIC_IntTrapD,    [InstrStage<1, [A2_XU]>],
  56                                  [2, 0]>,
  57   InstrItinData<IIC_BrB,         [InstrStage<1, [A2_XU]>],
  58                                  [6, 0, 0]>,
  59   InstrItinData<IIC_BrCR,        [InstrStage<1, [A2_XU]>],
  60                                  [1, 0, 0]>,
  61   InstrItinData<IIC_BrMCR,       [InstrStage<1, [A2_XU]>],
  62                                  [5, 0, 0]>,
  63   InstrItinData<IIC_BrMCRX,      [InstrStage<1, [A2_XU]>],
  64                                  [1, 0, 0]>,
  65   InstrItinData<IIC_LdStDCBA,    [InstrStage<1, [A2_XU]>],
  66                                  [1, 0, 0]>,
  67   InstrItinData<IIC_LdStDCBF,    [InstrStage<1, [A2_XU]>],
  68                                  [1, 0, 0]>,
  69   InstrItinData<IIC_LdStDCBI,    [InstrStage<1, [A2_XU]>],
  70                                  [1, 0, 0]>,
  71   InstrItinData<IIC_LdStLoad,    [InstrStage<1, [A2_XU]>],
  72                                  [6, 0, 0]>,
  73   InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [A2_XU]>],
  74                                  [6, 8, 0, 0]>,
  75   InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [A2_XU]>],
  76                                  [6, 8, 0, 0]>,
  77   InstrItinData<IIC_LdStLDU,     [InstrStage<1, [A2_XU]>],
  78                                  [6, 0, 0]>,
  79   InstrItinData<IIC_LdStLDUX,    [InstrStage<1, [A2_XU]>],
  80                                  [6, 0, 0]>,
  81   InstrItinData<IIC_LdStStore,   [InstrStage<1, [A2_XU]>],
  82                                  [0, 0, 0]>,
  83   InstrItinData<IIC_LdStICBI,    [InstrStage<1, [A2_XU]>],
  84                                  [16, 0, 0]>,
  85   InstrItinData<IIC_LdStSTFD,    [InstrStage<1, [A2_XU]>],
  86                                  [0, 0, 0]>,
  87   InstrItinData<IIC_LdStSTFDU,   [InstrStage<1, [A2_XU]>],
  88                                  [2, 0, 0, 0]>,
  89   InstrItinData<IIC_LdStLFD,     [InstrStage<1, [A2_XU]>],
  90                                  [7, 0, 0]>,
  91   InstrItinData<IIC_LdStLFDU,    [InstrStage<1, [A2_XU]>],
  92                                  [7, 9, 0, 0]>,
  93   InstrItinData<IIC_LdStLFDUX,   [InstrStage<1, [A2_XU]>],
  94                                  [7, 9, 0, 0]>,
  95   InstrItinData<IIC_LdStLHA,     [InstrStage<1, [A2_XU]>],
  96                                  [6, 0, 0]>,
  97   InstrItinData<IIC_LdStLHAU,    [InstrStage<1, [A2_XU]>],
  98                                  [6, 8, 0, 0]>,
  99   InstrItinData<IIC_LdStLHAUX,   [InstrStage<1, [A2_XU]>],
 100                                  [6, 8, 0, 0]>,
 101   InstrItinData<IIC_LdStLWARX,   [InstrStage<1, [A2_XU]>],
 102                                  [82, 0, 0]>, // L2 latency
 103   InstrItinData<IIC_LdStSTD,     [InstrStage<1, [A2_XU]>],
 104                                  [0, 0, 0]>,
 105   InstrItinData<IIC_LdStSTU,     [InstrStage<1, [A2_XU]>],
 106                                  [2, 0, 0, 0]>,
 107   InstrItinData<IIC_LdStSTUX,    [InstrStage<1, [A2_XU]>],
 108                                  [2, 0, 0, 0]>,
 109   InstrItinData<IIC_LdStSTDCX,   [InstrStage<1, [A2_XU]>],
 110                                  [82, 0, 0]>, // L2 latency
 111   InstrItinData<IIC_LdStSTWCX,   [InstrStage<1, [A2_XU]>],
 112                                  [82, 0, 0]>, // L2 latency
 113   InstrItinData<IIC_LdStSync,    [InstrStage<1, [A2_XU]>],
 114                                  [6]>,
 115   InstrItinData<IIC_SprISYNC,    [InstrStage<1, [A2_XU]>],
 116                                  [16]>,
 117   InstrItinData<IIC_SprMTMSR,    [InstrStage<1, [A2_XU]>],
 118                                  [16, 0]>,
 119   InstrItinData<IIC_SprMFCR,     [InstrStage<1, [A2_XU]>],
 120                                  [6, 0]>,
 121   InstrItinData<IIC_SprMFCRF,    [InstrStage<1, [A2_XU]>],
 122                                  [1, 0]>,
 123   InstrItinData<IIC_SprMFMSR,    [InstrStage<1, [A2_XU]>],
 124                                  [4, 0]>,
 125   InstrItinData<IIC_SprMFSPR,    [InstrStage<1, [A2_XU]>],
 126                                  [6, 0]>,
 127   InstrItinData<IIC_SprMFTB,     [InstrStage<1, [A2_XU]>],
 128                                  [4, 0]>,
 129   InstrItinData<IIC_SprMTSPR,    [InstrStage<1, [A2_XU]>],
 130                                  [6, 0]>,
 131   InstrItinData<IIC_SprRFI,      [InstrStage<1, [A2_XU]>],
 132                                  [16]>,
 133   InstrItinData<IIC_SprSC,       [InstrStage<1, [A2_XU]>],
 134                                  [16]>,
 135   InstrItinData<IIC_FPGeneral,   [InstrStage<1, [A2_FU]>],
 136                                  [6, 0, 0]>,
 137   InstrItinData<IIC_FPAddSub,    [InstrStage<1, [A2_FU]>],
 138                                  [6, 0, 0]>,
 139   InstrItinData<IIC_FPCompare,   [InstrStage<1, [A2_FU]>],
 140                                  [5, 0, 0]>,
 141   InstrItinData<IIC_FPDivD,      [InstrStage<1, [A2_FU]>],
 142                                  [72, 0, 0]>,
 143   InstrItinData<IIC_FPDivS,      [InstrStage<1, [A2_FU]>],
 144                                  [59, 0, 0]>,
 145   InstrItinData<IIC_FPSqrtD,     [InstrStage<1, [A2_FU]>],
 146                                  [69, 0, 0]>,
 147   InstrItinData<IIC_FPSqrtS,     [InstrStage<1, [A2_FU]>],
 148                                  [65, 0, 0]>,
 149   InstrItinData<IIC_FPFused,     [InstrStage<1, [A2_FU]>],
 150                                  [6, 0, 0, 0]>,
 151   InstrItinData<IIC_FPRes,       [InstrStage<1, [A2_FU]>],
 152                                  [6, 0]>
 153 ]>;
 154
 155 // ===---------------------------------------------------------------------===//
 156 // A2 machine model for scheduling and other instruction cost heuristics.
 157
 158 def PPCA2Model : SchedMachineModel {
 159   let IssueWidth = 1;  // 1 instruction is dispatched per cycle.
 160   let LoadLatency = 6; // Optimistic load latency assuming bypass.
 161                        // This is overriden by OperandCycles if the
 162                        // Itineraries are queried instead.
 163   let MispredictPenalty = 13;
 164
 165   let CompleteModel = 0;
 166
 167   let Itineraries = PPCA2Itineraries;
 168 }
 169