lib/Target/XCore/XCoreISelDAGToDAG.cpp

   1 //===-- XCoreISelDAGToDAG.cpp - A dag to dag inst selector for XCore ------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines an instruction selector for the XCore target.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "XCore.h"
  14 #include "XCoreTargetMachine.h"
  15 #include "llvm/CodeGen/MachineFrameInfo.h"
  16 #include "llvm/CodeGen/MachineFunction.h"
  17 #include "llvm/CodeGen/MachineInstrBuilder.h"
  18 #include "llvm/CodeGen/MachineRegisterInfo.h"
  19 #include "llvm/CodeGen/SelectionDAG.h"
  20 #include "llvm/CodeGen/SelectionDAGISel.h"
  21 #include "llvm/CodeGen/TargetLowering.h"
  22 #include "llvm/IR/CallingConv.h"
  23 #include "llvm/IR/Constants.h"
  24 #include "llvm/IR/DerivedTypes.h"
  25 #include "llvm/IR/Function.h"
  26 #include "llvm/IR/Intrinsics.h"
  27 #include "llvm/IR/LLVMContext.h"
  28 #include "llvm/Support/Debug.h"
  29 #include "llvm/Support/ErrorHandling.h"
  30 #include "llvm/Support/raw_ostream.h"
  31 using namespace llvm;
  32
  33 /// XCoreDAGToDAGISel - XCore specific code to select XCore machine
  34 /// instructions for SelectionDAG operations.
  35 ///
  36 namespace {
  37   class XCoreDAGToDAGISel : public SelectionDAGISel {
  38
  39   public:
  40     XCoreDAGToDAGISel(XCoreTargetMachine &TM, CodeGenOpt::Level OptLevel)
  41       : SelectionDAGISel(TM, OptLevel) {}
  42
  43     void Select(SDNode *N) override;
  44     bool tryBRIND(SDNode *N);
  45
  46     /// getI32Imm - Return a target constant with the specified value, of type
  47     /// i32.
  48     inline SDValue getI32Imm(unsigned Imm, const SDLoc &dl) {
  49       return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
  50     }
  51
  52     inline bool immMskBitp(SDNode *inN) const {
  53       ConstantSDNode *N = cast<ConstantSDNode>(inN);
  54       uint32_t value = (uint32_t)N->getZExtValue();
  55       if (!isMask_32(value)) {
  56         return false;
  57       }
  58       int msksize = 32 - countLeadingZeros(value);
  59       return (msksize >= 1 && msksize <= 8) ||
  60               msksize == 16 || msksize == 24 || msksize == 32;
  61     }
  62
  63     // Complex Pattern Selectors.
  64     bool SelectADDRspii(SDValue Addr, SDValue &Base, SDValue &Offset);
  65
  66     bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
  67                                       std::vector<SDValue> &OutOps) override;
  68
  69     StringRef getPassName() const override {
  70       return "XCore DAG->DAG Pattern Instruction Selection";
  71     }
  72
  73     // Include the pieces autogenerated from the target description.
  74   #include "XCoreGenDAGISel.inc"
  75   };
  76 }  // end anonymous namespace
  77
  78 /// createXCoreISelDag - This pass converts a legalized DAG into a
  79 /// XCore-specific DAG, ready for instruction scheduling.
  80 ///
  81 FunctionPass *llvm::createXCoreISelDag(XCoreTargetMachine &TM,
  82                                        CodeGenOpt::Level OptLevel) {
  83   return new XCoreDAGToDAGISel(TM, OptLevel);
  84 }
  85
  86 bool XCoreDAGToDAGISel::SelectADDRspii(SDValue Addr, SDValue &Base,
  87                                        SDValue &Offset) {
  88   FrameIndexSDNode *FIN = nullptr;
  89   if ((FIN = dyn_cast<FrameIndexSDNode>(Addr))) {
  90     Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
  91     Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
  92     return true;
  93   }
  94   if (Addr.getOpcode() == ISD::ADD) {
  95     ConstantSDNode *CN = nullptr;
  96     if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
  97       && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
  98       && (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) {
  99       // Constant positive word offset from frame index
 100       Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
 101       Offset = CurDAG->getTargetConstant(CN->getSExtValue(), SDLoc(Addr),
 102                                          MVT::i32);
 103       return true;
 104     }
 105   }
 106   return false;
 107 }
 108
 109 bool XCoreDAGToDAGISel::
 110 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
 111                              std::vector<SDValue> &OutOps) {
 112   SDValue Reg;
 113   switch (ConstraintID) {
 114   default: return true;
 115   case InlineAsm::Constraint_m: // Memory.
 116     switch (Op.getOpcode()) {
 117     default: return true;
 118     case XCoreISD::CPRelativeWrapper:
 119       Reg = CurDAG->getRegister(XCore::CP, MVT::i32);
 120       break;
 121     case XCoreISD::DPRelativeWrapper:
 122       Reg = CurDAG->getRegister(XCore::DP, MVT::i32);
 123       break;
 124     }
 125   }
 126   OutOps.push_back(Reg);
 127   OutOps.push_back(Op.getOperand(0));
 128   return false;
 129 }
 130
 131 void XCoreDAGToDAGISel::Select(SDNode *N) {
 132   SDLoc dl(N);
 133   switch (N->getOpcode()) {
 134   default: break;
 135   case ISD::Constant: {
 136     uint64_t Val = cast<ConstantSDNode>(N)->getZExtValue();
 137     if (immMskBitp(N)) {
 138       // Transformation function: get the size of a mask
 139       // Look for the first non-zero bit
 140       SDValue MskSize = getI32Imm(32 - countLeadingZeros((uint32_t)Val), dl);
 141       ReplaceNode(N, CurDAG->getMachineNode(XCore::MKMSK_rus, dl,
 142                                             MVT::i32, MskSize));
 143       return;
 144     }
 145     else if (!isUInt<16>(Val)) {
 146       SDValue CPIdx = CurDAG->getTargetConstantPool(
 147           ConstantInt::get(Type::getInt32Ty(*CurDAG->getContext()), Val),
 148           getTargetLowering()->getPointerTy(CurDAG->getDataLayout()));
 149       SDNode *node = CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32,
 150                                             MVT::Other, CPIdx,
 151                                             CurDAG->getEntryNode());
 152       MachineMemOperand *MemOp =
 153           MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(*MF),
 154                                    MachineMemOperand::MOLoad, 4, 4);
 155       CurDAG->setNodeMemRefs(cast<MachineSDNode>(node), {MemOp});
 156       ReplaceNode(N, node);
 157       return;
 158     }
 159     break;
 160   }
 161   case XCoreISD::LADD: {
 162     SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
 163                         N->getOperand(2) };
 164     ReplaceNode(N, CurDAG->getMachineNode(XCore::LADD_l5r, dl, MVT::i32,
 165                                           MVT::i32, Ops));
 166     return;
 167   }
 168   case XCoreISD::LSUB: {
 169     SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
 170                         N->getOperand(2) };
 171     ReplaceNode(N, CurDAG->getMachineNode(XCore::LSUB_l5r, dl, MVT::i32,
 172                                           MVT::i32, Ops));
 173     return;
 174   }
 175   case XCoreISD::MACCU: {
 176     SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
 177                       N->getOperand(2), N->getOperand(3) };
 178     ReplaceNode(N, CurDAG->getMachineNode(XCore::MACCU_l4r, dl, MVT::i32,
 179                                           MVT::i32, Ops));
 180     return;
 181   }
 182   case XCoreISD::MACCS: {
 183     SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
 184                       N->getOperand(2), N->getOperand(3) };
 185     ReplaceNode(N, CurDAG->getMachineNode(XCore::MACCS_l4r, dl, MVT::i32,
 186                                           MVT::i32, Ops));
 187     return;
 188   }
 189   case XCoreISD::LMUL: {
 190     SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
 191                       N->getOperand(2), N->getOperand(3) };
 192     ReplaceNode(N, CurDAG->getMachineNode(XCore::LMUL_l6r, dl, MVT::i32,
 193                                           MVT::i32, Ops));
 194     return;
 195   }
 196   case XCoreISD::CRC8: {
 197     SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) };
 198     ReplaceNode(N, CurDAG->getMachineNode(XCore::CRC8_l4r, dl, MVT::i32,
 199                                           MVT::i32, Ops));
 200     return;
 201   }
 202   case ISD::BRIND:
 203     if (tryBRIND(N))
 204       return;
 205     break;
 206   // Other cases are autogenerated.
 207   }
 208   SelectCode(N);
 209 }
 210
 211 /// Given a chain return a new chain where any appearance of Old is replaced
 212 /// by New. There must be at most one instruction between Old and Chain and
 213 /// this instruction must be a TokenFactor. Returns an empty SDValue if
 214 /// these conditions don't hold.
 215 static SDValue
 216 replaceInChain(SelectionDAG *CurDAG, SDValue Chain, SDValue Old, SDValue New)
 217 {
 218   if (Chain == Old)
 219     return New;
 220   if (Chain->getOpcode() != ISD::TokenFactor)
 221     return SDValue();
 222   SmallVector<SDValue, 8> Ops;
 223   bool found = false;
 224   for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) {
 225     if (Chain->getOperand(i) == Old) {
 226       Ops.push_back(New);
 227       found = true;
 228     } else {
 229       Ops.push_back(Chain->getOperand(i));
 230     }
 231   }
 232   if (!found)
 233     return SDValue();
 234   return CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, Ops);
 235 }
 236
 237 bool XCoreDAGToDAGISel::tryBRIND(SDNode *N) {
 238   SDLoc dl(N);
 239   // (brind (int_xcore_checkevent (addr)))
 240   SDValue Chain = N->getOperand(0);
 241   SDValue Addr = N->getOperand(1);
 242   if (Addr->getOpcode() != ISD::INTRINSIC_W_CHAIN)
 243     return false;
 244   unsigned IntNo = cast<ConstantSDNode>(Addr->getOperand(1))->getZExtValue();
 245   if (IntNo != Intrinsic::xcore_checkevent)
 246     return false;
 247   SDValue nextAddr = Addr->getOperand(2);
 248   SDValue CheckEventChainOut(Addr.getNode(), 1);
 249   if (!CheckEventChainOut.use_empty()) {
 250     // If the chain out of the checkevent intrinsic is an operand of the
 251     // indirect branch or used in a TokenFactor which is the operand of the
 252     // indirect branch then build a new chain which uses the chain coming into
 253     // the checkevent intrinsic instead.
 254     SDValue CheckEventChainIn = Addr->getOperand(0);
 255     SDValue NewChain = replaceInChain(CurDAG, Chain, CheckEventChainOut,
 256                                       CheckEventChainIn);
 257     if (!NewChain.getNode())
 258       return false;
 259     Chain = NewChain;
 260   }
 261   // Enable events on the thread using setsr 1 and then disable them immediately
 262   // after with clrsr 1. If any resources owned by the thread are ready an event
 263   // will be taken. If no resource is ready we branch to the address which was
 264   // the operand to the checkevent intrinsic.
 265   SDValue constOne = getI32Imm(1, dl);
 266   SDValue Glue =
 267     SDValue(CurDAG->getMachineNode(XCore::SETSR_branch_u6, dl, MVT::Glue,
 268                                    constOne, Chain), 0);
 269   Glue =
 270     SDValue(CurDAG->getMachineNode(XCore::CLRSR_branch_u6, dl, MVT::Glue,
 271                                    constOne, Glue), 0);
 272   if (nextAddr->getOpcode() == XCoreISD::PCRelativeWrapper &&
 273       nextAddr->getOperand(0)->getOpcode() == ISD::TargetBlockAddress) {
 274     CurDAG->SelectNodeTo(N, XCore::BRFU_lu6, MVT::Other,
 275                          nextAddr->getOperand(0), Glue);
 276     return true;
 277   }
 278   CurDAG->SelectNodeTo(N, XCore::BAU_1r, MVT::Other, nextAddr, Glue);
 279   return true;
 280 }