lib/CodeGen/MachineCSE.cpp

   1 //===- MachineCSE.cpp - Machine Common Subexpression Elimination Pass -----===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This pass performs global common subexpression elimination on machine
  11 // instructions using a scoped hash table based value numbering scheme. It
  12 // must be run while the machine function is still in SSA form.
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #include "llvm/ADT/DenseMap.h"
  17 #include "llvm/ADT/ScopedHashTable.h"
  18 #include "llvm/ADT/SmallPtrSet.h"
  19 #include "llvm/ADT/SmallSet.h"
  20 #include "llvm/ADT/SmallVector.h"
  21 #include "llvm/ADT/Statistic.h"
  22 #include "llvm/Analysis/AliasAnalysis.h"
  23 #include "llvm/CodeGen/MachineBasicBlock.h"
  24 #include "llvm/CodeGen/MachineDominators.h"
  25 #include "llvm/CodeGen/MachineFunction.h"
  26 #include "llvm/CodeGen/MachineFunctionPass.h"
  27 #include "llvm/CodeGen/MachineInstr.h"
  28 #include "llvm/CodeGen/MachineOperand.h"
  29 #include "llvm/CodeGen/MachineRegisterInfo.h"
  30 #include "llvm/CodeGen/Passes.h"
  31 #include "llvm/CodeGen/TargetInstrInfo.h"
  32 #include "llvm/CodeGen/TargetOpcodes.h"
  33 #include "llvm/CodeGen/TargetRegisterInfo.h"
  34 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  35 #include "llvm/MC/MCInstrDesc.h"
  36 #include "llvm/MC/MCRegisterInfo.h"
  37 #include "llvm/Pass.h"
  38 #include "llvm/Support/Allocator.h"
  39 #include "llvm/Support/Debug.h"
  40 #include "llvm/Support/RecyclingAllocator.h"
  41 #include "llvm/Support/raw_ostream.h"
  42 #include <cassert>
  43 #include <iterator>
  44 #include <utility>
  45 #include <vector>
  46
  47 using namespace llvm;
  48
  49 #define DEBUG_TYPE "machine-cse"
  50
  51 STATISTIC(NumCoalesces, "Number of copies coalesced");
  52 STATISTIC(NumCSEs,      "Number of common subexpression eliminated");
  53 STATISTIC(NumPhysCSEs,
  54           "Number of physreg referencing common subexpr eliminated");
  55 STATISTIC(NumCrossBBCSEs,
  56           "Number of cross-MBB physreg referencing CS eliminated");
  57 STATISTIC(NumCommutes,  "Number of copies coalesced after commuting");
  58
  59 namespace {
  60
  61   class MachineCSE : public MachineFunctionPass {
  62     const TargetInstrInfo *TII;
  63     const TargetRegisterInfo *TRI;
  64     AliasAnalysis *AA;
  65     MachineDominatorTree *DT;
  66     MachineRegisterInfo *MRI;
  67
  68   public:
  69     static char ID; // Pass identification
  70
  71     MachineCSE() : MachineFunctionPass(ID) {
  72       initializeMachineCSEPass(*PassRegistry::getPassRegistry());
  73     }
  74
  75     bool runOnMachineFunction(MachineFunction &MF) override;
  76
  77     void getAnalysisUsage(AnalysisUsage &AU) const override {
  78       AU.setPreservesCFG();
  79       MachineFunctionPass::getAnalysisUsage(AU);
  80       AU.addRequired<AAResultsWrapperPass>();
  81       AU.addPreservedID(MachineLoopInfoID);
  82       AU.addRequired<MachineDominatorTree>();
  83       AU.addPreserved<MachineDominatorTree>();
  84     }
  85
  86     void releaseMemory() override {
  87       ScopeMap.clear();
  88       Exps.clear();
  89     }
  90
  91   private:
  92     using AllocatorTy = RecyclingAllocator<BumpPtrAllocator,
  93                             ScopedHashTableVal<MachineInstr *, unsigned>>;
  94     using ScopedHTType =
  95         ScopedHashTable<MachineInstr *, unsigned, MachineInstrExpressionTrait,
  96                         AllocatorTy>;
  97     using ScopeType = ScopedHTType::ScopeTy;
  98
  99     unsigned LookAheadLimit = 0;
 100     DenseMap<MachineBasicBlock *, ScopeType *> ScopeMap;
 101     ScopedHTType VNT;
 102     SmallVector<MachineInstr *, 64> Exps;
 103     unsigned CurrVN = 0;
 104
 105     bool PerformTrivialCopyPropagation(MachineInstr *MI,
 106                                        MachineBasicBlock *MBB);
 107     bool isPhysDefTriviallyDead(unsigned Reg,
 108                                 MachineBasicBlock::const_iterator I,
 109                                 MachineBasicBlock::const_iterator E) const;
 110     bool hasLivePhysRegDefUses(const MachineInstr *MI,
 111                                const MachineBasicBlock *MBB,
 112                                SmallSet<unsigned,8> &PhysRefs,
 113                                SmallVectorImpl<unsigned> &PhysDefs,
 114                                bool &PhysUseDef) const;
 115     bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
 116                           SmallSet<unsigned,8> &PhysRefs,
 117                           SmallVectorImpl<unsigned> &PhysDefs,
 118                           bool &NonLocal) const;
 119     bool isCSECandidate(MachineInstr *MI);
 120     bool isProfitableToCSE(unsigned CSReg, unsigned Reg,
 121                            MachineInstr *CSMI, MachineInstr *MI);
 122     void EnterScope(MachineBasicBlock *MBB);
 123     void ExitScope(MachineBasicBlock *MBB);
 124     bool ProcessBlock(MachineBasicBlock *MBB);
 125     void ExitScopeIfDone(MachineDomTreeNode *Node,
 126                          DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren);
 127     bool PerformCSE(MachineDomTreeNode *Node);
 128   };
 129
 130 } // end anonymous namespace
 131
 132 char MachineCSE::ID = 0;
 133
 134 char &llvm::MachineCSEID = MachineCSE::ID;
 135
 136 INITIALIZE_PASS_BEGIN(MachineCSE, DEBUG_TYPE,
 137                       "Machine Common Subexpression Elimination", false, false)
 138 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
 139 INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
 140 INITIALIZE_PASS_END(MachineCSE, DEBUG_TYPE,
 141                     "Machine Common Subexpression Elimination", false, false)
 142
 143 /// The source register of a COPY machine instruction can be propagated to all
 144 /// its users, and this propagation could increase the probability of finding
 145 /// common subexpressions. If the COPY has only one user, the COPY itself can
 146 /// be removed.
 147 bool MachineCSE::PerformTrivialCopyPropagation(MachineInstr *MI,
 148                                                MachineBasicBlock *MBB) {
 149   bool Changed = false;
 150   for (MachineOperand &MO : MI->operands()) {
 151     if (!MO.isReg() || !MO.isUse())
 152       continue;
 153     unsigned Reg = MO.getReg();
 154     if (!TargetRegisterInfo::isVirtualRegister(Reg))
 155       continue;
 156     bool OnlyOneUse = MRI->hasOneNonDBGUse(Reg);
 157     MachineInstr *DefMI = MRI->getVRegDef(Reg);
 158     if (!DefMI->isCopy())
 159       continue;
 160     unsigned SrcReg = DefMI->getOperand(1).getReg();
 161     if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
 162       continue;
 163     if (DefMI->getOperand(0).getSubReg())
 164       continue;
 165     // FIXME: We should trivially coalesce subregister copies to expose CSE
 166     // opportunities on instructions with truncated operands (see
 167     // cse-add-with-overflow.ll). This can be done here as follows:
 168     // if (SrcSubReg)
 169     //  RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC,
 170     //                                     SrcSubReg);
 171     // MO.substVirtReg(SrcReg, SrcSubReg, *TRI);
 172     //
 173     // The 2-addr pass has been updated to handle coalesced subregs. However,
 174     // some machine-specific code still can't handle it.
 175     // To handle it properly we also need a way find a constrained subregister
 176     // class given a super-reg class and subreg index.
 177     if (DefMI->getOperand(1).getSubReg())
 178       continue;
 179     if (!MRI->constrainRegAttrs(SrcReg, Reg))
 180       continue;
 181     LLVM_DEBUG(dbgs() << "Coalescing: " << *DefMI);
 182     LLVM_DEBUG(dbgs() << "***     to: " << *MI);
 183
 184     // Update matching debug values.
 185     DefMI->changeDebugValuesDefReg(SrcReg);
 186
 187     // Propagate SrcReg of copies to MI.
 188     MO.setReg(SrcReg);
 189     MRI->clearKillFlags(SrcReg);
 190     // Coalesce single use copies.
 191     if (OnlyOneUse) {
 192       DefMI->eraseFromParent();
 193       ++NumCoalesces;
 194     }
 195     Changed = true;
 196   }
 197
 198   return Changed;
 199 }
 200
 201 bool
 202 MachineCSE::isPhysDefTriviallyDead(unsigned Reg,
 203                                    MachineBasicBlock::const_iterator I,
 204                                    MachineBasicBlock::const_iterator E) const {
 205   unsigned LookAheadLeft = LookAheadLimit;
 206   while (LookAheadLeft) {
 207     // Skip over dbg_value's.
 208     I = skipDebugInstructionsForward(I, E);
 209
 210     if (I == E)
 211       // Reached end of block, we don't know if register is dead or not.
 212       return false;
 213
 214     bool SeenDef = false;
 215     for (const MachineOperand &MO : I->operands()) {
 216       if (MO.isRegMask() && MO.clobbersPhysReg(Reg))
 217         SeenDef = true;
 218       if (!MO.isReg() || !MO.getReg())
 219         continue;
 220       if (!TRI->regsOverlap(MO.getReg(), Reg))
 221         continue;
 222       if (MO.isUse())
 223         // Found a use!
 224         return false;
 225       SeenDef = true;
 226     }
 227     if (SeenDef)
 228       // See a def of Reg (or an alias) before encountering any use, it's
 229       // trivially dead.
 230       return true;
 231
 232     --LookAheadLeft;
 233     ++I;
 234   }
 235   return false;
 236 }
 237
 238 static bool isCallerPreservedOrConstPhysReg(unsigned Reg,
 239                                             const MachineFunction &MF,
 240                                             const TargetRegisterInfo &TRI) {
 241   // MachineRegisterInfo::isConstantPhysReg directly called by
 242   // MachineRegisterInfo::isCallerPreservedOrConstPhysReg expects the
 243   // reserved registers to be frozen. That doesn't cause a problem  post-ISel as
 244   // most (if not all) targets freeze reserved registers right after ISel.
 245   //
 246   // It does cause issues mid-GlobalISel, however, hence the additional
 247   // reservedRegsFrozen check.
 248   const MachineRegisterInfo &MRI = MF.getRegInfo();
 249   return TRI.isCallerPreservedPhysReg(Reg, MF) ||
 250          (MRI.reservedRegsFrozen() && MRI.isConstantPhysReg(Reg));
 251 }
 252
 253 /// hasLivePhysRegDefUses - Return true if the specified instruction read/write
 254 /// physical registers (except for dead defs of physical registers). It also
 255 /// returns the physical register def by reference if it's the only one and the
 256 /// instruction does not uses a physical register.
 257 bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
 258                                        const MachineBasicBlock *MBB,
 259                                        SmallSet<unsigned,8> &PhysRefs,
 260                                        SmallVectorImpl<unsigned> &PhysDefs,
 261                                        bool &PhysUseDef) const{
 262   // First, add all uses to PhysRefs.
 263   for (const MachineOperand &MO : MI->operands()) {
 264     if (!MO.isReg() || MO.isDef())
 265       continue;
 266     unsigned Reg = MO.getReg();
 267     if (!Reg)
 268       continue;
 269     if (TargetRegisterInfo::isVirtualRegister(Reg))
 270       continue;
 271     // Reading either caller preserved or constant physregs is ok.
 272     if (!isCallerPreservedOrConstPhysReg(Reg, *MI->getMF(), *TRI))
 273       for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
 274         PhysRefs.insert(*AI);
 275   }
 276
 277   // Next, collect all defs into PhysDefs.  If any is already in PhysRefs
 278   // (which currently contains only uses), set the PhysUseDef flag.
 279   PhysUseDef = false;
 280   MachineBasicBlock::const_iterator I = MI; I = std::next(I);
 281   for (const MachineOperand &MO : MI->operands()) {
 282     if (!MO.isReg() || !MO.isDef())
 283       continue;
 284     unsigned Reg = MO.getReg();
 285     if (!Reg)
 286       continue;
 287     if (TargetRegisterInfo::isVirtualRegister(Reg))
 288       continue;
 289     // Check against PhysRefs even if the def is "dead".
 290     if (PhysRefs.count(Reg))
 291       PhysUseDef = true;
 292     // If the def is dead, it's ok. But the def may not marked "dead". That's
 293     // common since this pass is run before livevariables. We can scan
 294     // forward a few instructions and check if it is obviously dead.
 295     if (!MO.isDead() && !isPhysDefTriviallyDead(Reg, I, MBB->end()))
 296       PhysDefs.push_back(Reg);
 297   }
 298
 299   // Finally, add all defs to PhysRefs as well.
 300   for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i)
 301     for (MCRegAliasIterator AI(PhysDefs[i], TRI, true); AI.isValid(); ++AI)
 302       PhysRefs.insert(*AI);
 303
 304   return !PhysRefs.empty();
 305 }
 306
 307 bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
 308                                   SmallSet<unsigned,8> &PhysRefs,
 309                                   SmallVectorImpl<unsigned> &PhysDefs,
 310                                   bool &NonLocal) const {
 311   // For now conservatively returns false if the common subexpression is
 312   // not in the same basic block as the given instruction. The only exception
 313   // is if the common subexpression is in the sole predecessor block.
 314   const MachineBasicBlock *MBB = MI->getParent();
 315   const MachineBasicBlock *CSMBB = CSMI->getParent();
 316
 317   bool CrossMBB = false;
 318   if (CSMBB != MBB) {
 319     if (MBB->pred_size() != 1 || *MBB->pred_begin() != CSMBB)
 320       return false;
 321
 322     for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
 323       if (MRI->isAllocatable(PhysDefs[i]) || MRI->isReserved(PhysDefs[i]))
 324         // Avoid extending live range of physical registers if they are
 325         //allocatable or reserved.
 326         return false;
 327     }
 328     CrossMBB = true;
 329   }
 330   MachineBasicBlock::const_iterator I = CSMI; I = std::next(I);
 331   MachineBasicBlock::const_iterator E = MI;
 332   MachineBasicBlock::const_iterator EE = CSMBB->end();
 333   unsigned LookAheadLeft = LookAheadLimit;
 334   while (LookAheadLeft) {
 335     // Skip over dbg_value's.
 336     while (I != E && I != EE && I->isDebugInstr())
 337       ++I;
 338
 339     if (I == EE) {
 340       assert(CrossMBB && "Reaching end-of-MBB without finding MI?");
 341       (void)CrossMBB;
 342       CrossMBB = false;
 343       NonLocal = true;
 344       I = MBB->begin();
 345       EE = MBB->end();
 346       continue;
 347     }
 348
 349     if (I == E)
 350       return true;
 351
 352     for (const MachineOperand &MO : I->operands()) {
 353       // RegMasks go on instructions like calls that clobber lots of physregs.
 354       // Don't attempt to CSE across such an instruction.
 355       if (MO.isRegMask())
 356         return false;
 357       if (!MO.isReg() || !MO.isDef())
 358         continue;
 359       unsigned MOReg = MO.getReg();
 360       if (TargetRegisterInfo::isVirtualRegister(MOReg))
 361         continue;
 362       if (PhysRefs.count(MOReg))
 363         return false;
 364     }
 365
 366     --LookAheadLeft;
 367     ++I;
 368   }
 369
 370   return false;
 371 }
 372
 373 bool MachineCSE::isCSECandidate(MachineInstr *MI) {
 374   if (MI->isPosition() || MI->isPHI() || MI->isImplicitDef() || MI->isKill() ||
 375       MI->isInlineAsm() || MI->isDebugInstr())
 376     return false;
 377
 378   // Ignore copies.
 379   if (MI->isCopyLike())
 380     return false;
 381
 382   // Ignore stuff that we obviously can't move.
 383   if (MI->mayStore() || MI->isCall() || MI->isTerminator() ||
 384       MI->hasUnmodeledSideEffects())
 385     return false;
 386
 387   if (MI->mayLoad()) {
 388     // Okay, this instruction does a load. As a refinement, we allow the target
 389     // to decide whether the loaded value is actually a constant. If so, we can
 390     // actually use it as a load.
 391     if (!MI->isDereferenceableInvariantLoad(AA))
 392       // FIXME: we should be able to hoist loads with no other side effects if
 393       // there are no other instructions which can change memory in this loop.
 394       // This is a trivial form of alias analysis.
 395       return false;
 396   }
 397
 398   // Ignore stack guard loads, otherwise the register that holds CSEed value may
 399   // be spilled and get loaded back with corrupted data.
 400   if (MI->getOpcode() == TargetOpcode::LOAD_STACK_GUARD)
 401     return false;
 402
 403   return true;
 404 }
 405
 406 /// isProfitableToCSE - Return true if it's profitable to eliminate MI with a
 407 /// common expression that defines Reg.
 408 bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg,
 409                                    MachineInstr *CSMI, MachineInstr *MI) {
 410   // FIXME: Heuristics that works around the lack the live range splitting.
 411
 412   // If CSReg is used at all uses of Reg, CSE should not increase register
 413   // pressure of CSReg.
 414   bool MayIncreasePressure = true;
 415   if (TargetRegisterInfo::isVirtualRegister(CSReg) &&
 416       TargetRegisterInfo::isVirtualRegister(Reg)) {
 417     MayIncreasePressure = false;
 418     SmallPtrSet<MachineInstr*, 8> CSUses;
 419     for (MachineInstr &MI : MRI->use_nodbg_instructions(CSReg)) {
 420       CSUses.insert(&MI);
 421     }
 422     for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
 423       if (!CSUses.count(&MI)) {
 424         MayIncreasePressure = true;
 425         break;
 426       }
 427     }
 428   }
 429   if (!MayIncreasePressure) return true;
 430
 431   // Heuristics #1: Don't CSE "cheap" computation if the def is not local or in
 432   // an immediate predecessor. We don't want to increase register pressure and
 433   // end up causing other computation to be spilled.
 434   if (TII->isAsCheapAsAMove(*MI)) {
 435     MachineBasicBlock *CSBB = CSMI->getParent();
 436     MachineBasicBlock *BB = MI->getParent();
 437     if (CSBB != BB && !CSBB->isSuccessor(BB))
 438       return false;
 439   }
 440
 441   // Heuristics #2: If the expression doesn't not use a vr and the only use
 442   // of the redundant computation are copies, do not cse.
 443   bool HasVRegUse = false;
 444   for (const MachineOperand &MO : MI->operands()) {
 445     if (MO.isReg() && MO.isUse() &&
 446         TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
 447       HasVRegUse = true;
 448       break;
 449     }
 450   }
 451   if (!HasVRegUse) {
 452     bool HasNonCopyUse = false;
 453     for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
 454       // Ignore copies.
 455       if (!MI.isCopyLike()) {
 456         HasNonCopyUse = true;
 457         break;
 458       }
 459     }
 460     if (!HasNonCopyUse)
 461       return false;
 462   }
 463
 464   // Heuristics #3: If the common subexpression is used by PHIs, do not reuse
 465   // it unless the defined value is already used in the BB of the new use.
 466   bool HasPHI = false;
 467   for (MachineInstr &UseMI : MRI->use_nodbg_instructions(CSReg)) {
 468     HasPHI |= UseMI.isPHI();
 469     if (UseMI.getParent() == MI->getParent())
 470       return true;
 471   }
 472
 473   return !HasPHI;
 474 }
 475
 476 void MachineCSE::EnterScope(MachineBasicBlock *MBB) {
 477   LLVM_DEBUG(dbgs() << "Entering: " << MBB->getName() << '\n');
 478   ScopeType *Scope = new ScopeType(VNT);
 479   ScopeMap[MBB] = Scope;
 480 }
 481
 482 void MachineCSE::ExitScope(MachineBasicBlock *MBB) {
 483   LLVM_DEBUG(dbgs() << "Exiting: " << MBB->getName() << '\n');
 484   DenseMap<MachineBasicBlock*, ScopeType*>::iterator SI = ScopeMap.find(MBB);
 485   assert(SI != ScopeMap.end());
 486   delete SI->second;
 487   ScopeMap.erase(SI);
 488 }
 489
 490 bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
 491   bool Changed = false;
 492
 493   SmallVector<std::pair<unsigned, unsigned>, 8> CSEPairs;
 494   SmallVector<unsigned, 2> ImplicitDefsToUpdate;
 495   SmallVector<unsigned, 2> ImplicitDefs;
 496   for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ) {
 497     MachineInstr *MI = &*I;
 498     ++I;
 499
 500     if (!isCSECandidate(MI))
 501       continue;
 502
 503     bool FoundCSE = VNT.count(MI);
 504     if (!FoundCSE) {
 505       // Using trivial copy propagation to find more CSE opportunities.
 506       if (PerformTrivialCopyPropagation(MI, MBB)) {
 507         Changed = true;
 508
 509         // After coalescing MI itself may become a copy.
 510         if (MI->isCopyLike())
 511           continue;
 512
 513         // Try again to see if CSE is possible.
 514         FoundCSE = VNT.count(MI);
 515       }
 516     }
 517
 518     // Commute commutable instructions.
 519     bool Commuted = false;
 520     if (!FoundCSE && MI->isCommutable()) {
 521       if (MachineInstr *NewMI = TII->commuteInstruction(*MI)) {
 522         Commuted = true;
 523         FoundCSE = VNT.count(NewMI);
 524         if (NewMI != MI) {
 525           // New instruction. It doesn't need to be kept.
 526           NewMI->eraseFromParent();
 527           Changed = true;
 528         } else if (!FoundCSE)
 529           // MI was changed but it didn't help, commute it back!
 530           (void)TII->commuteInstruction(*MI);
 531       }
 532     }
 533
 534     // If the instruction defines physical registers and the values *may* be
 535     // used, then it's not safe to replace it with a common subexpression.
 536     // It's also not safe if the instruction uses physical registers.
 537     bool CrossMBBPhysDef = false;
 538     SmallSet<unsigned, 8> PhysRefs;
 539     SmallVector<unsigned, 2> PhysDefs;
 540     bool PhysUseDef = false;
 541     if (FoundCSE && hasLivePhysRegDefUses(MI, MBB, PhysRefs,
 542                                           PhysDefs, PhysUseDef)) {
 543       FoundCSE = false;
 544
 545       // ... Unless the CS is local or is in the sole predecessor block
 546       // and it also defines the physical register which is not clobbered
 547       // in between and the physical register uses were not clobbered.
 548       // This can never be the case if the instruction both uses and
 549       // defines the same physical register, which was detected above.
 550       if (!PhysUseDef) {
 551         unsigned CSVN = VNT.lookup(MI);
 552         MachineInstr *CSMI = Exps[CSVN];
 553         if (PhysRegDefsReach(CSMI, MI, PhysRefs, PhysDefs, CrossMBBPhysDef))
 554           FoundCSE = true;
 555       }
 556     }
 557
 558     if (!FoundCSE) {
 559       VNT.insert(MI, CurrVN++);
 560       Exps.push_back(MI);
 561       continue;
 562     }
 563
 564     // Found a common subexpression, eliminate it.
 565     unsigned CSVN = VNT.lookup(MI);
 566     MachineInstr *CSMI = Exps[CSVN];
 567     LLVM_DEBUG(dbgs() << "Examining: " << *MI);
 568     LLVM_DEBUG(dbgs() << "*** Found a common subexpression: " << *CSMI);
 569
 570     // Check if it's profitable to perform this CSE.
 571     bool DoCSE = true;
 572     unsigned NumDefs = MI->getNumDefs();
 573
 574     for (unsigned i = 0, e = MI->getNumOperands(); NumDefs && i != e; ++i) {
 575       MachineOperand &MO = MI->getOperand(i);
 576       if (!MO.isReg() || !MO.isDef())
 577         continue;
 578       unsigned OldReg = MO.getReg();
 579       unsigned NewReg = CSMI->getOperand(i).getReg();
 580
 581       // Go through implicit defs of CSMI and MI, if a def is not dead at MI,
 582       // we should make sure it is not dead at CSMI.
 583       if (MO.isImplicit() && !MO.isDead() && CSMI->getOperand(i).isDead())
 584         ImplicitDefsToUpdate.push_back(i);
 585
 586       // Keep track of implicit defs of CSMI and MI, to clear possibly
 587       // made-redundant kill flags.
 588       if (MO.isImplicit() && !MO.isDead() && OldReg == NewReg)
 589         ImplicitDefs.push_back(OldReg);
 590
 591       if (OldReg == NewReg) {
 592         --NumDefs;
 593         continue;
 594       }
 595
 596       assert(TargetRegisterInfo::isVirtualRegister(OldReg) &&
 597              TargetRegisterInfo::isVirtualRegister(NewReg) &&
 598              "Do not CSE physical register defs!");
 599
 600       if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) {
 601         LLVM_DEBUG(dbgs() << "*** Not profitable, avoid CSE!\n");
 602         DoCSE = false;
 603         break;
 604       }
 605
 606       // Don't perform CSE if the result of the new instruction cannot exist
 607       // within the constraints (register class, bank, or low-level type) of
 608       // the old instruction.
 609       if (!MRI->constrainRegAttrs(NewReg, OldReg)) {
 610         LLVM_DEBUG(
 611             dbgs() << "*** Not the same register constraints, avoid CSE!\n");
 612         DoCSE = false;
 613         break;
 614       }
 615
 616       CSEPairs.push_back(std::make_pair(OldReg, NewReg));
 617       --NumDefs;
 618     }
 619
 620     // Actually perform the elimination.
 621     if (DoCSE) {
 622       for (std::pair<unsigned, unsigned> &CSEPair : CSEPairs) {
 623         unsigned OldReg = CSEPair.first;
 624         unsigned NewReg = CSEPair.second;
 625         // OldReg may have been unused but is used now, clear the Dead flag
 626         MachineInstr *Def = MRI->getUniqueVRegDef(NewReg);
 627         assert(Def != nullptr && "CSEd register has no unique definition?");
 628         Def->clearRegisterDeads(NewReg);
 629         // Replace with NewReg and clear kill flags which may be wrong now.
 630         MRI->replaceRegWith(OldReg, NewReg);
 631         MRI->clearKillFlags(NewReg);
 632       }
 633
 634       // Go through implicit defs of CSMI and MI, if a def is not dead at MI,
 635       // we should make sure it is not dead at CSMI.
 636       for (unsigned ImplicitDefToUpdate : ImplicitDefsToUpdate)
 637         CSMI->getOperand(ImplicitDefToUpdate).setIsDead(false);
 638
 639       // Go through implicit defs of CSMI and MI, and clear the kill flags on
 640       // their uses in all the instructions between CSMI and MI.
 641       // We might have made some of the kill flags redundant, consider:
 642       //   subs  ... implicit-def %nzcv    <- CSMI
 643       //   csinc ... implicit killed %nzcv <- this kill flag isn't valid anymore
 644       //   subs  ... implicit-def %nzcv    <- MI, to be eliminated
 645       //   csinc ... implicit killed %nzcv
 646       // Since we eliminated MI, and reused a register imp-def'd by CSMI
 647       // (here %nzcv), that register, if it was killed before MI, should have
 648       // that kill flag removed, because it's lifetime was extended.
 649       if (CSMI->getParent() == MI->getParent()) {
 650         for (MachineBasicBlock::iterator II = CSMI, IE = MI; II != IE; ++II)
 651           for (auto ImplicitDef : ImplicitDefs)
 652             if (MachineOperand *MO = II->findRegisterUseOperand(
 653                     ImplicitDef, /*isKill=*/true, TRI))
 654               MO->setIsKill(false);
 655       } else {
 656         // If the instructions aren't in the same BB, bail out and clear the
 657         // kill flag on all uses of the imp-def'd register.
 658         for (auto ImplicitDef : ImplicitDefs)
 659           MRI->clearKillFlags(ImplicitDef);
 660       }
 661
 662       if (CrossMBBPhysDef) {
 663         // Add physical register defs now coming in from a predecessor to MBB
 664         // livein list.
 665         while (!PhysDefs.empty()) {
 666           unsigned LiveIn = PhysDefs.pop_back_val();
 667           if (!MBB->isLiveIn(LiveIn))
 668             MBB->addLiveIn(LiveIn);
 669         }
 670         ++NumCrossBBCSEs;
 671       }
 672
 673       MI->eraseFromParent();
 674       ++NumCSEs;
 675       if (!PhysRefs.empty())
 676         ++NumPhysCSEs;
 677       if (Commuted)
 678         ++NumCommutes;
 679       Changed = true;
 680     } else {
 681       VNT.insert(MI, CurrVN++);
 682       Exps.push_back(MI);
 683     }
 684     CSEPairs.clear();
 685     ImplicitDefsToUpdate.clear();
 686     ImplicitDefs.clear();
 687   }
 688
 689   return Changed;
 690 }
 691
 692 /// ExitScopeIfDone - Destroy scope for the MBB that corresponds to the given
 693 /// dominator tree node if its a leaf or all of its children are done. Walk
 694 /// up the dominator tree to destroy ancestors which are now done.
 695 void
 696 MachineCSE::ExitScopeIfDone(MachineDomTreeNode *Node,
 697                         DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren) {
 698   if (OpenChildren[Node])
 699     return;
 700
 701   // Pop scope.
 702   ExitScope(Node->getBlock());
 703
 704   // Now traverse upwards to pop ancestors whose offsprings are all done.
 705   while (MachineDomTreeNode *Parent = Node->getIDom()) {
 706     unsigned Left = --OpenChildren[Parent];
 707     if (Left != 0)
 708       break;
 709     ExitScope(Parent->getBlock());
 710     Node = Parent;
 711   }
 712 }
 713
 714 bool MachineCSE::PerformCSE(MachineDomTreeNode *Node) {
 715   SmallVector<MachineDomTreeNode*, 32> Scopes;
 716   SmallVector<MachineDomTreeNode*, 8> WorkList;
 717   DenseMap<MachineDomTreeNode*, unsigned> OpenChildren;
 718
 719   CurrVN = 0;
 720
 721   // Perform a DFS walk to determine the order of visit.
 722   WorkList.push_back(Node);
 723   do {
 724     Node = WorkList.pop_back_val();
 725     Scopes.push_back(Node);
 726     const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
 727     OpenChildren[Node] = Children.size();
 728     for (MachineDomTreeNode *Child : Children)
 729       WorkList.push_back(Child);
 730   } while (!WorkList.empty());
 731
 732   // Now perform CSE.
 733   bool Changed = false;
 734   for (MachineDomTreeNode *Node : Scopes) {
 735     MachineBasicBlock *MBB = Node->getBlock();
 736     EnterScope(MBB);
 737     Changed |= ProcessBlock(MBB);
 738     // If it's a leaf node, it's done. Traverse upwards to pop ancestors.
 739     ExitScopeIfDone(Node, OpenChildren);
 740   }
 741
 742   return Changed;
 743 }
 744
 745 bool MachineCSE::runOnMachineFunction(MachineFunction &MF) {
 746   if (skipFunction(MF.getFunction()))
 747     return false;
 748
 749   TII = MF.getSubtarget().getInstrInfo();
 750   TRI = MF.getSubtarget().getRegisterInfo();
 751   MRI = &MF.getRegInfo();
 752   AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
 753   DT = &getAnalysis<MachineDominatorTree>();
 754   LookAheadLimit = TII->getMachineCSELookAheadLimit();
 755   return PerformCSE(DT->getRootNode());
 756 }