1 //===-- RISCVMCTargetDesc.h - RISCV Target Descriptions ---------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file provides RISCV specific target descriptions.
11 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCTARGETDESC_H
14 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCTARGETDESC_H
16 #include "llvm/Config/config.h"
17 #include "llvm/MC/MCTargetOptions.h"
18 #include "llvm/Support/DataTypes.h"
26 class MCObjectTargetWriter
;
28 class MCSubtargetInfo
;
33 class raw_pwrite_stream
;
35 MCCodeEmitter
*createRISCVMCCodeEmitter(const MCInstrInfo
&MCII
,
36 const MCRegisterInfo
&MRI
,
39 MCAsmBackend
*createRISCVAsmBackend(const Target
&T
, const MCSubtargetInfo
&STI
,
40 const MCRegisterInfo
&MRI
,
41 const MCTargetOptions
&Options
);
43 std::unique_ptr
<MCObjectTargetWriter
> createRISCVELFObjectWriter(uint8_t OSABI
,
47 // Defines symbolic names for RISC-V registers.
48 #define GET_REGINFO_ENUM
49 #include "RISCVGenRegisterInfo.inc"
51 // Defines symbolic names for RISC-V instructions.
52 #define GET_INSTRINFO_ENUM
53 #include "RISCVGenInstrInfo.inc"
55 #define GET_SUBTARGETINFO_ENUM
56 #include "RISCVGenSubtargetInfo.inc"