| blob | 161d88c1a047f5dbc0a445d0cf1d63773b02c857 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1
3 ; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP
4 ; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP
5 ; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM
7 declare i4 @llvm.ssub.sat.i4(i4, i4)
8 declare i8 @llvm.ssub.sat.i8(i8, i8)
9 declare i16 @llvm.ssub.sat.i16(i16, i16)
10 declare i32 @llvm.ssub.sat.i32(i32, i32)
11 declare i64 @llvm.ssub.sat.i64(i64, i64)
12 declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>)
14 define i32 @func(i32 %x, i32 %y) nounwind {
15 ; CHECK-T1-LABEL: func:
16 ; CHECK-T1: @ %bb.0:
17 ; CHECK-T1-NEXT: .save {r4, lr}
18 ; CHECK-T1-NEXT: push {r4, lr}
19 ; CHECK-T1-NEXT: mov r2, r0
20 ; CHECK-T1-NEXT: movs r3, #1
21 ; CHECK-T1-NEXT: subs r0, r0, r1
22 ; CHECK-T1-NEXT: mov r4, r3
23 ; CHECK-T1-NEXT: bmi .LBB0_2
24 ; CHECK-T1-NEXT: @ %bb.1:
25 ; CHECK-T1-NEXT: movs r4, #0
26 ; CHECK-T1-NEXT: .LBB0_2:
27 ; CHECK-T1-NEXT: cmp r4, #0
28 ; CHECK-T1-NEXT: bne .LBB0_4
29 ; CHECK-T1-NEXT: @ %bb.3:
30 ; CHECK-T1-NEXT: lsls r3, r3, #31
31 ; CHECK-T1-NEXT: cmp r2, r1
32 ; CHECK-T1-NEXT: bvs .LBB0_5
33 ; CHECK-T1-NEXT: b .LBB0_6
34 ; CHECK-T1-NEXT: .LBB0_4:
35 ; CHECK-T1-NEXT: ldr r3, .LCPI0_0
36 ; CHECK-T1-NEXT: cmp r2, r1
37 ; CHECK-T1-NEXT: bvc .LBB0_6
38 ; CHECK-T1-NEXT: .LBB0_5:
39 ; CHECK-T1-NEXT: mov r0, r3
40 ; CHECK-T1-NEXT: .LBB0_6:
41 ; CHECK-T1-NEXT: pop {r4, pc}
42 ; CHECK-T1-NEXT: .p2align 2
43 ; CHECK-T1-NEXT: @ %bb.7:
44 ; CHECK-T1-NEXT: .LCPI0_0:
45 ; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
46 ;
47 ; CHECK-T2-LABEL: func:
48 ; CHECK-T2: @ %bb.0:
49 ; CHECK-T2-NEXT: subs.w r12, r0, r1
50 ; CHECK-T2-NEXT: mov.w r3, #0
51 ; CHECK-T2-NEXT: mov.w r2, #-2147483648
52 ; CHECK-T2-NEXT: it mi
53 ; CHECK-T2-NEXT: movmi r3, #1
54 ; CHECK-T2-NEXT: cmp r3, #0
55 ; CHECK-T2-NEXT: it ne
56 ; CHECK-T2-NEXT: mvnne r2, #-2147483648
57 ; CHECK-T2-NEXT: cmp r0, r1
58 ; CHECK-T2-NEXT: it vc
59 ; CHECK-T2-NEXT: movvc r2, r12
60 ; CHECK-T2-NEXT: mov r0, r2
61 ; CHECK-T2-NEXT: bx lr
62 ;
63 ; CHECK-ARM-LABEL: func:
64 ; CHECK-ARM: @ %bb.0:
65 ; CHECK-ARM-NEXT: subs r12, r0, r1
66 ; CHECK-ARM-NEXT: mov r3, #0
67 ; CHECK-ARM-NEXT: movwmi r3, #1
68 ; CHECK-ARM-NEXT: mov r2, #-2147483648
69 ; CHECK-ARM-NEXT: cmp r3, #0
70 ; CHECK-ARM-NEXT: mvnne r2, #-2147483648
71 ; CHECK-ARM-NEXT: cmp r0, r1
72 ; CHECK-ARM-NEXT: movvc r2, r12
73 ; CHECK-ARM-NEXT: mov r0, r2
74 ; CHECK-ARM-NEXT: bx lr
75 %tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %y)
76 ret i32 %tmp
77 }
79 define i64 @func2(i64 %x, i64 %y) nounwind {
80 ; CHECK-T1-LABEL: func2:
81 ; CHECK-T1: @ %bb.0:
82 ; CHECK-T1-NEXT: .save {r4, r5, r6, r7, lr}
83 ; CHECK-T1-NEXT: push {r4, r5, r6, r7, lr}
84 ; CHECK-T1-NEXT: .pad #4
85 ; CHECK-T1-NEXT: sub sp, #4
86 ; CHECK-T1-NEXT: str r2, [sp] @ 4-byte Spill
87 ; CHECK-T1-NEXT: mov r2, r0
88 ; CHECK-T1-NEXT: movs r4, #1
89 ; CHECK-T1-NEXT: movs r0, #0
90 ; CHECK-T1-NEXT: cmp r3, #0
91 ; CHECK-T1-NEXT: mov r5, r4
92 ; CHECK-T1-NEXT: bge .LBB1_2
93 ; CHECK-T1-NEXT: @ %bb.1:
94 ; CHECK-T1-NEXT: mov r5, r0
95 ; CHECK-T1-NEXT: .LBB1_2:
96 ; CHECK-T1-NEXT: cmp r1, #0
97 ; CHECK-T1-NEXT: mov r7, r4
98 ; CHECK-T1-NEXT: bge .LBB1_4
99 ; CHECK-T1-NEXT: @ %bb.3:
100 ; CHECK-T1-NEXT: mov r7, r0
101 ; CHECK-T1-NEXT: .LBB1_4:
102 ; CHECK-T1-NEXT: subs r5, r7, r5
103 ; CHECK-T1-NEXT: subs r6, r5, #1
104 ; CHECK-T1-NEXT: sbcs r5, r6
105 ; CHECK-T1-NEXT: ldr r6, [sp] @ 4-byte Reload
106 ; CHECK-T1-NEXT: subs r6, r2, r6
107 ; CHECK-T1-NEXT: sbcs r1, r3
108 ; CHECK-T1-NEXT: cmp r1, #0
109 ; CHECK-T1-NEXT: mov r2, r4
110 ; CHECK-T1-NEXT: bge .LBB1_6
111 ; CHECK-T1-NEXT: @ %bb.5:
112 ; CHECK-T1-NEXT: mov r2, r0
113 ; CHECK-T1-NEXT: .LBB1_6:
114 ; CHECK-T1-NEXT: subs r0, r7, r2
115 ; CHECK-T1-NEXT: subs r2, r0, #1
116 ; CHECK-T1-NEXT: sbcs r0, r2
117 ; CHECK-T1-NEXT: ands r5, r0
118 ; CHECK-T1-NEXT: beq .LBB1_8
119 ; CHECK-T1-NEXT: @ %bb.7:
120 ; CHECK-T1-NEXT: asrs r6, r1, #31
121 ; CHECK-T1-NEXT: .LBB1_8:
122 ; CHECK-T1-NEXT: cmp r1, #0
123 ; CHECK-T1-NEXT: bmi .LBB1_10
124 ; CHECK-T1-NEXT: @ %bb.9:
125 ; CHECK-T1-NEXT: lsls r2, r4, #31
126 ; CHECK-T1-NEXT: cmp r5, #0
127 ; CHECK-T1-NEXT: beq .LBB1_11
128 ; CHECK-T1-NEXT: b .LBB1_12
129 ; CHECK-T1-NEXT: .LBB1_10:
130 ; CHECK-T1-NEXT: ldr r2, .LCPI1_0
131 ; CHECK-T1-NEXT: cmp r5, #0
132 ; CHECK-T1-NEXT: bne .LBB1_12
133 ; CHECK-T1-NEXT: .LBB1_11:
134 ; CHECK-T1-NEXT: mov r2, r1
135 ; CHECK-T1-NEXT: .LBB1_12:
136 ; CHECK-T1-NEXT: mov r0, r6
137 ; CHECK-T1-NEXT: mov r1, r2
138 ; CHECK-T1-NEXT: add sp, #4
139 ; CHECK-T1-NEXT: pop {r4, r5, r6, r7, pc}
140 ; CHECK-T1-NEXT: .p2align 2
141 ; CHECK-T1-NEXT: @ %bb.13:
142 ; CHECK-T1-NEXT: .LCPI1_0:
143 ; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
144 ;
145 ; CHECK-T2-LABEL: func2:
146 ; CHECK-T2: @ %bb.0:
147 ; CHECK-T2-NEXT: .save {r4, lr}
148 ; CHECK-T2-NEXT: push {r4, lr}
149 ; CHECK-T2-NEXT: cmp.w r3, #-1
150 ; CHECK-T2-NEXT: mov.w lr, #0
151 ; CHECK-T2-NEXT: it gt
152 ; CHECK-T2-NEXT: movgt.w lr, #1
153 ; CHECK-T2-NEXT: cmp.w r1, #-1
154 ; CHECK-T2-NEXT: mov.w r4, #0
155 ; CHECK-T2-NEXT: mov.w r12, #0
156 ; CHECK-T2-NEXT: it gt
157 ; CHECK-T2-NEXT: movgt r4, #1
158 ; CHECK-T2-NEXT: subs.w lr, r4, lr
159 ; CHECK-T2-NEXT: it ne
160 ; CHECK-T2-NEXT: movne.w lr, #1
161 ; CHECK-T2-NEXT: subs r0, r0, r2
162 ; CHECK-T2-NEXT: sbc.w r2, r1, r3
163 ; CHECK-T2-NEXT: cmp.w r2, #-1
164 ; CHECK-T2-NEXT: it gt
165 ; CHECK-T2-NEXT: movgt.w r12, #1
166 ; CHECK-T2-NEXT: subs.w r1, r4, r12
167 ; CHECK-T2-NEXT: it ne
168 ; CHECK-T2-NEXT: movne r1, #1
169 ; CHECK-T2-NEXT: ands.w r3, lr, r1
170 ; CHECK-T2-NEXT: mov.w r1, #-2147483648
171 ; CHECK-T2-NEXT: it ne
172 ; CHECK-T2-NEXT: asrne r0, r2, #31
173 ; CHECK-T2-NEXT: cmp r2, #0
174 ; CHECK-T2-NEXT: it mi
175 ; CHECK-T2-NEXT: mvnmi r1, #-2147483648
176 ; CHECK-T2-NEXT: cmp r3, #0
177 ; CHECK-T2-NEXT: it eq
178 ; CHECK-T2-NEXT: moveq r1, r2
179 ; CHECK-T2-NEXT: pop {r4, pc}
180 ;
181 ; CHECK-ARM-LABEL: func2:
182 ; CHECK-ARM: @ %bb.0:
183 ; CHECK-ARM-NEXT: .save {r4, lr}
184 ; CHECK-ARM-NEXT: push {r4, lr}
185 ; CHECK-ARM-NEXT: cmn r3, #1
186 ; CHECK-ARM-NEXT: mov lr, #0
187 ; CHECK-ARM-NEXT: movwgt lr, #1
188 ; CHECK-ARM-NEXT: cmn r1, #1
189 ; CHECK-ARM-NEXT: mov r4, #0
190 ; CHECK-ARM-NEXT: mov r12, #0
191 ; CHECK-ARM-NEXT: movwgt r4, #1
192 ; CHECK-ARM-NEXT: subs lr, r4, lr
193 ; CHECK-ARM-NEXT: movwne lr, #1
194 ; CHECK-ARM-NEXT: subs r0, r0, r2
195 ; CHECK-ARM-NEXT: sbc r2, r1, r3
196 ; CHECK-ARM-NEXT: cmn r2, #1
197 ; CHECK-ARM-NEXT: movwgt r12, #1
198 ; CHECK-ARM-NEXT: subs r1, r4, r12
199 ; CHECK-ARM-NEXT: movwne r1, #1
200 ; CHECK-ARM-NEXT: ands r3, lr, r1
201 ; CHECK-ARM-NEXT: asrne r0, r2, #31
202 ; CHECK-ARM-NEXT: mov r1, #-2147483648
203 ; CHECK-ARM-NEXT: cmp r2, #0
204 ; CHECK-ARM-NEXT: mvnmi r1, #-2147483648
205 ; CHECK-ARM-NEXT: cmp r3, #0
206 ; CHECK-ARM-NEXT: moveq r1, r2
207 ; CHECK-ARM-NEXT: pop {r4, pc}
208 %tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %y)
209 ret i64 %tmp
210 }
212 define i16 @func16(i16 %x, i16 %y) nounwind {
213 ; CHECK-T1-LABEL: func16:
214 ; CHECK-T1: @ %bb.0:
215 ; CHECK-T1-NEXT: subs r0, r0, r1
216 ; CHECK-T1-NEXT: ldr r1, .LCPI2_0
217 ; CHECK-T1-NEXT: cmp r0, r1
218 ; CHECK-T1-NEXT: blt .LBB2_2
219 ; CHECK-T1-NEXT: @ %bb.1:
220 ; CHECK-T1-NEXT: mov r0, r1
221 ; CHECK-T1-NEXT: .LBB2_2:
222 ; CHECK-T1-NEXT: ldr r1, .LCPI2_1
223 ; CHECK-T1-NEXT: cmp r0, r1
224 ; CHECK-T1-NEXT: bgt .LBB2_4
225 ; CHECK-T1-NEXT: @ %bb.3:
226 ; CHECK-T1-NEXT: mov r0, r1
227 ; CHECK-T1-NEXT: .LBB2_4:
228 ; CHECK-T1-NEXT: bx lr
229 ; CHECK-T1-NEXT: .p2align 2
230 ; CHECK-T1-NEXT: @ %bb.5:
231 ; CHECK-T1-NEXT: .LCPI2_0:
232 ; CHECK-T1-NEXT: .long 32767 @ 0x7fff
233 ; CHECK-T1-NEXT: .LCPI2_1:
234 ; CHECK-T1-NEXT: .long 4294934528 @ 0xffff8000
235 ;
236 ; CHECK-T2-LABEL: func16:
237 ; CHECK-T2: @ %bb.0:
238 ; CHECK-T2-NEXT: subs r0, r0, r1
239 ; CHECK-T2-NEXT: movw r1, #32767
240 ; CHECK-T2-NEXT: cmp r0, r1
241 ; CHECK-T2-NEXT: it lt
242 ; CHECK-T2-NEXT: movlt r1, r0
243 ; CHECK-T2-NEXT: movw r0, #32768
244 ; CHECK-T2-NEXT: cmn.w r1, #32768
245 ; CHECK-T2-NEXT: movt r0, #65535
246 ; CHECK-T2-NEXT: it gt
247 ; CHECK-T2-NEXT: movgt r0, r1
248 ; CHECK-T2-NEXT: bx lr
249 ;
250 ; CHECK-ARM-LABEL: func16:
251 ; CHECK-ARM: @ %bb.0:
252 ; CHECK-ARM-NEXT: sub r0, r0, r1
253 ; CHECK-ARM-NEXT: movw r1, #32767
254 ; CHECK-ARM-NEXT: cmp r0, r1
255 ; CHECK-ARM-NEXT: movlt r1, r0
256 ; CHECK-ARM-NEXT: movw r0, #32768
257 ; CHECK-ARM-NEXT: movt r0, #65535
258 ; CHECK-ARM-NEXT: cmn r1, #32768
259 ; CHECK-ARM-NEXT: movgt r0, r1
260 ; CHECK-ARM-NEXT: bx lr
261 %tmp = call i16 @llvm.ssub.sat.i16(i16 %x, i16 %y)
262 ret i16 %tmp
263 }
265 define i8 @func8(i8 %x, i8 %y) nounwind {
266 ; CHECK-T1-LABEL: func8:
267 ; CHECK-T1: @ %bb.0:
268 ; CHECK-T1-NEXT: subs r0, r0, r1
269 ; CHECK-T1-NEXT: movs r1, #127
270 ; CHECK-T1-NEXT: cmp r0, #127
271 ; CHECK-T1-NEXT: blt .LBB3_2
272 ; CHECK-T1-NEXT: @ %bb.1:
273 ; CHECK-T1-NEXT: mov r0, r1
274 ; CHECK-T1-NEXT: .LBB3_2:
275 ; CHECK-T1-NEXT: mvns r1, r1
276 ; CHECK-T1-NEXT: cmp r0, r1
277 ; CHECK-T1-NEXT: bgt .LBB3_4
278 ; CHECK-T1-NEXT: @ %bb.3:
279 ; CHECK-T1-NEXT: mov r0, r1
280 ; CHECK-T1-NEXT: .LBB3_4:
281 ; CHECK-T1-NEXT: bx lr
282 ;
283 ; CHECK-T2-LABEL: func8:
284 ; CHECK-T2: @ %bb.0:
285 ; CHECK-T2-NEXT: subs r0, r0, r1
286 ; CHECK-T2-NEXT: cmp r0, #127
287 ; CHECK-T2-NEXT: it ge
288 ; CHECK-T2-NEXT: movge r0, #127
289 ; CHECK-T2-NEXT: cmn.w r0, #128
290 ; CHECK-T2-NEXT: it le
291 ; CHECK-T2-NEXT: mvnle r0, #127
292 ; CHECK-T2-NEXT: bx lr
293 ;
294 ; CHECK-ARM-LABEL: func8:
295 ; CHECK-ARM: @ %bb.0:
296 ; CHECK-ARM-NEXT: sub r0, r0, r1
297 ; CHECK-ARM-NEXT: cmp r0, #127
298 ; CHECK-ARM-NEXT: movge r0, #127
299 ; CHECK-ARM-NEXT: cmn r0, #128
300 ; CHECK-ARM-NEXT: mvnle r0, #127
301 ; CHECK-ARM-NEXT: bx lr
302 %tmp = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %y)
303 ret i8 %tmp
304 }
306 define i4 @func3(i4 %x, i4 %y) nounwind {
307 ; CHECK-T1-LABEL: func3:
308 ; CHECK-T1: @ %bb.0:
309 ; CHECK-T1-NEXT: subs r0, r0, r1
310 ; CHECK-T1-NEXT: movs r1, #7
311 ; CHECK-T1-NEXT: cmp r0, #7
312 ; CHECK-T1-NEXT: blt .LBB4_2
313 ; CHECK-T1-NEXT: @ %bb.1:
314 ; CHECK-T1-NEXT: mov r0, r1
315 ; CHECK-T1-NEXT: .LBB4_2:
316 ; CHECK-T1-NEXT: mvns r1, r1
317 ; CHECK-T1-NEXT: cmp r0, r1
318 ; CHECK-T1-NEXT: bgt .LBB4_4
319 ; CHECK-T1-NEXT: @ %bb.3:
320 ; CHECK-T1-NEXT: mov r0, r1
321 ; CHECK-T1-NEXT: .LBB4_4:
322 ; CHECK-T1-NEXT: bx lr
323 ;
324 ; CHECK-T2-LABEL: func3:
325 ; CHECK-T2: @ %bb.0:
326 ; CHECK-T2-NEXT: subs r0, r0, r1
327 ; CHECK-T2-NEXT: cmp r0, #7
328 ; CHECK-T2-NEXT: it ge
329 ; CHECK-T2-NEXT: movge r0, #7
330 ; CHECK-T2-NEXT: cmn.w r0, #8
331 ; CHECK-T2-NEXT: it le
332 ; CHECK-T2-NEXT: mvnle r0, #7
333 ; CHECK-T2-NEXT: bx lr
334 ;
335 ; CHECK-ARM-LABEL: func3:
336 ; CHECK-ARM: @ %bb.0:
337 ; CHECK-ARM-NEXT: sub r0, r0, r1
338 ; CHECK-ARM-NEXT: cmp r0, #7
339 ; CHECK-ARM-NEXT: movge r0, #7
340 ; CHECK-ARM-NEXT: cmn r0, #8
341 ; CHECK-ARM-NEXT: mvnle r0, #7
342 ; CHECK-ARM-NEXT: bx lr
343 %tmp = call i4 @llvm.ssub.sat.i4(i4 %x, i4 %y)
344 ret i4 %tmp
345 }
347 define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
348 ; CHECK-T1-LABEL: vec:
349 ; CHECK-T1: @ %bb.0:
350 ; CHECK-T1-NEXT: .save {r4, r5, r6, r7, lr}
351 ; CHECK-T1-NEXT: push {r4, r5, r6, r7, lr}
352 ; CHECK-T1-NEXT: .pad #12
353 ; CHECK-T1-NEXT: sub sp, #12
354 ; CHECK-T1-NEXT: str r3, [sp] @ 4-byte Spill
355 ; CHECK-T1-NEXT: mov r4, r1
356 ; CHECK-T1-NEXT: mov r1, r0
357 ; CHECK-T1-NEXT: ldr r5, [sp, #32]
358 ; CHECK-T1-NEXT: movs r7, #1
359 ; CHECK-T1-NEXT: movs r0, #0
360 ; CHECK-T1-NEXT: str r0, [sp, #8] @ 4-byte Spill
361 ; CHECK-T1-NEXT: subs r0, r1, r5
362 ; CHECK-T1-NEXT: str r0, [sp, #4] @ 4-byte Spill
363 ; CHECK-T1-NEXT: mov r6, r7
364 ; CHECK-T1-NEXT: bmi .LBB5_2
365 ; CHECK-T1-NEXT: @ %bb.1:
366 ; CHECK-T1-NEXT: ldr r6, [sp, #8] @ 4-byte Reload
367 ; CHECK-T1-NEXT: .LBB5_2:
368 ; CHECK-T1-NEXT: lsls r3, r7, #31
369 ; CHECK-T1-NEXT: ldr r0, .LCPI5_0
370 ; CHECK-T1-NEXT: cmp r6, #0
371 ; CHECK-T1-NEXT: mov r6, r0
372 ; CHECK-T1-NEXT: bne .LBB5_4
373 ; CHECK-T1-NEXT: @ %bb.3:
374 ; CHECK-T1-NEXT: mov r6, r3
375 ; CHECK-T1-NEXT: .LBB5_4:
376 ; CHECK-T1-NEXT: cmp r1, r5
377 ; CHECK-T1-NEXT: bvc .LBB5_6
378 ; CHECK-T1-NEXT: @ %bb.5:
379 ; CHECK-T1-NEXT: str r6, [sp, #4] @ 4-byte Spill
380 ; CHECK-T1-NEXT: .LBB5_6:
381 ; CHECK-T1-NEXT: ldr r5, [sp, #36]
382 ; CHECK-T1-NEXT: subs r1, r4, r5
383 ; CHECK-T1-NEXT: mov r6, r7
384 ; CHECK-T1-NEXT: bmi .LBB5_8
385 ; CHECK-T1-NEXT: @ %bb.7:
386 ; CHECK-T1-NEXT: ldr r6, [sp, #8] @ 4-byte Reload
387 ; CHECK-T1-NEXT: .LBB5_8:
388 ; CHECK-T1-NEXT: cmp r6, #0
389 ; CHECK-T1-NEXT: mov r6, r0
390 ; CHECK-T1-NEXT: bne .LBB5_10
391 ; CHECK-T1-NEXT: @ %bb.9:
392 ; CHECK-T1-NEXT: mov r6, r3
393 ; CHECK-T1-NEXT: .LBB5_10:
394 ; CHECK-T1-NEXT: cmp r4, r5
395 ; CHECK-T1-NEXT: bvc .LBB5_12
396 ; CHECK-T1-NEXT: @ %bb.11:
397 ; CHECK-T1-NEXT: mov r1, r6
398 ; CHECK-T1-NEXT: .LBB5_12:
399 ; CHECK-T1-NEXT: ldr r5, [sp, #40]
400 ; CHECK-T1-NEXT: subs r4, r2, r5
401 ; CHECK-T1-NEXT: mov r6, r7
402 ; CHECK-T1-NEXT: bmi .LBB5_14
403 ; CHECK-T1-NEXT: @ %bb.13:
404 ; CHECK-T1-NEXT: ldr r6, [sp, #8] @ 4-byte Reload
405 ; CHECK-T1-NEXT: .LBB5_14:
406 ; CHECK-T1-NEXT: cmp r6, #0
407 ; CHECK-T1-NEXT: mov r6, r0
408 ; CHECK-T1-NEXT: bne .LBB5_16
409 ; CHECK-T1-NEXT: @ %bb.15:
410 ; CHECK-T1-NEXT: mov r6, r3
411 ; CHECK-T1-NEXT: .LBB5_16:
412 ; CHECK-T1-NEXT: cmp r2, r5
413 ; CHECK-T1-NEXT: bvc .LBB5_18
414 ; CHECK-T1-NEXT: @ %bb.17:
415 ; CHECK-T1-NEXT: mov r4, r6
416 ; CHECK-T1-NEXT: .LBB5_18:
417 ; CHECK-T1-NEXT: ldr r2, [sp, #44]
418 ; CHECK-T1-NEXT: ldr r6, [sp] @ 4-byte Reload
419 ; CHECK-T1-NEXT: subs r5, r6, r2
420 ; CHECK-T1-NEXT: bpl .LBB5_23
421 ; CHECK-T1-NEXT: @ %bb.19:
422 ; CHECK-T1-NEXT: cmp r7, #0
423 ; CHECK-T1-NEXT: beq .LBB5_24
424 ; CHECK-T1-NEXT: .LBB5_20:
425 ; CHECK-T1-NEXT: cmp r6, r2
426 ; CHECK-T1-NEXT: bvc .LBB5_22
427 ; CHECK-T1-NEXT: .LBB5_21:
428 ; CHECK-T1-NEXT: mov r5, r0
429 ; CHECK-T1-NEXT: .LBB5_22:
430 ; CHECK-T1-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
431 ; CHECK-T1-NEXT: mov r2, r4
432 ; CHECK-T1-NEXT: mov r3, r5
433 ; CHECK-T1-NEXT: add sp, #12
434 ; CHECK-T1-NEXT: pop {r4, r5, r6, r7, pc}
435 ; CHECK-T1-NEXT: .LBB5_23:
436 ; CHECK-T1-NEXT: ldr r7, [sp, #8] @ 4-byte Reload
437 ; CHECK-T1-NEXT: cmp r7, #0
438 ; CHECK-T1-NEXT: bne .LBB5_20
439 ; CHECK-T1-NEXT: .LBB5_24:
440 ; CHECK-T1-NEXT: mov r0, r3
441 ; CHECK-T1-NEXT: cmp r6, r2
442 ; CHECK-T1-NEXT: bvs .LBB5_21
443 ; CHECK-T1-NEXT: b .LBB5_22
444 ; CHECK-T1-NEXT: .p2align 2
445 ; CHECK-T1-NEXT: @ %bb.25:
446 ; CHECK-T1-NEXT: .LCPI5_0:
447 ; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
448 ;
449 ; CHECK-T2-LABEL: vec:
450 ; CHECK-T2: @ %bb.0:
451 ; CHECK-T2-NEXT: .save {r4, r5, r6, r7, lr}
452 ; CHECK-T2-NEXT: push {r4, r5, r6, r7, lr}
453 ; CHECK-T2-NEXT: .pad #4
454 ; CHECK-T2-NEXT: sub sp, #4
455 ; CHECK-T2-NEXT: ldr r4, [sp, #24]
456 ; CHECK-T2-NEXT: mov lr, r0
457 ; CHECK-T2-NEXT: ldr r7, [sp, #28]
458 ; CHECK-T2-NEXT: movs r5, #0
459 ; CHECK-T2-NEXT: subs r6, r0, r4
460 ; CHECK-T2-NEXT: mov.w r0, #0
461 ; CHECK-T2-NEXT: it mi
462 ; CHECK-T2-NEXT: movmi r0, #1
463 ; CHECK-T2-NEXT: cmp r0, #0
464 ; CHECK-T2-NEXT: mov.w r0, #-2147483648
465 ; CHECK-T2-NEXT: mov.w r12, #-2147483648
466 ; CHECK-T2-NEXT: it ne
467 ; CHECK-T2-NEXT: mvnne r0, #-2147483648
468 ; CHECK-T2-NEXT: cmp lr, r4
469 ; CHECK-T2-NEXT: it vc
470 ; CHECK-T2-NEXT: movvc r0, r6
471 ; CHECK-T2-NEXT: subs r6, r1, r7
472 ; CHECK-T2-NEXT: mov.w r4, #0
473 ; CHECK-T2-NEXT: mov.w lr, #-2147483648
474 ; CHECK-T2-NEXT: it mi
475 ; CHECK-T2-NEXT: movmi r4, #1
476 ; CHECK-T2-NEXT: cmp r4, #0
477 ; CHECK-T2-NEXT: it ne
478 ; CHECK-T2-NEXT: mvnne lr, #-2147483648
479 ; CHECK-T2-NEXT: cmp r1, r7
480 ; CHECK-T2-NEXT: ldr r1, [sp, #32]
481 ; CHECK-T2-NEXT: mov.w r4, #0
482 ; CHECK-T2-NEXT: it vc
483 ; CHECK-T2-NEXT: movvc lr, r6
484 ; CHECK-T2-NEXT: subs r6, r2, r1
485 ; CHECK-T2-NEXT: it mi
486 ; CHECK-T2-NEXT: movmi r4, #1
487 ; CHECK-T2-NEXT: cmp r4, #0
488 ; CHECK-T2-NEXT: mov.w r4, #-2147483648
489 ; CHECK-T2-NEXT: it ne
490 ; CHECK-T2-NEXT: mvnne r4, #-2147483648
491 ; CHECK-T2-NEXT: cmp r2, r1
492 ; CHECK-T2-NEXT: ldr r1, [sp, #36]
493 ; CHECK-T2-NEXT: it vc
494 ; CHECK-T2-NEXT: movvc r4, r6
495 ; CHECK-T2-NEXT: subs r2, r3, r1
496 ; CHECK-T2-NEXT: it mi
497 ; CHECK-T2-NEXT: movmi r5, #1
498 ; CHECK-T2-NEXT: cmp r5, #0
499 ; CHECK-T2-NEXT: it ne
500 ; CHECK-T2-NEXT: mvnne r12, #-2147483648
501 ; CHECK-T2-NEXT: cmp r3, r1
502 ; CHECK-T2-NEXT: it vc
503 ; CHECK-T2-NEXT: movvc r12, r2
504 ; CHECK-T2-NEXT: mov r1, lr
505 ; CHECK-T2-NEXT: mov r2, r4
506 ; CHECK-T2-NEXT: mov r3, r12
507 ; CHECK-T2-NEXT: add sp, #4
508 ; CHECK-T2-NEXT: pop {r4, r5, r6, r7, pc}
509 ;
510 ; CHECK-ARM-LABEL: vec:
511 ; CHECK-ARM: @ %bb.0:
512 ; CHECK-ARM-NEXT: vmov d17, r2, r3
513 ; CHECK-ARM-NEXT: mov r12, sp
514 ; CHECK-ARM-NEXT: vld1.64 {d18, d19}, [r12]
515 ; CHECK-ARM-NEXT: vmov d16, r0, r1
516 ; CHECK-ARM-NEXT: vmvn.i32 q11, #0x80000000
517 ; CHECK-ARM-NEXT: vsub.i32 q10, q8, q9
518 ; CHECK-ARM-NEXT: vcgt.s32 q9, q9, #0
519 ; CHECK-ARM-NEXT: vclt.s32 q12, q10, #0
520 ; CHECK-ARM-NEXT: vmvn q13, q12
521 ; CHECK-ARM-NEXT: vcgt.s32 q8, q8, q10
522 ; CHECK-ARM-NEXT: vbsl q11, q12, q13
523 ; CHECK-ARM-NEXT: veor q8, q9, q8
524 ; CHECK-ARM-NEXT: vbsl q8, q11, q10
525 ; CHECK-ARM-NEXT: vmov r0, r1, d16
526 ; CHECK-ARM-NEXT: vmov r2, r3, d17
527 ; CHECK-ARM-NEXT: bx lr
528 %tmp = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
529 ret <4 x i32> %tmp
530 }