lib/Target/X86/X86FixupSetCC.cpp

   1 //===---- X86FixupSetCC.cpp - optimize usage of LEA instructions ----------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines a pass that fixes zero-extension of setcc patterns.
  10 // X86 setcc instructions are modeled to have no input arguments, and a single
  11 // GR8 output argument. This is consistent with other similar instructions
  12 // (e.g. movb), but means it is impossible to directly generate a setcc into
  13 // the lower GR8 of a specified GR32.
  14 // This means that ISel must select (zext (setcc)) into something like
  15 // seta %al; movzbl %al, %eax.
  16 // Unfortunately, this can cause a stall due to the partial register write
  17 // performed by the setcc. Instead, we can use:
  18 // xor %eax, %eax; seta %al
  19 // This both avoids the stall, and encodes shorter.
  20 //===----------------------------------------------------------------------===//
  21
  22 #include "X86.h"
  23 #include "X86InstrInfo.h"
  24 #include "X86Subtarget.h"
  25 #include "llvm/ADT/Statistic.h"
  26 #include "llvm/CodeGen/MachineFunctionPass.h"
  27 #include "llvm/CodeGen/MachineInstrBuilder.h"
  28 #include "llvm/CodeGen/MachineRegisterInfo.h"
  29
  30 using namespace llvm;
  31
  32 #define DEBUG_TYPE "x86-fixup-setcc"
  33
  34 STATISTIC(NumSubstZexts, "Number of setcc + zext pairs substituted");
  35
  36 namespace {
  37 class X86FixupSetCCPass : public MachineFunctionPass {
  38 public:
  39   X86FixupSetCCPass() : MachineFunctionPass(ID) {}
  40
  41   StringRef getPassName() const override { return "X86 Fixup SetCC"; }
  42
  43   bool runOnMachineFunction(MachineFunction &MF) override;
  44
  45 private:
  46   // Find the preceding instruction that imp-defs eflags.
  47   MachineInstr *findFlagsImpDef(MachineBasicBlock *MBB,
  48                                 MachineBasicBlock::reverse_iterator MI);
  49
  50   // Return true if MI imp-uses eflags.
  51   bool impUsesFlags(MachineInstr *MI);
  52
  53   // Return true if this is the opcode of a SetCC instruction with a register
  54   // output.
  55   bool isSetCCr(unsigned Opode);
  56
  57   MachineRegisterInfo *MRI;
  58   const X86InstrInfo *TII;
  59
  60   enum { SearchBound = 16 };
  61
  62   static char ID;
  63 };
  64
  65 char X86FixupSetCCPass::ID = 0;
  66 }
  67
  68 FunctionPass *llvm::createX86FixupSetCC() { return new X86FixupSetCCPass(); }
  69
  70 // We expect the instruction *immediately* before the setcc to imp-def
  71 // EFLAGS (because of scheduling glue). To make this less brittle w.r.t
  72 // scheduling, look backwards until we hit the beginning of the
  73 // basic-block, or a small bound (to avoid quadratic behavior).
  74 MachineInstr *
  75 X86FixupSetCCPass::findFlagsImpDef(MachineBasicBlock *MBB,
  76                                    MachineBasicBlock::reverse_iterator MI) {
  77   // FIXME: Should this be instr_rend(), and MI be reverse_instr_iterator?
  78   auto MBBStart = MBB->rend();
  79   for (int i = 0; (i < SearchBound) && (MI != MBBStart); ++i, ++MI)
  80     for (auto &Op : MI->implicit_operands())
  81       if (Op.isReg() && (Op.getReg() == X86::EFLAGS) && Op.isDef())
  82         return &*MI;
  83
  84   return nullptr;
  85 }
  86
  87 bool X86FixupSetCCPass::impUsesFlags(MachineInstr *MI) {
  88   for (auto &Op : MI->implicit_operands())
  89     if (Op.isReg() && (Op.getReg() == X86::EFLAGS) && Op.isUse())
  90       return true;
  91
  92   return false;
  93 }
  94
  95 bool X86FixupSetCCPass::runOnMachineFunction(MachineFunction &MF) {
  96   bool Changed = false;
  97   MRI = &MF.getRegInfo();
  98   TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
  99
 100   SmallVector<MachineInstr*, 4> ToErase;
 101
 102   for (auto &MBB : MF) {
 103     for (auto &MI : MBB) {
 104       // Find a setcc that is used by a zext.
 105       // This doesn't have to be the only use, the transformation is safe
 106       // regardless.
 107       if (MI.getOpcode() != X86::SETCCr)
 108         continue;
 109
 110       MachineInstr *ZExt = nullptr;
 111       for (auto &Use : MRI->use_instructions(MI.getOperand(0).getReg()))
 112         if (Use.getOpcode() == X86::MOVZX32rr8)
 113           ZExt = &Use;
 114
 115       if (!ZExt)
 116         continue;
 117
 118       // Find the preceding instruction that imp-defs eflags.
 119       MachineInstr *FlagsDefMI = findFlagsImpDef(
 120           MI.getParent(), MachineBasicBlock::reverse_iterator(&MI));
 121       if (!FlagsDefMI)
 122         continue;
 123
 124       // We'd like to put something that clobbers eflags directly before
 125       // FlagsDefMI. This can't hurt anything after FlagsDefMI, because
 126       // it, itself, by definition, clobbers eflags. But it may happen that
 127       // FlagsDefMI also *uses* eflags, in which case the transformation is
 128       // invalid.
 129       if (impUsesFlags(FlagsDefMI))
 130         continue;
 131
 132       ++NumSubstZexts;
 133       Changed = true;
 134
 135       // On 32-bit, we need to be careful to force an ABCD register.
 136       const TargetRegisterClass *RC = MF.getSubtarget<X86Subtarget>().is64Bit()
 137                                           ? &X86::GR32RegClass
 138                                           : &X86::GR32_ABCDRegClass;
 139       Register ZeroReg = MRI->createVirtualRegister(RC);
 140       Register InsertReg = MRI->createVirtualRegister(RC);
 141
 142       // Initialize a register with 0. This must go before the eflags def
 143       BuildMI(MBB, FlagsDefMI, MI.getDebugLoc(), TII->get(X86::MOV32r0),
 144               ZeroReg);
 145
 146       // X86 setcc only takes an output GR8, so fake a GR32 input by inserting
 147       // the setcc result into the low byte of the zeroed register.
 148       BuildMI(*ZExt->getParent(), ZExt, ZExt->getDebugLoc(),
 149               TII->get(X86::INSERT_SUBREG), InsertReg)
 150           .addReg(ZeroReg)
 151           .addReg(MI.getOperand(0).getReg())
 152           .addImm(X86::sub_8bit);
 153       MRI->replaceRegWith(ZExt->getOperand(0).getReg(), InsertReg);
 154       ToErase.push_back(ZExt);
 155     }
 156   }
 157
 158   for (auto &I : ToErase)
 159     I->eraseFromParent();
 160
 161   return Changed;
 162 }