1 ; RUN: llc < %s -regalloc=fast -optimize-regalloc=0 -no-integrated-as | FileCheck %s
2 ; RUN: llc < %s -regalloc=basic -no-integrated-as | FileCheck %s
3 ; RUN: llc < %s -regalloc=greedy -no-integrated-as | FileCheck %s
5 ; The 1st, 2nd, 3rd and 5th registers must all be different. The registers
6 ; referenced in the 4th and 6th operands must not be the same as the 1st or 5th
9 ; CHECK: 1st=[[A1:%...]]
11 ; CHECK: 2nd=[[A2:%...]]
14 ; CHECK: 3rd=[[A3:%...]]
18 ; CHECK: 5th=[[A5:%...]]
23 ; The 6th operand is an 8-bit register, and it mustn't alias the 1st and 5th.
29 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
30 target triple = "i386-apple-darwin8"
31 %struct.foo = type { i32, i32, i8* }
33 define i32 @get(%struct.foo* %c, i8* %state) nounwind {
35 %0 = getelementptr %struct.foo, %struct.foo* %c, i32 0, i32 0 ; <i32*> [#uses=2]
36 %1 = getelementptr %struct.foo, %struct.foo* %c, i32 0, i32 1 ; <i32*> [#uses=2]
37 %2 = getelementptr %struct.foo, %struct.foo* %c, i32 0, i32 2 ; <i8**> [#uses=2]
38 %3 = load i32, i32* %0, align 4 ; <i32> [#uses=1]
39 %4 = load i32, i32* %1, align 4 ; <i32> [#uses=1]
40 %5 = load i8, i8* %state, align 1 ; <i8> [#uses=1]
41 %asmtmp = tail call { i32, i32, i32, i32 } asm sideeffect "#1st=$0 $1 2nd=$1 $2 3rd=$2 $4 5th=$4 $3=4th 1$0 1%eXx 5$4 5%eXx 6th=$5", "=&r,=r,=r,=*m,=&q,=*imr,1,2,*m,5,~{dirflag},~{fpsr},~{flags},~{cx}"(i8** %2, i8* %state, i32 %3, i32 %4, i8** %2, i8 %5) nounwind ; <{ i32, i32, i32, i32 }> [#uses=3]
42 %asmresult = extractvalue { i32, i32, i32, i32 } %asmtmp, 0 ; <i32> [#uses=1]
43 %asmresult1 = extractvalue { i32, i32, i32, i32 } %asmtmp, 1 ; <i32> [#uses=1]
44 store i32 %asmresult1, i32* %0
45 %asmresult2 = extractvalue { i32, i32, i32, i32 } %asmtmp, 2 ; <i32> [#uses=1]
46 store i32 %asmresult2, i32* %1