lib/Analysis/TargetTransformInfo.cpp

   1 //===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 #include "llvm/Analysis/TargetTransformInfo.h"
  10 #include "llvm/Analysis/TargetTransformInfoImpl.h"
  11 #include "llvm/IR/CallSite.h"
  12 #include "llvm/IR/DataLayout.h"
  13 #include "llvm/IR/Instruction.h"
  14 #include "llvm/IR/Instructions.h"
  15 #include "llvm/IR/IntrinsicInst.h"
  16 #include "llvm/IR/Module.h"
  17 #include "llvm/IR/Operator.h"
  18 #include "llvm/IR/PatternMatch.h"
  19 #include "llvm/Support/CommandLine.h"
  20 #include "llvm/Support/ErrorHandling.h"
  21 #include "llvm/Analysis/CFG.h"
  22 #include "llvm/Analysis/LoopIterator.h"
  23 #include <utility>
  24
  25 using namespace llvm;
  26 using namespace PatternMatch;
  27
  28 #define DEBUG_TYPE "tti"
  29
  30 static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
  31                                      cl::Hidden,
  32                                      cl::desc("Recognize reduction patterns."));
  33
  34 namespace {
  35 /// No-op implementation of the TTI interface using the utility base
  36 /// classes.
  37 ///
  38 /// This is used when no target specific information is available.
  39 struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
  40   explicit NoTTIImpl(const DataLayout &DL)
  41       : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
  42 };
  43 }
  44
  45 bool HardwareLoopInfo::canAnalyze(LoopInfo &LI) {
  46   // If the loop has irreducible control flow, it can not be converted to
  47   // Hardware loop.
  48   LoopBlocksRPO RPOT(L);
  49   RPOT.perform(&LI);
  50   if (containsIrreducibleCFG<const BasicBlock *>(RPOT, LI))
  51     return false;
  52   return true;
  53 }
  54
  55 bool HardwareLoopInfo::isHardwareLoopCandidate(ScalarEvolution &SE,
  56                                                LoopInfo &LI, DominatorTree &DT,
  57                                                bool ForceNestedLoop,
  58                                                bool ForceHardwareLoopPHI) {
  59   SmallVector<BasicBlock *, 4> ExitingBlocks;
  60   L->getExitingBlocks(ExitingBlocks);
  61
  62   for (SmallVectorImpl<BasicBlock *>::iterator I = ExitingBlocks.begin(),
  63                                                IE = ExitingBlocks.end();
  64        I != IE; ++I) {
  65     BasicBlock *BB = *I;
  66
  67     // If we pass the updated counter back through a phi, we need to know
  68     // which latch the updated value will be coming from.
  69     if (!L->isLoopLatch(BB)) {
  70       if (ForceHardwareLoopPHI || CounterInReg)
  71         continue;
  72     }
  73
  74     const SCEV *EC = SE.getExitCount(L, BB);
  75     if (isa<SCEVCouldNotCompute>(EC))
  76       continue;
  77     if (const SCEVConstant *ConstEC = dyn_cast<SCEVConstant>(EC)) {
  78       if (ConstEC->getValue()->isZero())
  79         continue;
  80     } else if (!SE.isLoopInvariant(EC, L))
  81       continue;
  82
  83     if (SE.getTypeSizeInBits(EC->getType()) > CountType->getBitWidth())
  84       continue;
  85
  86     // If this exiting block is contained in a nested loop, it is not eligible
  87     // for insertion of the branch-and-decrement since the inner loop would
  88     // end up messing up the value in the CTR.
  89     if (!IsNestingLegal && LI.getLoopFor(BB) != L && !ForceNestedLoop)
  90       continue;
  91
  92     // We now have a loop-invariant count of loop iterations (which is not the
  93     // constant zero) for which we know that this loop will not exit via this
  94     // existing block.
  95
  96     // We need to make sure that this block will run on every loop iteration.
  97     // For this to be true, we must dominate all blocks with backedges. Such
  98     // blocks are in-loop predecessors to the header block.
  99     bool NotAlways = false;
 100     for (pred_iterator PI = pred_begin(L->getHeader()),
 101                        PIE = pred_end(L->getHeader());
 102          PI != PIE; ++PI) {
 103       if (!L->contains(*PI))
 104         continue;
 105
 106       if (!DT.dominates(*I, *PI)) {
 107         NotAlways = true;
 108         break;
 109       }
 110     }
 111
 112     if (NotAlways)
 113       continue;
 114
 115     // Make sure this blocks ends with a conditional branch.
 116     Instruction *TI = BB->getTerminator();
 117     if (!TI)
 118       continue;
 119
 120     if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
 121       if (!BI->isConditional())
 122         continue;
 123
 124       ExitBranch = BI;
 125     } else
 126       continue;
 127
 128     // Note that this block may not be the loop latch block, even if the loop
 129     // has a latch block.
 130     ExitBlock = *I;
 131     ExitCount = EC;
 132     break;
 133   }
 134
 135   if (!ExitBlock)
 136     return false;
 137   return true;
 138 }
 139
 140 TargetTransformInfo::TargetTransformInfo(const DataLayout &DL)
 141     : TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {}
 142
 143 TargetTransformInfo::~TargetTransformInfo() {}
 144
 145 TargetTransformInfo::TargetTransformInfo(TargetTransformInfo &&Arg)
 146     : TTIImpl(std::move(Arg.TTIImpl)) {}
 147
 148 TargetTransformInfo &TargetTransformInfo::operator=(TargetTransformInfo &&RHS) {
 149   TTIImpl = std::move(RHS.TTIImpl);
 150   return *this;
 151 }
 152
 153 int TargetTransformInfo::getOperationCost(unsigned Opcode, Type *Ty,
 154                                           Type *OpTy) const {
 155   int Cost = TTIImpl->getOperationCost(Opcode, Ty, OpTy);
 156   assert(Cost >= 0 && "TTI should not produce negative costs!");
 157   return Cost;
 158 }
 159
 160 int TargetTransformInfo::getCallCost(FunctionType *FTy, int NumArgs,
 161                                      const User *U) const {
 162   int Cost = TTIImpl->getCallCost(FTy, NumArgs, U);
 163   assert(Cost >= 0 && "TTI should not produce negative costs!");
 164   return Cost;
 165 }
 166
 167 int TargetTransformInfo::getCallCost(const Function *F,
 168                                      ArrayRef<const Value *> Arguments,
 169                                      const User *U) const {
 170   int Cost = TTIImpl->getCallCost(F, Arguments, U);
 171   assert(Cost >= 0 && "TTI should not produce negative costs!");
 172   return Cost;
 173 }
 174
 175 unsigned TargetTransformInfo::getInliningThresholdMultiplier() const {
 176   return TTIImpl->getInliningThresholdMultiplier();
 177 }
 178
 179 int TargetTransformInfo::getInlinerVectorBonusPercent() const {
 180   return TTIImpl->getInlinerVectorBonusPercent();
 181 }
 182
 183 int TargetTransformInfo::getGEPCost(Type *PointeeType, const Value *Ptr,
 184                                     ArrayRef<const Value *> Operands) const {
 185   return TTIImpl->getGEPCost(PointeeType, Ptr, Operands);
 186 }
 187
 188 int TargetTransformInfo::getExtCost(const Instruction *I,
 189                                     const Value *Src) const {
 190   return TTIImpl->getExtCost(I, Src);
 191 }
 192
 193 int TargetTransformInfo::getIntrinsicCost(
 194     Intrinsic::ID IID, Type *RetTy, ArrayRef<const Value *> Arguments,
 195     const User *U) const {
 196   int Cost = TTIImpl->getIntrinsicCost(IID, RetTy, Arguments, U);
 197   assert(Cost >= 0 && "TTI should not produce negative costs!");
 198   return Cost;
 199 }
 200
 201 unsigned
 202 TargetTransformInfo::getEstimatedNumberOfCaseClusters(const SwitchInst &SI,
 203                                                       unsigned &JTSize) const {
 204   return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize);
 205 }
 206
 207 int TargetTransformInfo::getUserCost(const User *U,
 208     ArrayRef<const Value *> Operands) const {
 209   int Cost = TTIImpl->getUserCost(U, Operands);
 210   assert(Cost >= 0 && "TTI should not produce negative costs!");
 211   return Cost;
 212 }
 213
 214 bool TargetTransformInfo::hasBranchDivergence() const {
 215   return TTIImpl->hasBranchDivergence();
 216 }
 217
 218 bool TargetTransformInfo::isSourceOfDivergence(const Value *V) const {
 219   return TTIImpl->isSourceOfDivergence(V);
 220 }
 221
 222 bool llvm::TargetTransformInfo::isAlwaysUniform(const Value *V) const {
 223   return TTIImpl->isAlwaysUniform(V);
 224 }
 225
 226 unsigned TargetTransformInfo::getFlatAddressSpace() const {
 227   return TTIImpl->getFlatAddressSpace();
 228 }
 229
 230 bool TargetTransformInfo::isLoweredToCall(const Function *F) const {
 231   return TTIImpl->isLoweredToCall(F);
 232 }
 233
 234 bool TargetTransformInfo::isHardwareLoopProfitable(
 235   Loop *L, ScalarEvolution &SE, AssumptionCache &AC,
 236   TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const {
 237   return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
 238 }
 239
 240 void TargetTransformInfo::getUnrollingPreferences(
 241     Loop *L, ScalarEvolution &SE, UnrollingPreferences &UP) const {
 242   return TTIImpl->getUnrollingPreferences(L, SE, UP);
 243 }
 244
 245 bool TargetTransformInfo::isLegalAddImmediate(int64_t Imm) const {
 246   return TTIImpl->isLegalAddImmediate(Imm);
 247 }
 248
 249 bool TargetTransformInfo::isLegalICmpImmediate(int64_t Imm) const {
 250   return TTIImpl->isLegalICmpImmediate(Imm);
 251 }
 252
 253 bool TargetTransformInfo::isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
 254                                                 int64_t BaseOffset,
 255                                                 bool HasBaseReg,
 256                                                 int64_t Scale,
 257                                                 unsigned AddrSpace,
 258                                                 Instruction *I) const {
 259   return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
 260                                         Scale, AddrSpace, I);
 261 }
 262
 263 bool TargetTransformInfo::isLSRCostLess(LSRCost &C1, LSRCost &C2) const {
 264   return TTIImpl->isLSRCostLess(C1, C2);
 265 }
 266
 267 bool TargetTransformInfo::canMacroFuseCmp() const {
 268   return TTIImpl->canMacroFuseCmp();
 269 }
 270
 271 bool TargetTransformInfo::canSaveCmp(Loop *L, BranchInst **BI,
 272                                      ScalarEvolution *SE, LoopInfo *LI,
 273                                      DominatorTree *DT, AssumptionCache *AC,
 274                                      TargetLibraryInfo *LibInfo) const {
 275   return TTIImpl->canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo);
 276 }
 277
 278 bool TargetTransformInfo::shouldFavorPostInc() const {
 279   return TTIImpl->shouldFavorPostInc();
 280 }
 281
 282 bool TargetTransformInfo::shouldFavorBackedgeIndex(const Loop *L) const {
 283   return TTIImpl->shouldFavorBackedgeIndex(L);
 284 }
 285
 286 bool TargetTransformInfo::isLegalMaskedStore(Type *DataType) const {
 287   return TTIImpl->isLegalMaskedStore(DataType);
 288 }
 289
 290 bool TargetTransformInfo::isLegalMaskedLoad(Type *DataType) const {
 291   return TTIImpl->isLegalMaskedLoad(DataType);
 292 }
 293
 294 bool TargetTransformInfo::isLegalNTStore(Type *DataType,
 295                                          unsigned Alignment) const {
 296   return TTIImpl->isLegalNTStore(DataType, Alignment);
 297 }
 298
 299 bool TargetTransformInfo::isLegalNTLoad(Type *DataType,
 300                                         unsigned Alignment) const {
 301   return TTIImpl->isLegalNTLoad(DataType, Alignment);
 302 }
 303
 304 bool TargetTransformInfo::isLegalMaskedGather(Type *DataType) const {
 305   return TTIImpl->isLegalMaskedGather(DataType);
 306 }
 307
 308 bool TargetTransformInfo::isLegalMaskedScatter(Type *DataType) const {
 309   return TTIImpl->isLegalMaskedScatter(DataType);
 310 }
 311
 312 bool TargetTransformInfo::isLegalMaskedCompressStore(Type *DataType) const {
 313   return TTIImpl->isLegalMaskedCompressStore(DataType);
 314 }
 315
 316 bool TargetTransformInfo::isLegalMaskedExpandLoad(Type *DataType) const {
 317   return TTIImpl->isLegalMaskedExpandLoad(DataType);
 318 }
 319
 320 bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
 321   return TTIImpl->hasDivRemOp(DataType, IsSigned);
 322 }
 323
 324 bool TargetTransformInfo::hasVolatileVariant(Instruction *I,
 325                                              unsigned AddrSpace) const {
 326   return TTIImpl->hasVolatileVariant(I, AddrSpace);
 327 }
 328
 329 bool TargetTransformInfo::prefersVectorizedAddressing() const {
 330   return TTIImpl->prefersVectorizedAddressing();
 331 }
 332
 333 int TargetTransformInfo::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
 334                                               int64_t BaseOffset,
 335                                               bool HasBaseReg,
 336                                               int64_t Scale,
 337                                               unsigned AddrSpace) const {
 338   int Cost = TTIImpl->getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg,
 339                                            Scale, AddrSpace);
 340   assert(Cost >= 0 && "TTI should not produce negative costs!");
 341   return Cost;
 342 }
 343
 344 bool TargetTransformInfo::LSRWithInstrQueries() const {
 345   return TTIImpl->LSRWithInstrQueries();
 346 }
 347
 348 bool TargetTransformInfo::isTruncateFree(Type *Ty1, Type *Ty2) const {
 349   return TTIImpl->isTruncateFree(Ty1, Ty2);
 350 }
 351
 352 bool TargetTransformInfo::isProfitableToHoist(Instruction *I) const {
 353   return TTIImpl->isProfitableToHoist(I);
 354 }
 355
 356 bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
 357
 358 bool TargetTransformInfo::isTypeLegal(Type *Ty) const {
 359   return TTIImpl->isTypeLegal(Ty);
 360 }
 361
 362 unsigned TargetTransformInfo::getJumpBufAlignment() const {
 363   return TTIImpl->getJumpBufAlignment();
 364 }
 365
 366 unsigned TargetTransformInfo::getJumpBufSize() const {
 367   return TTIImpl->getJumpBufSize();
 368 }
 369
 370 bool TargetTransformInfo::shouldBuildLookupTables() const {
 371   return TTIImpl->shouldBuildLookupTables();
 372 }
 373 bool TargetTransformInfo::shouldBuildLookupTablesForConstant(Constant *C) const {
 374   return TTIImpl->shouldBuildLookupTablesForConstant(C);
 375 }
 376
 377 bool TargetTransformInfo::useColdCCForColdCall(Function &F) const {
 378   return TTIImpl->useColdCCForColdCall(F);
 379 }
 380
 381 unsigned TargetTransformInfo::
 382 getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const {
 383   return TTIImpl->getScalarizationOverhead(Ty, Insert, Extract);
 384 }
 385
 386 unsigned TargetTransformInfo::
 387 getOperandsScalarizationOverhead(ArrayRef<const Value *> Args,
 388                                  unsigned VF) const {
 389   return TTIImpl->getOperandsScalarizationOverhead(Args, VF);
 390 }
 391
 392 bool TargetTransformInfo::supportsEfficientVectorElementLoadStore() const {
 393   return TTIImpl->supportsEfficientVectorElementLoadStore();
 394 }
 395
 396 bool TargetTransformInfo::enableAggressiveInterleaving(bool LoopHasReductions) const {
 397   return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
 398 }
 399
 400 TargetTransformInfo::MemCmpExpansionOptions
 401 TargetTransformInfo::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
 402   return TTIImpl->enableMemCmpExpansion(OptSize, IsZeroCmp);
 403 }
 404
 405 bool TargetTransformInfo::enableInterleavedAccessVectorization() const {
 406   return TTIImpl->enableInterleavedAccessVectorization();
 407 }
 408
 409 bool TargetTransformInfo::enableMaskedInterleavedAccessVectorization() const {
 410   return TTIImpl->enableMaskedInterleavedAccessVectorization();
 411 }
 412
 413 bool TargetTransformInfo::isFPVectorizationPotentiallyUnsafe() const {
 414   return TTIImpl->isFPVectorizationPotentiallyUnsafe();
 415 }
 416
 417 bool TargetTransformInfo::allowsMisalignedMemoryAccesses(LLVMContext &Context,
 418                                                          unsigned BitWidth,
 419                                                          unsigned AddressSpace,
 420                                                          unsigned Alignment,
 421                                                          bool *Fast) const {
 422   return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth, AddressSpace,
 423                                                  Alignment, Fast);
 424 }
 425
 426 TargetTransformInfo::PopcntSupportKind
 427 TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
 428   return TTIImpl->getPopcntSupport(IntTyWidthInBit);
 429 }
 430
 431 bool TargetTransformInfo::haveFastSqrt(Type *Ty) const {
 432   return TTIImpl->haveFastSqrt(Ty);
 433 }
 434
 435 bool TargetTransformInfo::isFCmpOrdCheaperThanFCmpZero(Type *Ty) const {
 436   return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
 437 }
 438
 439 int TargetTransformInfo::getFPOpCost(Type *Ty) const {
 440   int Cost = TTIImpl->getFPOpCost(Ty);
 441   assert(Cost >= 0 && "TTI should not produce negative costs!");
 442   return Cost;
 443 }
 444
 445 int TargetTransformInfo::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
 446                                                const APInt &Imm,
 447                                                Type *Ty) const {
 448   int Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
 449   assert(Cost >= 0 && "TTI should not produce negative costs!");
 450   return Cost;
 451 }
 452
 453 int TargetTransformInfo::getIntImmCost(const APInt &Imm, Type *Ty) const {
 454   int Cost = TTIImpl->getIntImmCost(Imm, Ty);
 455   assert(Cost >= 0 && "TTI should not produce negative costs!");
 456   return Cost;
 457 }
 458
 459 int TargetTransformInfo::getIntImmCost(unsigned Opcode, unsigned Idx,
 460                                        const APInt &Imm, Type *Ty) const {
 461   int Cost = TTIImpl->getIntImmCost(Opcode, Idx, Imm, Ty);
 462   assert(Cost >= 0 && "TTI should not produce negative costs!");
 463   return Cost;
 464 }
 465
 466 int TargetTransformInfo::getIntImmCost(Intrinsic::ID IID, unsigned Idx,
 467                                        const APInt &Imm, Type *Ty) const {
 468   int Cost = TTIImpl->getIntImmCost(IID, Idx, Imm, Ty);
 469   assert(Cost >= 0 && "TTI should not produce negative costs!");
 470   return Cost;
 471 }
 472
 473 unsigned TargetTransformInfo::getNumberOfRegisters(bool Vector) const {
 474   return TTIImpl->getNumberOfRegisters(Vector);
 475 }
 476
 477 unsigned TargetTransformInfo::getRegisterBitWidth(bool Vector) const {
 478   return TTIImpl->getRegisterBitWidth(Vector);
 479 }
 480
 481 unsigned TargetTransformInfo::getMinVectorRegisterBitWidth() const {
 482   return TTIImpl->getMinVectorRegisterBitWidth();
 483 }
 484
 485 bool TargetTransformInfo::shouldMaximizeVectorBandwidth(bool OptSize) const {
 486   return TTIImpl->shouldMaximizeVectorBandwidth(OptSize);
 487 }
 488
 489 unsigned TargetTransformInfo::getMinimumVF(unsigned ElemWidth) const {
 490   return TTIImpl->getMinimumVF(ElemWidth);
 491 }
 492
 493 bool TargetTransformInfo::shouldConsiderAddressTypePromotion(
 494     const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
 495   return TTIImpl->shouldConsiderAddressTypePromotion(
 496       I, AllowPromotionWithoutCommonHeader);
 497 }
 498
 499 unsigned TargetTransformInfo::getCacheLineSize() const {
 500   return TTIImpl->getCacheLineSize();
 501 }
 502
 503 llvm::Optional<unsigned> TargetTransformInfo::getCacheSize(CacheLevel Level)
 504   const {
 505   return TTIImpl->getCacheSize(Level);
 506 }
 507
 508 llvm::Optional<unsigned> TargetTransformInfo::getCacheAssociativity(
 509   CacheLevel Level) const {
 510   return TTIImpl->getCacheAssociativity(Level);
 511 }
 512
 513 unsigned TargetTransformInfo::getPrefetchDistance() const {
 514   return TTIImpl->getPrefetchDistance();
 515 }
 516
 517 unsigned TargetTransformInfo::getMinPrefetchStride() const {
 518   return TTIImpl->getMinPrefetchStride();
 519 }
 520
 521 unsigned TargetTransformInfo::getMaxPrefetchIterationsAhead() const {
 522   return TTIImpl->getMaxPrefetchIterationsAhead();
 523 }
 524
 525 unsigned TargetTransformInfo::getMaxInterleaveFactor(unsigned VF) const {
 526   return TTIImpl->getMaxInterleaveFactor(VF);
 527 }
 528
 529 TargetTransformInfo::OperandValueKind
 530 TargetTransformInfo::getOperandInfo(Value *V, OperandValueProperties &OpProps) {
 531   OperandValueKind OpInfo = OK_AnyValue;
 532   OpProps = OP_None;
 533
 534   if (auto *CI = dyn_cast<ConstantInt>(V)) {
 535     if (CI->getValue().isPowerOf2())
 536       OpProps = OP_PowerOf2;
 537     return OK_UniformConstantValue;
 538   }
 539
 540   // A broadcast shuffle creates a uniform value.
 541   // TODO: Add support for non-zero index broadcasts.
 542   // TODO: Add support for different source vector width.
 543   if (auto *ShuffleInst = dyn_cast<ShuffleVectorInst>(V))
 544     if (ShuffleInst->isZeroEltSplat())
 545       OpInfo = OK_UniformValue;
 546
 547   const Value *Splat = getSplatValue(V);
 548
 549   // Check for a splat of a constant or for a non uniform vector of constants
 550   // and check if the constant(s) are all powers of two.
 551   if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
 552     OpInfo = OK_NonUniformConstantValue;
 553     if (Splat) {
 554       OpInfo = OK_UniformConstantValue;
 555       if (auto *CI = dyn_cast<ConstantInt>(Splat))
 556         if (CI->getValue().isPowerOf2())
 557           OpProps = OP_PowerOf2;
 558     } else if (auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
 559       OpProps = OP_PowerOf2;
 560       for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I) {
 561         if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I)))
 562           if (CI->getValue().isPowerOf2())
 563             continue;
 564         OpProps = OP_None;
 565         break;
 566       }
 567     }
 568   }
 569
 570   // Check for a splat of a uniform value. This is not loop aware, so return
 571   // true only for the obviously uniform cases (argument, globalvalue)
 572   if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat)))
 573     OpInfo = OK_UniformValue;
 574
 575   return OpInfo;
 576 }
 577
 578 int TargetTransformInfo::getArithmeticInstrCost(
 579     unsigned Opcode, Type *Ty, OperandValueKind Opd1Info,
 580     OperandValueKind Opd2Info, OperandValueProperties Opd1PropInfo,
 581     OperandValueProperties Opd2PropInfo,
 582     ArrayRef<const Value *> Args) const {
 583   int Cost = TTIImpl->getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
 584                                              Opd1PropInfo, Opd2PropInfo, Args);
 585   assert(Cost >= 0 && "TTI should not produce negative costs!");
 586   return Cost;
 587 }
 588
 589 int TargetTransformInfo::getShuffleCost(ShuffleKind Kind, Type *Ty, int Index,
 590                                         Type *SubTp) const {
 591   int Cost = TTIImpl->getShuffleCost(Kind, Ty, Index, SubTp);
 592   assert(Cost >= 0 && "TTI should not produce negative costs!");
 593   return Cost;
 594 }
 595
 596 int TargetTransformInfo::getCastInstrCost(unsigned Opcode, Type *Dst,
 597                                  Type *Src, const Instruction *I) const {
 598   assert ((I == nullptr || I->getOpcode() == Opcode) &&
 599           "Opcode should reflect passed instruction.");
 600   int Cost = TTIImpl->getCastInstrCost(Opcode, Dst, Src, I);
 601   assert(Cost >= 0 && "TTI should not produce negative costs!");
 602   return Cost;
 603 }
 604
 605 int TargetTransformInfo::getExtractWithExtendCost(unsigned Opcode, Type *Dst,
 606                                                   VectorType *VecTy,
 607                                                   unsigned Index) const {
 608   int Cost = TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index);
 609   assert(Cost >= 0 && "TTI should not produce negative costs!");
 610   return Cost;
 611 }
 612
 613 int TargetTransformInfo::getCFInstrCost(unsigned Opcode) const {
 614   int Cost = TTIImpl->getCFInstrCost(Opcode);
 615   assert(Cost >= 0 && "TTI should not produce negative costs!");
 616   return Cost;
 617 }
 618
 619 int TargetTransformInfo::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
 620                                  Type *CondTy, const Instruction *I) const {
 621   assert ((I == nullptr || I->getOpcode() == Opcode) &&
 622           "Opcode should reflect passed instruction.");
 623   int Cost = TTIImpl->getCmpSelInstrCost(Opcode, ValTy, CondTy, I);
 624   assert(Cost >= 0 && "TTI should not produce negative costs!");
 625   return Cost;
 626 }
 627
 628 int TargetTransformInfo::getVectorInstrCost(unsigned Opcode, Type *Val,
 629                                             unsigned Index) const {
 630   int Cost = TTIImpl->getVectorInstrCost(Opcode, Val, Index);
 631   assert(Cost >= 0 && "TTI should not produce negative costs!");
 632   return Cost;
 633 }
 634
 635 int TargetTransformInfo::getMemoryOpCost(unsigned Opcode, Type *Src,
 636                                          unsigned Alignment,
 637                                          unsigned AddressSpace,
 638                                          const Instruction *I) const {
 639   assert ((I == nullptr || I->getOpcode() == Opcode) &&
 640           "Opcode should reflect passed instruction.");
 641   int Cost = TTIImpl->getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, I);
 642   assert(Cost >= 0 && "TTI should not produce negative costs!");
 643   return Cost;
 644 }
 645
 646 int TargetTransformInfo::getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
 647                                                unsigned Alignment,
 648                                                unsigned AddressSpace) const {
 649   int Cost =
 650       TTIImpl->getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace);
 651   assert(Cost >= 0 && "TTI should not produce negative costs!");
 652   return Cost;
 653 }
 654
 655 int TargetTransformInfo::getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
 656                                                 Value *Ptr, bool VariableMask,
 657                                                 unsigned Alignment) const {
 658   int Cost = TTIImpl->getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
 659                                              Alignment);
 660   assert(Cost >= 0 && "TTI should not produce negative costs!");
 661   return Cost;
 662 }
 663
 664 int TargetTransformInfo::getInterleavedMemoryOpCost(
 665     unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
 666     unsigned Alignment, unsigned AddressSpace, bool UseMaskForCond,
 667     bool UseMaskForGaps) const {
 668   int Cost = TTIImpl->getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
 669                                                  Alignment, AddressSpace,
 670                                                  UseMaskForCond,
 671                                                  UseMaskForGaps);
 672   assert(Cost >= 0 && "TTI should not produce negative costs!");
 673   return Cost;
 674 }
 675
 676 int TargetTransformInfo::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
 677                                     ArrayRef<Type *> Tys, FastMathFlags FMF,
 678                                     unsigned ScalarizationCostPassed) const {
 679   int Cost = TTIImpl->getIntrinsicInstrCost(ID, RetTy, Tys, FMF,
 680                                             ScalarizationCostPassed);
 681   assert(Cost >= 0 && "TTI should not produce negative costs!");
 682   return Cost;
 683 }
 684
 685 int TargetTransformInfo::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
 686            ArrayRef<Value *> Args, FastMathFlags FMF, unsigned VF) const {
 687   int Cost = TTIImpl->getIntrinsicInstrCost(ID, RetTy, Args, FMF, VF);
 688   assert(Cost >= 0 && "TTI should not produce negative costs!");
 689   return Cost;
 690 }
 691
 692 int TargetTransformInfo::getCallInstrCost(Function *F, Type *RetTy,
 693                                           ArrayRef<Type *> Tys) const {
 694   int Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys);
 695   assert(Cost >= 0 && "TTI should not produce negative costs!");
 696   return Cost;
 697 }
 698
 699 unsigned TargetTransformInfo::getNumberOfParts(Type *Tp) const {
 700   return TTIImpl->getNumberOfParts(Tp);
 701 }
 702
 703 int TargetTransformInfo::getAddressComputationCost(Type *Tp,
 704                                                    ScalarEvolution *SE,
 705                                                    const SCEV *Ptr) const {
 706   int Cost = TTIImpl->getAddressComputationCost(Tp, SE, Ptr);
 707   assert(Cost >= 0 && "TTI should not produce negative costs!");
 708   return Cost;
 709 }
 710
 711 int TargetTransformInfo::getMemcpyCost(const Instruction *I) const {
 712   int Cost = TTIImpl->getMemcpyCost(I);
 713   assert(Cost >= 0 && "TTI should not produce negative costs!");
 714   return Cost;
 715 }
 716
 717 int TargetTransformInfo::getArithmeticReductionCost(unsigned Opcode, Type *Ty,
 718                                                     bool IsPairwiseForm) const {
 719   int Cost = TTIImpl->getArithmeticReductionCost(Opcode, Ty, IsPairwiseForm);
 720   assert(Cost >= 0 && "TTI should not produce negative costs!");
 721   return Cost;
 722 }
 723
 724 int TargetTransformInfo::getMinMaxReductionCost(Type *Ty, Type *CondTy,
 725                                                 bool IsPairwiseForm,
 726                                                 bool IsUnsigned) const {
 727   int Cost =
 728       TTIImpl->getMinMaxReductionCost(Ty, CondTy, IsPairwiseForm, IsUnsigned);
 729   assert(Cost >= 0 && "TTI should not produce negative costs!");
 730   return Cost;
 731 }
 732
 733 unsigned
 734 TargetTransformInfo::getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys) const {
 735   return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
 736 }
 737
 738 bool TargetTransformInfo::getTgtMemIntrinsic(IntrinsicInst *Inst,
 739                                              MemIntrinsicInfo &Info) const {
 740   return TTIImpl->getTgtMemIntrinsic(Inst, Info);
 741 }
 742
 743 unsigned TargetTransformInfo::getAtomicMemIntrinsicMaxElementSize() const {
 744   return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
 745 }
 746
 747 Value *TargetTransformInfo::getOrCreateResultFromMemIntrinsic(
 748     IntrinsicInst *Inst, Type *ExpectedType) const {
 749   return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
 750 }
 751
 752 Type *TargetTransformInfo::getMemcpyLoopLoweringType(LLVMContext &Context,
 753                                                      Value *Length,
 754                                                      unsigned SrcAlign,
 755                                                      unsigned DestAlign) const {
 756   return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAlign,
 757                                             DestAlign);
 758 }
 759
 760 void TargetTransformInfo::getMemcpyLoopResidualLoweringType(
 761     SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
 762     unsigned RemainingBytes, unsigned SrcAlign, unsigned DestAlign) const {
 763   TTIImpl->getMemcpyLoopResidualLoweringType(OpsOut, Context, RemainingBytes,
 764                                              SrcAlign, DestAlign);
 765 }
 766
 767 bool TargetTransformInfo::areInlineCompatible(const Function *Caller,
 768                                               const Function *Callee) const {
 769   return TTIImpl->areInlineCompatible(Caller, Callee);
 770 }
 771
 772 bool TargetTransformInfo::areFunctionArgsABICompatible(
 773     const Function *Caller, const Function *Callee,
 774     SmallPtrSetImpl<Argument *> &Args) const {
 775   return TTIImpl->areFunctionArgsABICompatible(Caller, Callee, Args);
 776 }
 777
 778 bool TargetTransformInfo::isIndexedLoadLegal(MemIndexedMode Mode,
 779                                              Type *Ty) const {
 780   return TTIImpl->isIndexedLoadLegal(Mode, Ty);
 781 }
 782
 783 bool TargetTransformInfo::isIndexedStoreLegal(MemIndexedMode Mode,
 784                                               Type *Ty) const {
 785   return TTIImpl->isIndexedStoreLegal(Mode, Ty);
 786 }
 787
 788 unsigned TargetTransformInfo::getLoadStoreVecRegBitWidth(unsigned AS) const {
 789   return TTIImpl->getLoadStoreVecRegBitWidth(AS);
 790 }
 791
 792 bool TargetTransformInfo::isLegalToVectorizeLoad(LoadInst *LI) const {
 793   return TTIImpl->isLegalToVectorizeLoad(LI);
 794 }
 795
 796 bool TargetTransformInfo::isLegalToVectorizeStore(StoreInst *SI) const {
 797   return TTIImpl->isLegalToVectorizeStore(SI);
 798 }
 799
 800 bool TargetTransformInfo::isLegalToVectorizeLoadChain(
 801     unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const {
 802   return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
 803                                               AddrSpace);
 804 }
 805
 806 bool TargetTransformInfo::isLegalToVectorizeStoreChain(
 807     unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const {
 808   return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
 809                                                AddrSpace);
 810 }
 811
 812 unsigned TargetTransformInfo::getLoadVectorFactor(unsigned VF,
 813                                                   unsigned LoadSize,
 814                                                   unsigned ChainSizeInBytes,
 815                                                   VectorType *VecTy) const {
 816   return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
 817 }
 818
 819 unsigned TargetTransformInfo::getStoreVectorFactor(unsigned VF,
 820                                                    unsigned StoreSize,
 821                                                    unsigned ChainSizeInBytes,
 822                                                    VectorType *VecTy) const {
 823   return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
 824 }
 825
 826 bool TargetTransformInfo::useReductionIntrinsic(unsigned Opcode,
 827                                                 Type *Ty, ReductionFlags Flags) const {
 828   return TTIImpl->useReductionIntrinsic(Opcode, Ty, Flags);
 829 }
 830
 831 bool TargetTransformInfo::shouldExpandReduction(const IntrinsicInst *II) const {
 832   return TTIImpl->shouldExpandReduction(II);
 833 }
 834
 835 unsigned TargetTransformInfo::getGISelRematGlobalCost() const {
 836   return TTIImpl->getGISelRematGlobalCost();
 837 }
 838
 839 int TargetTransformInfo::getInstructionLatency(const Instruction *I) const {
 840   return TTIImpl->getInstructionLatency(I);
 841 }
 842
 843 static bool matchPairwiseShuffleMask(ShuffleVectorInst *SI, bool IsLeft,
 844                                      unsigned Level) {
 845   // We don't need a shuffle if we just want to have element 0 in position 0 of
 846   // the vector.
 847   if (!SI && Level == 0 && IsLeft)
 848     return true;
 849   else if (!SI)
 850     return false;
 851
 852   SmallVector<int, 32> Mask(SI->getType()->getVectorNumElements(), -1);
 853
 854   // Build a mask of 0, 2, ... (left) or 1, 3, ... (right) depending on whether
 855   // we look at the left or right side.
 856   for (unsigned i = 0, e = (1 << Level), val = !IsLeft; i != e; ++i, val += 2)
 857     Mask[i] = val;
 858
 859   SmallVector<int, 16> ActualMask = SI->getShuffleMask();
 860   return Mask == ActualMask;
 861 }
 862
 863 namespace {
 864 /// Kind of the reduction data.
 865 enum ReductionKind {
 866   RK_None,           /// Not a reduction.
 867   RK_Arithmetic,     /// Binary reduction data.
 868   RK_MinMax,         /// Min/max reduction data.
 869   RK_UnsignedMinMax, /// Unsigned min/max reduction data.
 870 };
 871 /// Contains opcode + LHS/RHS parts of the reduction operations.
 872 struct ReductionData {
 873   ReductionData() = delete;
 874   ReductionData(ReductionKind Kind, unsigned Opcode, Value *LHS, Value *RHS)
 875       : Opcode(Opcode), LHS(LHS), RHS(RHS), Kind(Kind) {
 876     assert(Kind != RK_None && "expected binary or min/max reduction only.");
 877   }
 878   unsigned Opcode = 0;
 879   Value *LHS = nullptr;
 880   Value *RHS = nullptr;
 881   ReductionKind Kind = RK_None;
 882   bool hasSameData(ReductionData &RD) const {
 883     return Kind == RD.Kind && Opcode == RD.Opcode;
 884   }
 885 };
 886 } // namespace
 887
 888 static Optional<ReductionData> getReductionData(Instruction *I) {
 889   Value *L, *R;
 890   if (m_BinOp(m_Value(L), m_Value(R)).match(I))
 891     return ReductionData(RK_Arithmetic, I->getOpcode(), L, R);
 892   if (auto *SI = dyn_cast<SelectInst>(I)) {
 893     if (m_SMin(m_Value(L), m_Value(R)).match(SI) ||
 894         m_SMax(m_Value(L), m_Value(R)).match(SI) ||
 895         m_OrdFMin(m_Value(L), m_Value(R)).match(SI) ||
 896         m_OrdFMax(m_Value(L), m_Value(R)).match(SI) ||
 897         m_UnordFMin(m_Value(L), m_Value(R)).match(SI) ||
 898         m_UnordFMax(m_Value(L), m_Value(R)).match(SI)) {
 899       auto *CI = cast<CmpInst>(SI->getCondition());
 900       return ReductionData(RK_MinMax, CI->getOpcode(), L, R);
 901     }
 902     if (m_UMin(m_Value(L), m_Value(R)).match(SI) ||
 903         m_UMax(m_Value(L), m_Value(R)).match(SI)) {
 904       auto *CI = cast<CmpInst>(SI->getCondition());
 905       return ReductionData(RK_UnsignedMinMax, CI->getOpcode(), L, R);
 906     }
 907   }
 908   return llvm::None;
 909 }
 910
 911 static ReductionKind matchPairwiseReductionAtLevel(Instruction *I,
 912                                                    unsigned Level,
 913                                                    unsigned NumLevels) {
 914   // Match one level of pairwise operations.
 915   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
 916   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
 917   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
 918   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
 919   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
 920   if (!I)
 921     return RK_None;
 922
 923   assert(I->getType()->isVectorTy() && "Expecting a vector type");
 924
 925   Optional<ReductionData> RD = getReductionData(I);
 926   if (!RD)
 927     return RK_None;
 928
 929   ShuffleVectorInst *LS = dyn_cast<ShuffleVectorInst>(RD->LHS);
 930   if (!LS && Level)
 931     return RK_None;
 932   ShuffleVectorInst *RS = dyn_cast<ShuffleVectorInst>(RD->RHS);
 933   if (!RS && Level)
 934     return RK_None;
 935
 936   // On level 0 we can omit one shufflevector instruction.
 937   if (!Level && !RS && !LS)
 938     return RK_None;
 939
 940   // Shuffle inputs must match.
 941   Value *NextLevelOpL = LS ? LS->getOperand(0) : nullptr;
 942   Value *NextLevelOpR = RS ? RS->getOperand(0) : nullptr;
 943   Value *NextLevelOp = nullptr;
 944   if (NextLevelOpR && NextLevelOpL) {
 945     // If we have two shuffles their operands must match.
 946     if (NextLevelOpL != NextLevelOpR)
 947       return RK_None;
 948
 949     NextLevelOp = NextLevelOpL;
 950   } else if (Level == 0 && (NextLevelOpR || NextLevelOpL)) {
 951     // On the first level we can omit the shufflevector <0, undef,...>. So the
 952     // input to the other shufflevector <1, undef> must match with one of the
 953     // inputs to the current binary operation.
 954     // Example:
 955     //  %NextLevelOpL = shufflevector %R, <1, undef ...>
 956     //  %BinOp        = fadd          %NextLevelOpL, %R
 957     if (NextLevelOpL && NextLevelOpL != RD->RHS)
 958       return RK_None;
 959     else if (NextLevelOpR && NextLevelOpR != RD->LHS)
 960       return RK_None;
 961
 962     NextLevelOp = NextLevelOpL ? RD->RHS : RD->LHS;
 963   } else
 964     return RK_None;
 965
 966   // Check that the next levels binary operation exists and matches with the
 967   // current one.
 968   if (Level + 1 != NumLevels) {
 969     Optional<ReductionData> NextLevelRD =
 970         getReductionData(cast<Instruction>(NextLevelOp));
 971     if (!NextLevelRD || !RD->hasSameData(*NextLevelRD))
 972       return RK_None;
 973   }
 974
 975   // Shuffle mask for pairwise operation must match.
 976   if (matchPairwiseShuffleMask(LS, /*IsLeft=*/true, Level)) {
 977     if (!matchPairwiseShuffleMask(RS, /*IsLeft=*/false, Level))
 978       return RK_None;
 979   } else if (matchPairwiseShuffleMask(RS, /*IsLeft=*/true, Level)) {
 980     if (!matchPairwiseShuffleMask(LS, /*IsLeft=*/false, Level))
 981       return RK_None;
 982   } else {
 983     return RK_None;
 984   }
 985
 986   if (++Level == NumLevels)
 987     return RD->Kind;
 988
 989   // Match next level.
 990   return matchPairwiseReductionAtLevel(cast<Instruction>(NextLevelOp), Level,
 991                                        NumLevels);
 992 }
 993
 994 static ReductionKind matchPairwiseReduction(const ExtractElementInst *ReduxRoot,
 995                                             unsigned &Opcode, Type *&Ty) {
 996   if (!EnableReduxCost)
 997     return RK_None;
 998
 999   // Need to extract the first element.
1000   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
1001   unsigned Idx = ~0u;
1002   if (CI)
1003     Idx = CI->getZExtValue();
1004   if (Idx != 0)
1005     return RK_None;
1006
1007   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
1008   if (!RdxStart)
1009     return RK_None;
1010   Optional<ReductionData> RD = getReductionData(RdxStart);
1011   if (!RD)
1012     return RK_None;
1013
1014   Type *VecTy = RdxStart->getType();
1015   unsigned NumVecElems = VecTy->getVectorNumElements();
1016   if (!isPowerOf2_32(NumVecElems))
1017     return RK_None;
1018
1019   // We look for a sequence of shuffle,shuffle,add triples like the following
1020   // that builds a pairwise reduction tree.
1021   //
1022   //  (X0, X1, X2, X3)
1023   //   (X0 + X1, X2 + X3, undef, undef)
1024   //    ((X0 + X1) + (X2 + X3), undef, undef, undef)
1025   //
1026   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
1027   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
1028   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
1029   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
1030   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
1031   // %rdx.shuf.1.0 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
1032   //       <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
1033   // %rdx.shuf.1.1 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
1034   //       <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
1035   // %bin.rdx8 = fadd <4 x float> %rdx.shuf.1.0, %rdx.shuf.1.1
1036   // %r = extractelement <4 x float> %bin.rdx8, i32 0
1037   if (matchPairwiseReductionAtLevel(RdxStart, 0, Log2_32(NumVecElems)) ==
1038       RK_None)
1039     return RK_None;
1040
1041   Opcode = RD->Opcode;
1042   Ty = VecTy;
1043
1044   return RD->Kind;
1045 }
1046
1047 static std::pair<Value *, ShuffleVectorInst *>
1048 getShuffleAndOtherOprd(Value *L, Value *R) {
1049   ShuffleVectorInst *S = nullptr;
1050
1051   if ((S = dyn_cast<ShuffleVectorInst>(L)))
1052     return std::make_pair(R, S);
1053
1054   S = dyn_cast<ShuffleVectorInst>(R);
1055   return std::make_pair(L, S);
1056 }
1057
1058 static ReductionKind
1059 matchVectorSplittingReduction(const ExtractElementInst *ReduxRoot,
1060                               unsigned &Opcode, Type *&Ty) {
1061   if (!EnableReduxCost)
1062     return RK_None;
1063
1064   // Need to extract the first element.
1065   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
1066   unsigned Idx = ~0u;
1067   if (CI)
1068     Idx = CI->getZExtValue();
1069   if (Idx != 0)
1070     return RK_None;
1071
1072   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
1073   if (!RdxStart)
1074     return RK_None;
1075   Optional<ReductionData> RD = getReductionData(RdxStart);
1076   if (!RD)
1077     return RK_None;
1078
1079   Type *VecTy = ReduxRoot->getOperand(0)->getType();
1080   unsigned NumVecElems = VecTy->getVectorNumElements();
1081   if (!isPowerOf2_32(NumVecElems))
1082     return RK_None;
1083
1084   // We look for a sequence of shuffles and adds like the following matching one
1085   // fadd, shuffle vector pair at a time.
1086   //
1087   // %rdx.shuf = shufflevector <4 x float> %rdx, <4 x float> undef,
1088   //                           <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
1089   // %bin.rdx = fadd <4 x float> %rdx, %rdx.shuf
1090   // %rdx.shuf7 = shufflevector <4 x float> %bin.rdx, <4 x float> undef,
1091   //                          <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
1092   // %bin.rdx8 = fadd <4 x float> %bin.rdx, %rdx.shuf7
1093   // %r = extractelement <4 x float> %bin.rdx8, i32 0
1094
1095   unsigned MaskStart = 1;
1096   Instruction *RdxOp = RdxStart;
1097   SmallVector<int, 32> ShuffleMask(NumVecElems, 0);
1098   unsigned NumVecElemsRemain = NumVecElems;
1099   while (NumVecElemsRemain - 1) {
1100     // Check for the right reduction operation.
1101     if (!RdxOp)
1102       return RK_None;
1103     Optional<ReductionData> RDLevel = getReductionData(RdxOp);
1104     if (!RDLevel || !RDLevel->hasSameData(*RD))
1105       return RK_None;
1106
1107     Value *NextRdxOp;
1108     ShuffleVectorInst *Shuffle;
1109     std::tie(NextRdxOp, Shuffle) =
1110         getShuffleAndOtherOprd(RDLevel->LHS, RDLevel->RHS);
1111
1112     // Check the current reduction operation and the shuffle use the same value.
1113     if (Shuffle == nullptr)
1114       return RK_None;
1115     if (Shuffle->getOperand(0) != NextRdxOp)
1116       return RK_None;
1117
1118     // Check that shuffle masks matches.
1119     for (unsigned j = 0; j != MaskStart; ++j)
1120       ShuffleMask[j] = MaskStart + j;
1121     // Fill the rest of the mask with -1 for undef.
1122     std::fill(&ShuffleMask[MaskStart], ShuffleMask.end(), -1);
1123
1124     SmallVector<int, 16> Mask = Shuffle->getShuffleMask();
1125     if (ShuffleMask != Mask)
1126       return RK_None;
1127
1128     RdxOp = dyn_cast<Instruction>(NextRdxOp);
1129     NumVecElemsRemain /= 2;
1130     MaskStart *= 2;
1131   }
1132
1133   Opcode = RD->Opcode;
1134   Ty = VecTy;
1135   return RD->Kind;
1136 }
1137
1138 int TargetTransformInfo::getInstructionThroughput(const Instruction *I) const {
1139   switch (I->getOpcode()) {
1140   case Instruction::GetElementPtr:
1141     return getUserCost(I);
1142
1143   case Instruction::Ret:
1144   case Instruction::PHI:
1145   case Instruction::Br: {
1146     return getCFInstrCost(I->getOpcode());
1147   }
1148   case Instruction::Add:
1149   case Instruction::FAdd:
1150   case Instruction::Sub:
1151   case Instruction::FSub:
1152   case Instruction::Mul:
1153   case Instruction::FMul:
1154   case Instruction::UDiv:
1155   case Instruction::SDiv:
1156   case Instruction::FDiv:
1157   case Instruction::URem:
1158   case Instruction::SRem:
1159   case Instruction::FRem:
1160   case Instruction::Shl:
1161   case Instruction::LShr:
1162   case Instruction::AShr:
1163   case Instruction::And:
1164   case Instruction::Or:
1165   case Instruction::Xor: {
1166     TargetTransformInfo::OperandValueKind Op1VK, Op2VK;
1167     TargetTransformInfo::OperandValueProperties Op1VP, Op2VP;
1168     Op1VK = getOperandInfo(I->getOperand(0), Op1VP);
1169     Op2VK = getOperandInfo(I->getOperand(1), Op2VP);
1170     SmallVector<const Value *, 2> Operands(I->operand_values());
1171     return getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK, Op2VK,
1172                                   Op1VP, Op2VP, Operands);
1173   }
1174   case Instruction::FNeg: {
1175     TargetTransformInfo::OperandValueKind Op1VK, Op2VK;
1176     TargetTransformInfo::OperandValueProperties Op1VP, Op2VP;
1177     Op1VK = getOperandInfo(I->getOperand(0), Op1VP);
1178     Op2VK = OK_AnyValue;
1179     Op2VP = OP_None;
1180     SmallVector<const Value *, 2> Operands(I->operand_values());
1181     return getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK, Op2VK,
1182                                   Op1VP, Op2VP, Operands);
1183   }
1184   case Instruction::Select: {
1185     const SelectInst *SI = cast<SelectInst>(I);
1186     Type *CondTy = SI->getCondition()->getType();
1187     return getCmpSelInstrCost(I->getOpcode(), I->getType(), CondTy, I);
1188   }
1189   case Instruction::ICmp:
1190   case Instruction::FCmp: {
1191     Type *ValTy = I->getOperand(0)->getType();
1192     return getCmpSelInstrCost(I->getOpcode(), ValTy, I->getType(), I);
1193   }
1194   case Instruction::Store: {
1195     const StoreInst *SI = cast<StoreInst>(I);
1196     Type *ValTy = SI->getValueOperand()->getType();
1197     return getMemoryOpCost(I->getOpcode(), ValTy,
1198                                 SI->getAlignment(),
1199                                 SI->getPointerAddressSpace(), I);
1200   }
1201   case Instruction::Load: {
1202     const LoadInst *LI = cast<LoadInst>(I);
1203     return getMemoryOpCost(I->getOpcode(), I->getType(),
1204                                 LI->getAlignment(),
1205                                 LI->getPointerAddressSpace(), I);
1206   }
1207   case Instruction::ZExt:
1208   case Instruction::SExt:
1209   case Instruction::FPToUI:
1210   case Instruction::FPToSI:
1211   case Instruction::FPExt:
1212   case Instruction::PtrToInt:
1213   case Instruction::IntToPtr:
1214   case Instruction::SIToFP:
1215   case Instruction::UIToFP:
1216   case Instruction::Trunc:
1217   case Instruction::FPTrunc:
1218   case Instruction::BitCast:
1219   case Instruction::AddrSpaceCast: {
1220     Type *SrcTy = I->getOperand(0)->getType();
1221     return getCastInstrCost(I->getOpcode(), I->getType(), SrcTy, I);
1222   }
1223   case Instruction::ExtractElement: {
1224     const ExtractElementInst * EEI = cast<ExtractElementInst>(I);
1225     ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1));
1226     unsigned Idx = -1;
1227     if (CI)
1228       Idx = CI->getZExtValue();
1229
1230     // Try to match a reduction sequence (series of shufflevector and vector
1231     // adds followed by a extractelement).
1232     unsigned ReduxOpCode;
1233     Type *ReduxType;
1234
1235     switch (matchVectorSplittingReduction(EEI, ReduxOpCode, ReduxType)) {
1236     case RK_Arithmetic:
1237       return getArithmeticReductionCost(ReduxOpCode, ReduxType,
1238                                              /*IsPairwiseForm=*/false);
1239     case RK_MinMax:
1240       return getMinMaxReductionCost(
1241           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1242           /*IsPairwiseForm=*/false, /*IsUnsigned=*/false);
1243     case RK_UnsignedMinMax:
1244       return getMinMaxReductionCost(
1245           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1246           /*IsPairwiseForm=*/false, /*IsUnsigned=*/true);
1247     case RK_None:
1248       break;
1249     }
1250
1251     switch (matchPairwiseReduction(EEI, ReduxOpCode, ReduxType)) {
1252     case RK_Arithmetic:
1253       return getArithmeticReductionCost(ReduxOpCode, ReduxType,
1254                                              /*IsPairwiseForm=*/true);
1255     case RK_MinMax:
1256       return getMinMaxReductionCost(
1257           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1258           /*IsPairwiseForm=*/true, /*IsUnsigned=*/false);
1259     case RK_UnsignedMinMax:
1260       return getMinMaxReductionCost(
1261           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1262           /*IsPairwiseForm=*/true, /*IsUnsigned=*/true);
1263     case RK_None:
1264       break;
1265     }
1266
1267     return getVectorInstrCost(I->getOpcode(),
1268                                    EEI->getOperand(0)->getType(), Idx);
1269   }
1270   case Instruction::InsertElement: {
1271     const InsertElementInst * IE = cast<InsertElementInst>(I);
1272     ConstantInt *CI = dyn_cast<ConstantInt>(IE->getOperand(2));
1273     unsigned Idx = -1;
1274     if (CI)
1275       Idx = CI->getZExtValue();
1276     return getVectorInstrCost(I->getOpcode(),
1277                                    IE->getType(), Idx);
1278   }
1279   case Instruction::ShuffleVector: {
1280     const ShuffleVectorInst *Shuffle = cast<ShuffleVectorInst>(I);
1281     Type *Ty = Shuffle->getType();
1282     Type *SrcTy = Shuffle->getOperand(0)->getType();
1283
1284     // TODO: Identify and add costs for insert subvector, etc.
1285     int SubIndex;
1286     if (Shuffle->isExtractSubvectorMask(SubIndex))
1287       return TTIImpl->getShuffleCost(SK_ExtractSubvector, SrcTy, SubIndex, Ty);
1288
1289     if (Shuffle->changesLength())
1290       return -1;
1291
1292     if (Shuffle->isIdentity())
1293       return 0;
1294
1295     if (Shuffle->isReverse())
1296       return TTIImpl->getShuffleCost(SK_Reverse, Ty, 0, nullptr);
1297
1298     if (Shuffle->isSelect())
1299       return TTIImpl->getShuffleCost(SK_Select, Ty, 0, nullptr);
1300
1301     if (Shuffle->isTranspose())
1302       return TTIImpl->getShuffleCost(SK_Transpose, Ty, 0, nullptr);
1303
1304     if (Shuffle->isZeroEltSplat())
1305       return TTIImpl->getShuffleCost(SK_Broadcast, Ty, 0, nullptr);
1306
1307     if (Shuffle->isSingleSource())
1308       return TTIImpl->getShuffleCost(SK_PermuteSingleSrc, Ty, 0, nullptr);
1309
1310     return TTIImpl->getShuffleCost(SK_PermuteTwoSrc, Ty, 0, nullptr);
1311   }
1312   case Instruction::Call:
1313     if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
1314       SmallVector<Value *, 4> Args(II->arg_operands());
1315
1316       FastMathFlags FMF;
1317       if (auto *FPMO = dyn_cast<FPMathOperator>(II))
1318         FMF = FPMO->getFastMathFlags();
1319
1320       return getIntrinsicInstrCost(II->getIntrinsicID(), II->getType(),
1321                                         Args, FMF);
1322     }
1323     return -1;
1324   default:
1325     // We don't have any information on this instruction.
1326     return -1;
1327   }
1328 }
1329
1330 TargetTransformInfo::Concept::~Concept() {}
1331
1332 TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1333
1334 TargetIRAnalysis::TargetIRAnalysis(
1335     std::function<Result(const Function &)> TTICallback)
1336     : TTICallback(std::move(TTICallback)) {}
1337
1338 TargetIRAnalysis::Result TargetIRAnalysis::run(const Function &F,
1339                                                FunctionAnalysisManager &) {
1340   return TTICallback(F);
1341 }
1342
1343 AnalysisKey TargetIRAnalysis::Key;
1344
1345 TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1346   return Result(F.getParent()->getDataLayout());
1347 }
1348
1349 // Register the basic pass.
1350 INITIALIZE_PASS(TargetTransformInfoWrapperPass, "tti",
1351                 "Target Transform Information", false, true)
1352 char TargetTransformInfoWrapperPass::ID = 0;
1353
1354 void TargetTransformInfoWrapperPass::anchor() {}
1355
1356 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass()
1357     : ImmutablePass(ID) {
1358   initializeTargetTransformInfoWrapperPassPass(
1359       *PassRegistry::getPassRegistry());
1360 }
1361
1362 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass(
1363     TargetIRAnalysis TIRA)
1364     : ImmutablePass(ID), TIRA(std::move(TIRA)) {
1365   initializeTargetTransformInfoWrapperPassPass(
1366       *PassRegistry::getPassRegistry());
1367 }
1368
1369 TargetTransformInfo &TargetTransformInfoWrapperPass::getTTI(const Function &F) {
1370   FunctionAnalysisManager DummyFAM;
1371   TTI = TIRA.run(F, DummyFAM);
1372   return *TTI;
1373 }
1374
1375 ImmutablePass *
1376 llvm::createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA) {
1377   return new TargetTransformInfoWrapperPass(std::move(TIRA));
1378 }