1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -O1 -verify-machineinstrs %s -o - | FileCheck %s
8 tracksRegLiveness: true
13 ; CHECK-LABEL: name: splat_4xi32
15 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
16 ; CHECK: [[DUPv4i32gpr:%[0-9]+]]:fpr128 = DUPv4i32gpr [[COPY]]
17 ; CHECK: $q0 = COPY [[DUPv4i32gpr]]
18 ; CHECK: RET_ReallyLR implicit $q0
19 %0:gpr(s32) = COPY $w0
20 %2:fpr(<4 x s32>) = G_IMPLICIT_DEF
21 %3:gpr(s32) = G_CONSTANT i32 0
22 %5:fpr(<4 x s32>) = G_BUILD_VECTOR %3(s32), %3(s32), %3(s32), %3(s32)
23 %1:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s32)
24 %4:fpr(<4 x s32>) = G_SHUFFLE_VECTOR %1(<4 x s32>), %2, %5(<4 x s32>)
25 $q0 = COPY %4(<4 x s32>)
26 RET_ReallyLR implicit $q0
34 tracksRegLiveness: true
39 ; CHECK-LABEL: name: splat_2xi64
41 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
42 ; CHECK: [[DUPv2i64gpr:%[0-9]+]]:fpr128 = DUPv2i64gpr [[COPY]]
43 ; CHECK: $q0 = COPY [[DUPv2i64gpr]]
44 ; CHECK: RET_ReallyLR implicit $q0
45 %0:gpr(s64) = COPY $x0
46 %2:fpr(<2 x s64>) = G_IMPLICIT_DEF
47 %3:gpr(s32) = G_CONSTANT i32 0
48 %5:fpr(<2 x s32>) = G_BUILD_VECTOR %3(s32), %3(s32)
49 %1:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %2, %0(s64), %3(s32)
50 %4:fpr(<2 x s64>) = G_SHUFFLE_VECTOR %1(<2 x s64>), %2, %5(<2 x s32>)
51 $q0 = COPY %4(<2 x s64>)
52 RET_ReallyLR implicit $q0
60 tracksRegLiveness: true
65 ; CHECK-LABEL: name: splat_4xf32
67 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
68 ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
69 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.ssub
70 ; CHECK: [[DUPv4i32lane:%[0-9]+]]:fpr128 = DUPv4i32lane [[INSERT_SUBREG]], 0
71 ; CHECK: $q0 = COPY [[DUPv4i32lane]]
72 ; CHECK: RET_ReallyLR implicit $q0
73 %0:fpr(s32) = COPY $s0
74 %2:fpr(<4 x s32>) = G_IMPLICIT_DEF
75 %3:gpr(s32) = G_CONSTANT i32 0
76 %5:fpr(<4 x s32>) = G_BUILD_VECTOR %3(s32), %3(s32), %3(s32), %3(s32)
77 %1:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s32)
78 %4:fpr(<4 x s32>) = G_SHUFFLE_VECTOR %1(<4 x s32>), %2, %5(<4 x s32>)
79 $q0 = COPY %4(<4 x s32>)
80 RET_ReallyLR implicit $q0
88 tracksRegLiveness: true
93 ; CHECK-LABEL: name: splat_2xf64
95 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
96 ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
97 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
98 ; CHECK: [[DUPv2i64lane:%[0-9]+]]:fpr128 = DUPv2i64lane [[INSERT_SUBREG]], 0
99 ; CHECK: $q0 = COPY [[DUPv2i64lane]]
100 ; CHECK: RET_ReallyLR implicit $q0
101 %0:fpr(s64) = COPY $d0
102 %2:fpr(<2 x s64>) = G_IMPLICIT_DEF
103 %3:gpr(s32) = G_CONSTANT i32 0
104 %5:fpr(<2 x s32>) = G_BUILD_VECTOR %3(s32), %3(s32)
105 %1:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %2, %0(s64), %3(s32)
106 %4:fpr(<2 x s64>) = G_SHUFFLE_VECTOR %1(<2 x s64>), %2, %5(<2 x s32>)
107 $q0 = COPY %4(<2 x s64>)
108 RET_ReallyLR implicit $q0
112 name: splat_2xf64_copies
115 regBankSelected: true
116 tracksRegLiveness: true
121 ; This test is exactly the same as splat_2xf64, except it adds two copies.
122 ; These copies shouldn't get in the way of matching the dup pattern.
123 %0:fpr(s64) = COPY $d0
124 %2:fpr(<2 x s64>) = G_IMPLICIT_DEF
125 %6:fpr(<2 x s64>) = COPY %2
126 %3:gpr(s32) = G_CONSTANT i32 0
127 %5:fpr(<2 x s32>) = G_BUILD_VECTOR %3(s32), %3(s32)
128 %1:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %6, %0(s64), %3(s32)
129 %7:fpr(<2 x s64>) = COPY %1
130 %4:fpr(<2 x s64>) = G_SHUFFLE_VECTOR %7(<2 x s64>), %2, %5(<2 x s32>)
131 $q0 = COPY %4(<2 x s64>)
132 RET_ReallyLR implicit $q0