1 ; RUN: llc -mtriple aarch64-none-linux-gnu -mattr=+dotprod < %s | FileCheck %s
3 declare <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32>, <8 x i8>, <8 x i8>)
4 declare <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>)
5 declare <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32>, <8 x i8>, <8 x i8>)
6 declare <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>)
8 define <2 x i32> @test_vdot_u32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #0 {
10 ; CHECK-LABEL: test_vdot_u32:
11 ; CHECK: udot v0.2s, v1.8b, v2.8b
12 %vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #2
13 ret <2 x i32> %vdot1.i
16 define <4 x i32> @test_vdotq_u32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #0 {
18 ; CHECK-LABEL: test_vdotq_u32:
19 ; CHECK: udot v0.4s, v1.16b, v2.16b
20 %vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #2
21 ret <4 x i32> %vdot1.i
24 define <2 x i32> @test_vdot_s32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #0 {
26 ; CHECK-LABEL: test_vdot_s32:
27 ; CHECK: sdot v0.2s, v1.8b, v2.8b
28 %vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #2
29 ret <2 x i32> %vdot1.i
32 define <4 x i32> @test_vdotq_s32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #0 {
34 ; CHECK-LABEL: test_vdotq_s32:
35 ; CHECK: sdot v0.4s, v1.16b, v2.16b
36 %vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #2
37 ret <4 x i32> %vdot1.i
40 define <2 x i32> @test_vdot_lane_u32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) {
42 ; CHECK-LABEL: test_vdot_lane_u32:
43 ; CHECK: udot v0.2s, v1.8b, v2.4b[1]
44 %.cast = bitcast <8 x i8> %c to <2 x i32>
45 %shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
46 %.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
47 %vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %.cast5) #2
48 ret <2 x i32> %vdot1.i
51 define <4 x i32> @test_vdotq_lane_u32(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c) {
53 ; CHECK-LABEL: test_vdotq_lane_u32:
54 ; CHECK: udot v0.4s, v1.16b, v2.4b[1]
55 %.cast = bitcast <8 x i8> %c to <2 x i32>
56 %shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
57 %.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
58 %vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %.cast3) #2
59 ret <4 x i32> %vdot1.i
62 define <2 x i32> @test_vdot_laneq_u32(<2 x i32> %a, <8 x i8> %b, <16 x i8> %c) {
64 ; CHECK-LABEL: test_vdot_laneq_u32:
65 ; CHECK: udot v0.2s, v1.8b, v2.4b[1]
66 %.cast = bitcast <16 x i8> %c to <4 x i32>
67 %shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <2 x i32> <i32 1, i32 1>
68 %.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
69 %vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %.cast5) #2
70 ret <2 x i32> %vdot1.i
73 define <4 x i32> @test_vdotq_laneq_u32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) {
75 ; CHECK-LABEL: test_vdotq_laneq_u32:
76 ; CHECK: udot v0.4s, v1.16b, v2.4b[1]
77 %.cast = bitcast <16 x i8> %c to <4 x i32>
78 %shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
79 %.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
80 %vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %.cast3) #2
81 ret <4 x i32> %vdot1.i
84 define <2 x i32> @test_vdot_lane_s32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) {
86 ; CHECK-LABEL: test_vdot_lane_s32:
87 ; CHECK: sdot v0.2s, v1.8b, v2.4b[1]
88 %.cast = bitcast <8 x i8> %c to <2 x i32>
89 %shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
90 %.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
91 %vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %.cast5) #2
92 ret <2 x i32> %vdot1.i
95 define <4 x i32> @test_vdotq_lane_s32(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c) {
97 ; CHECK-LABEL: test_vdotq_lane_s32:
98 ; CHECK: sdot v0.4s, v1.16b, v2.4b[1]
99 %.cast = bitcast <8 x i8> %c to <2 x i32>
100 %shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
101 %.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
102 %vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %.cast3) #2
103 ret <4 x i32> %vdot1.i
106 define <2 x i32> @test_vdot_laneq_s32(<2 x i32> %a, <8 x i8> %b, <16 x i8> %c) {
108 ; CHECK-LABEL: test_vdot_laneq_s32:
109 ; CHECK: sdot v0.2s, v1.8b, v2.4b[1]
110 %.cast = bitcast <16 x i8> %c to <4 x i32>
111 %shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <2 x i32> <i32 1, i32 1>
112 %.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
113 %vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %.cast5) #2
114 ret <2 x i32> %vdot1.i
117 define <4 x i32> @test_vdotq_laneq_s32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) {
119 ; CHECK-LABEL: test_vdotq_laneq_s32:
120 ; CHECK: sdot v0.4s, v1.16b, v2.4b[1]
121 %.cast = bitcast <16 x i8> %c to <4 x i32>
122 %shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
123 %.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
124 %vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %.cast3) #2
125 ret <4 x i32> %vdot1.i