| blob | 331085fe76776788661abd9b0dc05972ad69a998 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=armv6 < %s | FileCheck %s --check-prefixes=CHECK,ARM,ARM6
3 ; RUN: llc -mtriple=armv7 < %s | FileCheck %s --check-prefixes=CHECK,ARM,ARM78,ARM7
4 ; RUN: llc -mtriple=armv8a < %s | FileCheck %s --check-prefixes=CHECK,ARM,ARM78,ARM8
5 ; RUN: llc -mtriple=thumbv6 < %s | FileCheck %s --check-prefixes=CHECK,THUMB,THUMB6
6 ; RUN: llc -mtriple=thumbv7 < %s | FileCheck %s --check-prefixes=CHECK,THUMB,THUMB78,THUMB7
7 ; RUN: llc -mtriple=thumbv8-eabi < %s | FileCheck %s --check-prefixes=CHECK,THUMB,THUMB78,THUMB8
9 ; We are looking for the following pattern here:
10 ; (X & (C << Y)) ==/!= 0
11 ; It may be optimal to hoist the constant:
12 ; ((X l>> Y) & C) ==/!= 0
14 ;------------------------------------------------------------------------------;
15 ; A few scalar test
16 ;------------------------------------------------------------------------------;
18 ; i8 scalar
20 define i1 @scalar_i8_signbit_eq(i8 %x, i8 %y) nounwind {
21 ; ARM-LABEL: scalar_i8_signbit_eq:
22 ; ARM: @ %bb.0:
23 ; ARM-NEXT: uxtb r1, r1
24 ; ARM-NEXT: mvn r2, #127
25 ; ARM-NEXT: and r0, r0, r2, lsl r1
26 ; ARM-NEXT: uxtb r0, r0
27 ; ARM-NEXT: clz r0, r0
28 ; ARM-NEXT: lsr r0, r0, #5
29 ; ARM-NEXT: bx lr
30 ;
31 ; THUMB6-LABEL: scalar_i8_signbit_eq:
32 ; THUMB6: @ %bb.0:
33 ; THUMB6-NEXT: uxtb r1, r1
34 ; THUMB6-NEXT: movs r2, #127
35 ; THUMB6-NEXT: mvns r2, r2
36 ; THUMB6-NEXT: lsls r2, r1
37 ; THUMB6-NEXT: ands r2, r0
38 ; THUMB6-NEXT: uxtb r1, r2
39 ; THUMB6-NEXT: rsbs r0, r1, #0
40 ; THUMB6-NEXT: adcs r0, r1
41 ; THUMB6-NEXT: bx lr
42 ;
43 ; THUMB78-LABEL: scalar_i8_signbit_eq:
44 ; THUMB78: @ %bb.0:
45 ; THUMB78-NEXT: uxtb r1, r1
46 ; THUMB78-NEXT: mvn r2, #127
47 ; THUMB78-NEXT: lsl.w r1, r2, r1
48 ; THUMB78-NEXT: ands r0, r1
49 ; THUMB78-NEXT: uxtb r0, r0
50 ; THUMB78-NEXT: clz r0, r0
51 ; THUMB78-NEXT: lsrs r0, r0, #5
52 ; THUMB78-NEXT: bx lr
53 %t0 = shl i8 128, %y
54 %t1 = and i8 %t0, %x
55 %res = icmp eq i8 %t1, 0
56 ret i1 %res
57 }
59 define i1 @scalar_i8_lowestbit_eq(i8 %x, i8 %y) nounwind {
60 ; ARM-LABEL: scalar_i8_lowestbit_eq:
61 ; ARM: @ %bb.0:
62 ; ARM-NEXT: uxtb r1, r1
63 ; ARM-NEXT: mov r2, #1
64 ; ARM-NEXT: and r0, r0, r2, lsl r1
65 ; ARM-NEXT: uxtb r0, r0
66 ; ARM-NEXT: clz r0, r0
67 ; ARM-NEXT: lsr r0, r0, #5
68 ; ARM-NEXT: bx lr
69 ;
70 ; THUMB6-LABEL: scalar_i8_lowestbit_eq:
71 ; THUMB6: @ %bb.0:
72 ; THUMB6-NEXT: uxtb r1, r1
73 ; THUMB6-NEXT: movs r2, #1
74 ; THUMB6-NEXT: lsls r2, r1
75 ; THUMB6-NEXT: ands r2, r0
76 ; THUMB6-NEXT: uxtb r1, r2
77 ; THUMB6-NEXT: rsbs r0, r1, #0
78 ; THUMB6-NEXT: adcs r0, r1
79 ; THUMB6-NEXT: bx lr
80 ;
81 ; THUMB78-LABEL: scalar_i8_lowestbit_eq:
82 ; THUMB78: @ %bb.0:
83 ; THUMB78-NEXT: uxtb r1, r1
84 ; THUMB78-NEXT: movs r2, #1
85 ; THUMB78-NEXT: lsl.w r1, r2, r1
86 ; THUMB78-NEXT: ands r0, r1
87 ; THUMB78-NEXT: uxtb r0, r0
88 ; THUMB78-NEXT: clz r0, r0
89 ; THUMB78-NEXT: lsrs r0, r0, #5
90 ; THUMB78-NEXT: bx lr
91 %t0 = shl i8 1, %y
92 %t1 = and i8 %t0, %x
93 %res = icmp eq i8 %t1, 0
94 ret i1 %res
95 }
97 define i1 @scalar_i8_bitsinmiddle_eq(i8 %x, i8 %y) nounwind {
98 ; ARM-LABEL: scalar_i8_bitsinmiddle_eq:
99 ; ARM: @ %bb.0:
100 ; ARM-NEXT: uxtb r1, r1
101 ; ARM-NEXT: mov r2, #24
102 ; ARM-NEXT: and r0, r0, r2, lsl r1
103 ; ARM-NEXT: uxtb r0, r0
104 ; ARM-NEXT: clz r0, r0
105 ; ARM-NEXT: lsr r0, r0, #5
106 ; ARM-NEXT: bx lr
107 ;
108 ; THUMB6-LABEL: scalar_i8_bitsinmiddle_eq:
109 ; THUMB6: @ %bb.0:
110 ; THUMB6-NEXT: uxtb r1, r1
111 ; THUMB6-NEXT: movs r2, #24
112 ; THUMB6-NEXT: lsls r2, r1
113 ; THUMB6-NEXT: ands r2, r0
114 ; THUMB6-NEXT: uxtb r1, r2
115 ; THUMB6-NEXT: rsbs r0, r1, #0
116 ; THUMB6-NEXT: adcs r0, r1
117 ; THUMB6-NEXT: bx lr
118 ;
119 ; THUMB78-LABEL: scalar_i8_bitsinmiddle_eq:
120 ; THUMB78: @ %bb.0:
121 ; THUMB78-NEXT: uxtb r1, r1
122 ; THUMB78-NEXT: movs r2, #24
123 ; THUMB78-NEXT: lsl.w r1, r2, r1
124 ; THUMB78-NEXT: ands r0, r1
125 ; THUMB78-NEXT: uxtb r0, r0
126 ; THUMB78-NEXT: clz r0, r0
127 ; THUMB78-NEXT: lsrs r0, r0, #5
128 ; THUMB78-NEXT: bx lr
129 %t0 = shl i8 24, %y
130 %t1 = and i8 %t0, %x
131 %res = icmp eq i8 %t1, 0
132 ret i1 %res
133 }
135 ; i16 scalar
137 define i1 @scalar_i16_signbit_eq(i16 %x, i16 %y) nounwind {
138 ; ARM6-LABEL: scalar_i16_signbit_eq:
139 ; ARM6: @ %bb.0:
140 ; ARM6-NEXT: ldr r2, .LCPI3_0
141 ; ARM6-NEXT: uxth r1, r1
142 ; ARM6-NEXT: and r0, r0, r2, lsl r1
143 ; ARM6-NEXT: uxth r0, r0
144 ; ARM6-NEXT: clz r0, r0
145 ; ARM6-NEXT: lsr r0, r0, #5
146 ; ARM6-NEXT: bx lr
147 ; ARM6-NEXT: .p2align 2
148 ; ARM6-NEXT: @ %bb.1:
149 ; ARM6-NEXT: .LCPI3_0:
150 ; ARM6-NEXT: .long 4294934528 @ 0xffff8000
151 ;
152 ; ARM78-LABEL: scalar_i16_signbit_eq:
153 ; ARM78: @ %bb.0:
154 ; ARM78-NEXT: movw r2, #32768
155 ; ARM78-NEXT: uxth r1, r1
156 ; ARM78-NEXT: movt r2, #65535
157 ; ARM78-NEXT: and r0, r0, r2, lsl r1
158 ; ARM78-NEXT: uxth r0, r0
159 ; ARM78-NEXT: clz r0, r0
160 ; ARM78-NEXT: lsr r0, r0, #5
161 ; ARM78-NEXT: bx lr
162 ;
163 ; THUMB6-LABEL: scalar_i16_signbit_eq:
164 ; THUMB6: @ %bb.0:
165 ; THUMB6-NEXT: uxth r1, r1
166 ; THUMB6-NEXT: ldr r2, .LCPI3_0
167 ; THUMB6-NEXT: lsls r2, r1
168 ; THUMB6-NEXT: ands r2, r0
169 ; THUMB6-NEXT: uxth r1, r2
170 ; THUMB6-NEXT: rsbs r0, r1, #0
171 ; THUMB6-NEXT: adcs r0, r1
172 ; THUMB6-NEXT: bx lr
173 ; THUMB6-NEXT: .p2align 2
174 ; THUMB6-NEXT: @ %bb.1:
175 ; THUMB6-NEXT: .LCPI3_0:
176 ; THUMB6-NEXT: .long 4294934528 @ 0xffff8000
177 ;
178 ; THUMB78-LABEL: scalar_i16_signbit_eq:
179 ; THUMB78: @ %bb.0:
180 ; THUMB78-NEXT: movw r2, #32768
181 ; THUMB78-NEXT: uxth r1, r1
182 ; THUMB78-NEXT: movt r2, #65535
183 ; THUMB78-NEXT: lsl.w r1, r2, r1
184 ; THUMB78-NEXT: ands r0, r1
185 ; THUMB78-NEXT: uxth r0, r0
186 ; THUMB78-NEXT: clz r0, r0
187 ; THUMB78-NEXT: lsrs r0, r0, #5
188 ; THUMB78-NEXT: bx lr
189 %t0 = shl i16 32768, %y
190 %t1 = and i16 %t0, %x
191 %res = icmp eq i16 %t1, 0
192 ret i1 %res
193 }
195 define i1 @scalar_i16_lowestbit_eq(i16 %x, i16 %y) nounwind {
196 ; ARM-LABEL: scalar_i16_lowestbit_eq:
197 ; ARM: @ %bb.0:
198 ; ARM-NEXT: uxth r1, r1
199 ; ARM-NEXT: mov r2, #1
200 ; ARM-NEXT: and r0, r0, r2, lsl r1
201 ; ARM-NEXT: uxth r0, r0
202 ; ARM-NEXT: clz r0, r0
203 ; ARM-NEXT: lsr r0, r0, #5
204 ; ARM-NEXT: bx lr
205 ;
206 ; THUMB6-LABEL: scalar_i16_lowestbit_eq:
207 ; THUMB6: @ %bb.0:
208 ; THUMB6-NEXT: uxth r1, r1
209 ; THUMB6-NEXT: movs r2, #1
210 ; THUMB6-NEXT: lsls r2, r1
211 ; THUMB6-NEXT: ands r2, r0
212 ; THUMB6-NEXT: uxth r1, r2
213 ; THUMB6-NEXT: rsbs r0, r1, #0
214 ; THUMB6-NEXT: adcs r0, r1
215 ; THUMB6-NEXT: bx lr
216 ;
217 ; THUMB78-LABEL: scalar_i16_lowestbit_eq:
218 ; THUMB78: @ %bb.0:
219 ; THUMB78-NEXT: uxth r1, r1
220 ; THUMB78-NEXT: movs r2, #1
221 ; THUMB78-NEXT: lsl.w r1, r2, r1
222 ; THUMB78-NEXT: ands r0, r1
223 ; THUMB78-NEXT: uxth r0, r0
224 ; THUMB78-NEXT: clz r0, r0
225 ; THUMB78-NEXT: lsrs r0, r0, #5
226 ; THUMB78-NEXT: bx lr
227 %t0 = shl i16 1, %y
228 %t1 = and i16 %t0, %x
229 %res = icmp eq i16 %t1, 0
230 ret i1 %res
231 }
233 define i1 @scalar_i16_bitsinmiddle_eq(i16 %x, i16 %y) nounwind {
234 ; ARM-LABEL: scalar_i16_bitsinmiddle_eq:
235 ; ARM: @ %bb.0:
236 ; ARM-NEXT: uxth r1, r1
237 ; ARM-NEXT: mov r2, #4080
238 ; ARM-NEXT: and r0, r0, r2, lsl r1
239 ; ARM-NEXT: uxth r0, r0
240 ; ARM-NEXT: clz r0, r0
241 ; ARM-NEXT: lsr r0, r0, #5
242 ; ARM-NEXT: bx lr
243 ;
244 ; THUMB6-LABEL: scalar_i16_bitsinmiddle_eq:
245 ; THUMB6: @ %bb.0:
246 ; THUMB6-NEXT: uxth r1, r1
247 ; THUMB6-NEXT: movs r2, #255
248 ; THUMB6-NEXT: lsls r2, r2, #4
249 ; THUMB6-NEXT: lsls r2, r1
250 ; THUMB6-NEXT: ands r2, r0
251 ; THUMB6-NEXT: uxth r1, r2
252 ; THUMB6-NEXT: rsbs r0, r1, #0
253 ; THUMB6-NEXT: adcs r0, r1
254 ; THUMB6-NEXT: bx lr
255 ;
256 ; THUMB78-LABEL: scalar_i16_bitsinmiddle_eq:
257 ; THUMB78: @ %bb.0:
258 ; THUMB78-NEXT: uxth r1, r1
259 ; THUMB78-NEXT: mov.w r2, #4080
260 ; THUMB78-NEXT: lsl.w r1, r2, r1
261 ; THUMB78-NEXT: ands r0, r1
262 ; THUMB78-NEXT: uxth r0, r0
263 ; THUMB78-NEXT: clz r0, r0
264 ; THUMB78-NEXT: lsrs r0, r0, #5
265 ; THUMB78-NEXT: bx lr
266 %t0 = shl i16 4080, %y
267 %t1 = and i16 %t0, %x
268 %res = icmp eq i16 %t1, 0
269 ret i1 %res
270 }
272 ; i32 scalar
274 define i1 @scalar_i32_signbit_eq(i32 %x, i32 %y) nounwind {
275 ; ARM-LABEL: scalar_i32_signbit_eq:
276 ; ARM: @ %bb.0:
277 ; ARM-NEXT: mov r2, #-2147483648
278 ; ARM-NEXT: and r0, r0, r2, lsl r1
279 ; ARM-NEXT: clz r0, r0
280 ; ARM-NEXT: lsr r0, r0, #5
281 ; ARM-NEXT: bx lr
282 ;
283 ; THUMB6-LABEL: scalar_i32_signbit_eq:
284 ; THUMB6: @ %bb.0:
285 ; THUMB6-NEXT: movs r2, #1
286 ; THUMB6-NEXT: lsls r2, r2, #31
287 ; THUMB6-NEXT: lsls r2, r1
288 ; THUMB6-NEXT: ands r2, r0
289 ; THUMB6-NEXT: rsbs r0, r2, #0
290 ; THUMB6-NEXT: adcs r0, r2
291 ; THUMB6-NEXT: bx lr
292 ;
293 ; THUMB78-LABEL: scalar_i32_signbit_eq:
294 ; THUMB78: @ %bb.0:
295 ; THUMB78-NEXT: mov.w r2, #-2147483648
296 ; THUMB78-NEXT: lsl.w r1, r2, r1
297 ; THUMB78-NEXT: ands r0, r1
298 ; THUMB78-NEXT: clz r0, r0
299 ; THUMB78-NEXT: lsrs r0, r0, #5
300 ; THUMB78-NEXT: bx lr
301 %t0 = shl i32 2147483648, %y
302 %t1 = and i32 %t0, %x
303 %res = icmp eq i32 %t1, 0
304 ret i1 %res
305 }
307 define i1 @scalar_i32_lowestbit_eq(i32 %x, i32 %y) nounwind {
308 ; ARM-LABEL: scalar_i32_lowestbit_eq:
309 ; ARM: @ %bb.0:
310 ; ARM-NEXT: mov r2, #1
311 ; ARM-NEXT: and r0, r0, r2, lsl r1
312 ; ARM-NEXT: clz r0, r0
313 ; ARM-NEXT: lsr r0, r0, #5
314 ; ARM-NEXT: bx lr
315 ;
316 ; THUMB6-LABEL: scalar_i32_lowestbit_eq:
317 ; THUMB6: @ %bb.0:
318 ; THUMB6-NEXT: movs r2, #1
319 ; THUMB6-NEXT: lsls r2, r1
320 ; THUMB6-NEXT: ands r2, r0
321 ; THUMB6-NEXT: rsbs r0, r2, #0
322 ; THUMB6-NEXT: adcs r0, r2
323 ; THUMB6-NEXT: bx lr
324 ;
325 ; THUMB78-LABEL: scalar_i32_lowestbit_eq:
326 ; THUMB78: @ %bb.0:
327 ; THUMB78-NEXT: movs r2, #1
328 ; THUMB78-NEXT: lsl.w r1, r2, r1
329 ; THUMB78-NEXT: ands r0, r1
330 ; THUMB78-NEXT: clz r0, r0
331 ; THUMB78-NEXT: lsrs r0, r0, #5
332 ; THUMB78-NEXT: bx lr
333 %t0 = shl i32 1, %y
334 %t1 = and i32 %t0, %x
335 %res = icmp eq i32 %t1, 0
336 ret i1 %res
337 }
339 define i1 @scalar_i32_bitsinmiddle_eq(i32 %x, i32 %y) nounwind {
340 ; ARM6-LABEL: scalar_i32_bitsinmiddle_eq:
341 ; ARM6: @ %bb.0:
342 ; ARM6-NEXT: mov r2, #65280
343 ; ARM6-NEXT: orr r2, r2, #16711680
344 ; ARM6-NEXT: and r0, r0, r2, lsl r1
345 ; ARM6-NEXT: clz r0, r0
346 ; ARM6-NEXT: lsr r0, r0, #5
347 ; ARM6-NEXT: bx lr
348 ;
349 ; ARM78-LABEL: scalar_i32_bitsinmiddle_eq:
350 ; ARM78: @ %bb.0:
351 ; ARM78-NEXT: movw r2, #65280
352 ; ARM78-NEXT: movt r2, #255
353 ; ARM78-NEXT: and r0, r0, r2, lsl r1
354 ; ARM78-NEXT: clz r0, r0
355 ; ARM78-NEXT: lsr r0, r0, #5
356 ; ARM78-NEXT: bx lr
357 ;
358 ; THUMB6-LABEL: scalar_i32_bitsinmiddle_eq:
359 ; THUMB6: @ %bb.0:
360 ; THUMB6-NEXT: ldr r2, .LCPI8_0
361 ; THUMB6-NEXT: lsls r2, r1
362 ; THUMB6-NEXT: ands r2, r0
363 ; THUMB6-NEXT: rsbs r0, r2, #0
364 ; THUMB6-NEXT: adcs r0, r2
365 ; THUMB6-NEXT: bx lr
366 ; THUMB6-NEXT: .p2align 2
367 ; THUMB6-NEXT: @ %bb.1:
368 ; THUMB6-NEXT: .LCPI8_0:
369 ; THUMB6-NEXT: .long 16776960 @ 0xffff00
370 ;
371 ; THUMB78-LABEL: scalar_i32_bitsinmiddle_eq:
372 ; THUMB78: @ %bb.0:
373 ; THUMB78-NEXT: movw r2, #65280
374 ; THUMB78-NEXT: movt r2, #255
375 ; THUMB78-NEXT: lsl.w r1, r2, r1
376 ; THUMB78-NEXT: ands r0, r1
377 ; THUMB78-NEXT: clz r0, r0
378 ; THUMB78-NEXT: lsrs r0, r0, #5
379 ; THUMB78-NEXT: bx lr
380 %t0 = shl i32 16776960, %y
381 %t1 = and i32 %t0, %x
382 %res = icmp eq i32 %t1, 0
383 ret i1 %res
384 }
386 ; i64 scalar
388 define i1 @scalar_i64_signbit_eq(i64 %x, i64 %y) nounwind {
389 ; ARM6-LABEL: scalar_i64_signbit_eq:
390 ; ARM6: @ %bb.0:
391 ; ARM6-NEXT: mov r0, #-2147483648
392 ; ARM6-NEXT: lsl r0, r0, r2
393 ; ARM6-NEXT: subs r2, r2, #32
394 ; ARM6-NEXT: movpl r0, #0
395 ; ARM6-NEXT: and r0, r0, r1
396 ; ARM6-NEXT: clz r0, r0
397 ; ARM6-NEXT: lsr r0, r0, #5
398 ; ARM6-NEXT: bx lr
399 ;
400 ; ARM78-LABEL: scalar_i64_signbit_eq:
401 ; ARM78: @ %bb.0:
402 ; ARM78-NEXT: mov r0, #-2147483648
403 ; ARM78-NEXT: lsl r0, r0, r2
404 ; ARM78-NEXT: subs r2, r2, #32
405 ; ARM78-NEXT: movwpl r0, #0
406 ; ARM78-NEXT: and r0, r0, r1
407 ; ARM78-NEXT: clz r0, r0
408 ; ARM78-NEXT: lsr r0, r0, #5
409 ; ARM78-NEXT: bx lr
410 ;
411 ; THUMB6-LABEL: scalar_i64_signbit_eq:
412 ; THUMB6: @ %bb.0:
413 ; THUMB6-NEXT: push {r4, r5, r7, lr}
414 ; THUMB6-NEXT: mov r4, r1
415 ; THUMB6-NEXT: mov r5, r0
416 ; THUMB6-NEXT: movs r0, #1
417 ; THUMB6-NEXT: lsls r1, r0, #31
418 ; THUMB6-NEXT: movs r0, #0
419 ; THUMB6-NEXT: bl __ashldi3
420 ; THUMB6-NEXT: ands r1, r4
421 ; THUMB6-NEXT: ands r0, r5
422 ; THUMB6-NEXT: orrs r0, r1
423 ; THUMB6-NEXT: rsbs r1, r0, #0
424 ; THUMB6-NEXT: adcs r0, r1
425 ; THUMB6-NEXT: pop {r4, r5, r7, pc}
426 ;
427 ; THUMB78-LABEL: scalar_i64_signbit_eq:
428 ; THUMB78: @ %bb.0:
429 ; THUMB78-NEXT: mov.w r0, #-2147483648
430 ; THUMB78-NEXT: lsls r0, r2
431 ; THUMB78-NEXT: subs r2, #32
432 ; THUMB78-NEXT: it pl
433 ; THUMB78-NEXT: movpl r0, #0
434 ; THUMB78-NEXT: ands r0, r1
435 ; THUMB78-NEXT: clz r0, r0
436 ; THUMB78-NEXT: lsrs r0, r0, #5
437 ; THUMB78-NEXT: bx lr
438 %t0 = shl i64 9223372036854775808, %y
439 %t1 = and i64 %t0, %x
440 %res = icmp eq i64 %t1, 0
441 ret i1 %res
442 }
444 define i1 @scalar_i64_lowestbit_eq(i64 %x, i64 %y) nounwind {
445 ; ARM6-LABEL: scalar_i64_lowestbit_eq:
446 ; ARM6: @ %bb.0:
447 ; ARM6-NEXT: push {r11, lr}
448 ; ARM6-NEXT: mov r12, #1
449 ; ARM6-NEXT: subs lr, r2, #32
450 ; ARM6-NEXT: lsl r3, r12, r2
451 ; ARM6-NEXT: rsb r2, r2, #32
452 ; ARM6-NEXT: movpl r3, #0
453 ; ARM6-NEXT: and r0, r3, r0
454 ; ARM6-NEXT: lsr r2, r12, r2
455 ; ARM6-NEXT: lslpl r2, r12, lr
456 ; ARM6-NEXT: and r1, r2, r1
457 ; ARM6-NEXT: orr r0, r0, r1
458 ; ARM6-NEXT: clz r0, r0
459 ; ARM6-NEXT: lsr r0, r0, #5
460 ; ARM6-NEXT: pop {r11, pc}
461 ;
462 ; ARM78-LABEL: scalar_i64_lowestbit_eq:
463 ; ARM78: @ %bb.0:
464 ; ARM78-NEXT: push {r11, lr}
465 ; ARM78-NEXT: mov r12, #1
466 ; ARM78-NEXT: subs lr, r2, #32
467 ; ARM78-NEXT: lsl r3, r12, r2
468 ; ARM78-NEXT: rsb r2, r2, #32
469 ; ARM78-NEXT: movwpl r3, #0
470 ; ARM78-NEXT: and r0, r3, r0
471 ; ARM78-NEXT: lsr r2, r12, r2
472 ; ARM78-NEXT: lslpl r2, r12, lr
473 ; ARM78-NEXT: and r1, r2, r1
474 ; ARM78-NEXT: orr r0, r0, r1
475 ; ARM78-NEXT: clz r0, r0
476 ; ARM78-NEXT: lsr r0, r0, #5
477 ; ARM78-NEXT: pop {r11, pc}
478 ;
479 ; THUMB6-LABEL: scalar_i64_lowestbit_eq:
480 ; THUMB6: @ %bb.0:
481 ; THUMB6-NEXT: push {r4, r5, r7, lr}
482 ; THUMB6-NEXT: mov r4, r1
483 ; THUMB6-NEXT: mov r5, r0
484 ; THUMB6-NEXT: movs r0, #1
485 ; THUMB6-NEXT: movs r1, #0
486 ; THUMB6-NEXT: bl __ashldi3
487 ; THUMB6-NEXT: ands r1, r4
488 ; THUMB6-NEXT: ands r0, r5
489 ; THUMB6-NEXT: orrs r0, r1
490 ; THUMB6-NEXT: rsbs r1, r0, #0
491 ; THUMB6-NEXT: adcs r0, r1
492 ; THUMB6-NEXT: pop {r4, r5, r7, pc}
493 ;
494 ; THUMB7-LABEL: scalar_i64_lowestbit_eq:
495 ; THUMB7: @ %bb.0:
496 ; THUMB7-NEXT: push {r7, lr}
497 ; THUMB7-NEXT: rsb.w r3, r2, #32
498 ; THUMB7-NEXT: mov.w r12, #1
499 ; THUMB7-NEXT: subs.w lr, r2, #32
500 ; THUMB7-NEXT: lsl.w r2, r12, r2
501 ; THUMB7-NEXT: lsr.w r3, r12, r3
502 ; THUMB7-NEXT: it pl
503 ; THUMB7-NEXT: lslpl.w r3, r12, lr
504 ; THUMB7-NEXT: it pl
505 ; THUMB7-NEXT: movpl r2, #0
506 ; THUMB7-NEXT: ands r1, r3
507 ; THUMB7-NEXT: ands r0, r2
508 ; THUMB7-NEXT: orrs r0, r1
509 ; THUMB7-NEXT: clz r0, r0
510 ; THUMB7-NEXT: lsrs r0, r0, #5
511 ; THUMB7-NEXT: pop {r7, pc}
512 ;
513 ; THUMB8-LABEL: scalar_i64_lowestbit_eq:
514 ; THUMB8: @ %bb.0:
515 ; THUMB8-NEXT: .save {r7, lr}
516 ; THUMB8-NEXT: push {r7, lr}
517 ; THUMB8-NEXT: subs.w r3, r2, #32
518 ; THUMB8-NEXT: mov.w r12, #1
519 ; THUMB8-NEXT: lsl.w lr, r12, r3
520 ; THUMB8-NEXT: rsb.w r3, r2, #32
521 ; THUMB8-NEXT: lsl.w r2, r12, r2
522 ; THUMB8-NEXT: lsr.w r3, r12, r3
523 ; THUMB8-NEXT: it pl
524 ; THUMB8-NEXT: movpl r3, lr
525 ; THUMB8-NEXT: it pl
526 ; THUMB8-NEXT: movpl r2, #0
527 ; THUMB8-NEXT: ands r1, r3
528 ; THUMB8-NEXT: ands r0, r2
529 ; THUMB8-NEXT: orrs r0, r1
530 ; THUMB8-NEXT: clz r0, r0
531 ; THUMB8-NEXT: lsrs r0, r0, #5
532 ; THUMB8-NEXT: pop {r7, pc}
533 %t0 = shl i64 1, %y
534 %t1 = and i64 %t0, %x
535 %res = icmp eq i64 %t1, 0
536 ret i1 %res
537 }
539 define i1 @scalar_i64_bitsinmiddle_eq(i64 %x, i64 %y) nounwind {
540 ; ARM6-LABEL: scalar_i64_bitsinmiddle_eq:
541 ; ARM6: @ %bb.0:
542 ; ARM6-NEXT: push {r4, lr}
543 ; ARM6-NEXT: mov r12, #16711680
544 ; ARM6-NEXT: subs lr, r2, #32
545 ; ARM6-NEXT: orr r12, r12, #-16777216
546 ; ARM6-NEXT: mov r4, #255
547 ; ARM6-NEXT: orr r4, r4, #65280
548 ; ARM6-NEXT: lsl r3, r12, r2
549 ; ARM6-NEXT: movpl r3, #0
550 ; ARM6-NEXT: and r0, r3, r0
551 ; ARM6-NEXT: rsb r3, r2, #32
552 ; ARM6-NEXT: cmp lr, #0
553 ; ARM6-NEXT: lsr r3, r12, r3
554 ; ARM6-NEXT: orr r2, r3, r4, lsl r2
555 ; ARM6-NEXT: lslpl r2, r12, lr
556 ; ARM6-NEXT: and r1, r2, r1
557 ; ARM6-NEXT: orr r0, r0, r1
558 ; ARM6-NEXT: clz r0, r0
559 ; ARM6-NEXT: lsr r0, r0, #5
560 ; ARM6-NEXT: pop {r4, pc}
561 ;
562 ; ARM78-LABEL: scalar_i64_bitsinmiddle_eq:
563 ; ARM78: @ %bb.0:
564 ; ARM78-NEXT: push {r4, lr}
565 ; ARM78-NEXT: movw r12, #0
566 ; ARM78-NEXT: subs lr, r2, #32
567 ; ARM78-NEXT: movt r12, #65535
568 ; ARM78-NEXT: movw r4, #65535
569 ; ARM78-NEXT: lsl r3, r12, r2
570 ; ARM78-NEXT: movwpl r3, #0
571 ; ARM78-NEXT: and r0, r3, r0
572 ; ARM78-NEXT: rsb r3, r2, #32
573 ; ARM78-NEXT: cmp lr, #0
574 ; ARM78-NEXT: lsr r3, r12, r3
575 ; ARM78-NEXT: orr r2, r3, r4, lsl r2
576 ; ARM78-NEXT: lslpl r2, r12, lr
577 ; ARM78-NEXT: and r1, r2, r1
578 ; ARM78-NEXT: orr r0, r0, r1
579 ; ARM78-NEXT: clz r0, r0
580 ; ARM78-NEXT: lsr r0, r0, #5
581 ; ARM78-NEXT: pop {r4, pc}
582 ;
583 ; THUMB6-LABEL: scalar_i64_bitsinmiddle_eq:
584 ; THUMB6: @ %bb.0:
585 ; THUMB6-NEXT: push {r4, r5, r7, lr}
586 ; THUMB6-NEXT: mov r4, r1
587 ; THUMB6-NEXT: mov r5, r0
588 ; THUMB6-NEXT: ldr r0, .LCPI11_0
589 ; THUMB6-NEXT: ldr r1, .LCPI11_1
590 ; THUMB6-NEXT: bl __ashldi3
591 ; THUMB6-NEXT: ands r1, r4
592 ; THUMB6-NEXT: ands r0, r5
593 ; THUMB6-NEXT: orrs r0, r1
594 ; THUMB6-NEXT: rsbs r1, r0, #0
595 ; THUMB6-NEXT: adcs r0, r1
596 ; THUMB6-NEXT: pop {r4, r5, r7, pc}
597 ; THUMB6-NEXT: .p2align 2
598 ; THUMB6-NEXT: @ %bb.1:
599 ; THUMB6-NEXT: .LCPI11_0:
600 ; THUMB6-NEXT: .long 4294901760 @ 0xffff0000
601 ; THUMB6-NEXT: .LCPI11_1:
602 ; THUMB6-NEXT: .long 65535 @ 0xffff
603 ;
604 ; THUMB7-LABEL: scalar_i64_bitsinmiddle_eq:
605 ; THUMB7: @ %bb.0:
606 ; THUMB7-NEXT: push {r7, lr}
607 ; THUMB7-NEXT: movw r3, #65535
608 ; THUMB7-NEXT: movw lr, #0
609 ; THUMB7-NEXT: lsl.w r12, r3, r2
610 ; THUMB7-NEXT: rsb.w r3, r2, #32
611 ; THUMB7-NEXT: movt lr, #65535
612 ; THUMB7-NEXT: lsr.w r3, lr, r3
613 ; THUMB7-NEXT: orr.w r12, r12, r3
614 ; THUMB7-NEXT: subs.w r3, r2, #32
615 ; THUMB7-NEXT: lsl.w r2, lr, r2
616 ; THUMB7-NEXT: it pl
617 ; THUMB7-NEXT: lslpl.w r12, lr, r3
618 ; THUMB7-NEXT: it pl
619 ; THUMB7-NEXT: movpl r2, #0
620 ; THUMB7-NEXT: and.w r1, r1, r12
621 ; THUMB7-NEXT: ands r0, r2
622 ; THUMB7-NEXT: orrs r0, r1
623 ; THUMB7-NEXT: clz r0, r0
624 ; THUMB7-NEXT: lsrs r0, r0, #5
625 ; THUMB7-NEXT: pop {r7, pc}
626 ;
627 ; THUMB8-LABEL: scalar_i64_bitsinmiddle_eq:
628 ; THUMB8: @ %bb.0:
629 ; THUMB8-NEXT: .save {r7, lr}
630 ; THUMB8-NEXT: push {r7, lr}
631 ; THUMB8-NEXT: movw r3, #65535
632 ; THUMB8-NEXT: movw lr, #0
633 ; THUMB8-NEXT: lsl.w r12, r3, r2
634 ; THUMB8-NEXT: rsb.w r3, r2, #32
635 ; THUMB8-NEXT: movt lr, #65535
636 ; THUMB8-NEXT: lsr.w r3, lr, r3
637 ; THUMB8-NEXT: orr.w r12, r12, r3
638 ; THUMB8-NEXT: subs.w r3, r2, #32
639 ; THUMB8-NEXT: lsl.w r2, lr, r2
640 ; THUMB8-NEXT: lsl.w r3, lr, r3
641 ; THUMB8-NEXT: it mi
642 ; THUMB8-NEXT: movmi r3, r12
643 ; THUMB8-NEXT: it pl
644 ; THUMB8-NEXT: movpl r2, #0
645 ; THUMB8-NEXT: ands r1, r3
646 ; THUMB8-NEXT: ands r0, r2
647 ; THUMB8-NEXT: orrs r0, r1
648 ; THUMB8-NEXT: clz r0, r0
649 ; THUMB8-NEXT: lsrs r0, r0, #5
650 ; THUMB8-NEXT: pop {r7, pc}
651 %t0 = shl i64 281474976645120, %y
652 %t1 = and i64 %t0, %x
653 %res = icmp eq i64 %t1, 0
654 ret i1 %res
655 }
657 ;------------------------------------------------------------------------------;
658 ; A few trivial vector tests
659 ;------------------------------------------------------------------------------;
661 define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
662 ; ARM6-LABEL: vec_4xi32_splat_eq:
663 ; ARM6: @ %bb.0:
664 ; ARM6-NEXT: push {r11, lr}
665 ; ARM6-NEXT: ldr r12, [sp, #8]
666 ; ARM6-NEXT: mov lr, #1
667 ; ARM6-NEXT: and r0, r0, lr, lsl r12
668 ; ARM6-NEXT: ldr r12, [sp, #12]
669 ; ARM6-NEXT: clz r0, r0
670 ; ARM6-NEXT: and r1, r1, lr, lsl r12
671 ; ARM6-NEXT: ldr r12, [sp, #16]
672 ; ARM6-NEXT: clz r1, r1
673 ; ARM6-NEXT: lsr r0, r0, #5
674 ; ARM6-NEXT: and r2, r2, lr, lsl r12
675 ; ARM6-NEXT: ldr r12, [sp, #20]
676 ; ARM6-NEXT: clz r2, r2
677 ; ARM6-NEXT: lsr r1, r1, #5
678 ; ARM6-NEXT: and r3, r3, lr, lsl r12
679 ; ARM6-NEXT: lsr r2, r2, #5
680 ; ARM6-NEXT: clz r3, r3
681 ; ARM6-NEXT: lsr r3, r3, #5
682 ; ARM6-NEXT: pop {r11, pc}
683 ;
684 ; ARM78-LABEL: vec_4xi32_splat_eq:
685 ; ARM78: @ %bb.0:
686 ; ARM78-NEXT: vmov.i32 q8, #0x1
687 ; ARM78-NEXT: mov r12, sp
688 ; ARM78-NEXT: vld1.64 {d18, d19}, [r12]
689 ; ARM78-NEXT: vshl.u32 q8, q8, q9
690 ; ARM78-NEXT: vmov d19, r2, r3
691 ; ARM78-NEXT: vmov d18, r0, r1
692 ; ARM78-NEXT: vtst.32 q8, q8, q9
693 ; ARM78-NEXT: vmvn q8, q8
694 ; ARM78-NEXT: vmovn.i32 d16, q8
695 ; ARM78-NEXT: vmov r0, r1, d16
696 ; ARM78-NEXT: bx lr
697 ;
698 ; THUMB6-LABEL: vec_4xi32_splat_eq:
699 ; THUMB6: @ %bb.0:
700 ; THUMB6-NEXT: push {r4, r5, r6, lr}
701 ; THUMB6-NEXT: ldr r5, [sp, #16]
702 ; THUMB6-NEXT: movs r4, #1
703 ; THUMB6-NEXT: mov r6, r4
704 ; THUMB6-NEXT: lsls r6, r5
705 ; THUMB6-NEXT: ands r6, r0
706 ; THUMB6-NEXT: rsbs r0, r6, #0
707 ; THUMB6-NEXT: adcs r0, r6
708 ; THUMB6-NEXT: ldr r5, [sp, #20]
709 ; THUMB6-NEXT: mov r6, r4
710 ; THUMB6-NEXT: lsls r6, r5
711 ; THUMB6-NEXT: ands r6, r1
712 ; THUMB6-NEXT: rsbs r1, r6, #0
713 ; THUMB6-NEXT: adcs r1, r6
714 ; THUMB6-NEXT: ldr r5, [sp, #24]
715 ; THUMB6-NEXT: mov r6, r4
716 ; THUMB6-NEXT: lsls r6, r5
717 ; THUMB6-NEXT: ands r6, r2
718 ; THUMB6-NEXT: rsbs r2, r6, #0
719 ; THUMB6-NEXT: adcs r2, r6
720 ; THUMB6-NEXT: ldr r5, [sp, #28]
721 ; THUMB6-NEXT: lsls r4, r5
722 ; THUMB6-NEXT: ands r4, r3
723 ; THUMB6-NEXT: rsbs r3, r4, #0
724 ; THUMB6-NEXT: adcs r3, r4
725 ; THUMB6-NEXT: pop {r4, r5, r6, pc}
726 ;
727 ; THUMB78-LABEL: vec_4xi32_splat_eq:
728 ; THUMB78: @ %bb.0:
729 ; THUMB78-NEXT: vmov.i32 q8, #0x1
730 ; THUMB78-NEXT: mov r12, sp
731 ; THUMB78-NEXT: vld1.64 {d18, d19}, [r12]
732 ; THUMB78-NEXT: vshl.u32 q8, q8, q9
733 ; THUMB78-NEXT: vmov d19, r2, r3
734 ; THUMB78-NEXT: vmov d18, r0, r1
735 ; THUMB78-NEXT: vtst.32 q8, q8, q9
736 ; THUMB78-NEXT: vmvn q8, q8
737 ; THUMB78-NEXT: vmovn.i32 d16, q8
738 ; THUMB78-NEXT: vmov r0, r1, d16
739 ; THUMB78-NEXT: bx lr
740 %t0 = shl <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y
741 %t1 = and <4 x i32> %t0, %x
742 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>
743 ret <4 x i1> %res
744 }
746 define <4 x i1> @vec_4xi32_nonsplat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
747 ; ARM6-LABEL: vec_4xi32_nonsplat_eq:
748 ; ARM6: @ %bb.0:
749 ; ARM6-NEXT: ldr r12, [sp, #4]
750 ; ARM6-NEXT: mov r0, #1
751 ; ARM6-NEXT: and r0, r1, r0, lsl r12
752 ; ARM6-NEXT: ldr r12, [sp, #8]
753 ; ARM6-NEXT: clz r0, r0
754 ; ARM6-NEXT: lsr r1, r0, #5
755 ; ARM6-NEXT: mov r0, #65280
756 ; ARM6-NEXT: orr r0, r0, #16711680
757 ; ARM6-NEXT: and r0, r2, r0, lsl r12
758 ; ARM6-NEXT: ldr r12, [sp, #12]
759 ; ARM6-NEXT: clz r0, r0
760 ; ARM6-NEXT: lsr r2, r0, #5
761 ; ARM6-NEXT: mov r0, #-2147483648
762 ; ARM6-NEXT: and r0, r3, r0, lsl r12
763 ; ARM6-NEXT: clz r0, r0
764 ; ARM6-NEXT: lsr r3, r0, #5
765 ; ARM6-NEXT: mov r0, #1
766 ; ARM6-NEXT: bx lr
767 ;
768 ; ARM78-LABEL: vec_4xi32_nonsplat_eq:
769 ; ARM78: @ %bb.0:
770 ; ARM78-NEXT: mov r12, sp
771 ; ARM78-NEXT: vld1.64 {d16, d17}, [r12]
772 ; ARM78-NEXT: adr r12, .LCPI13_0
773 ; ARM78-NEXT: vld1.64 {d18, d19}, [r12:128]
774 ; ARM78-NEXT: vshl.u32 q8, q9, q8
775 ; ARM78-NEXT: vmov d19, r2, r3
776 ; ARM78-NEXT: vmov d18, r0, r1
777 ; ARM78-NEXT: vtst.32 q8, q8, q9
778 ; ARM78-NEXT: vmvn q8, q8
779 ; ARM78-NEXT: vmovn.i32 d16, q8
780 ; ARM78-NEXT: vmov r0, r1, d16
781 ; ARM78-NEXT: bx lr
782 ; ARM78-NEXT: .p2align 4
783 ; ARM78-NEXT: @ %bb.1:
784 ; ARM78-NEXT: .LCPI13_0:
785 ; ARM78-NEXT: .long 0 @ 0x0
786 ; ARM78-NEXT: .long 1 @ 0x1
787 ; ARM78-NEXT: .long 16776960 @ 0xffff00
788 ; ARM78-NEXT: .long 2147483648 @ 0x80000000
789 ;
790 ; THUMB6-LABEL: vec_4xi32_nonsplat_eq:
791 ; THUMB6: @ %bb.0:
792 ; THUMB6-NEXT: push {r4, r5, r7, lr}
793 ; THUMB6-NEXT: ldr r4, [sp, #20]
794 ; THUMB6-NEXT: movs r0, #1
795 ; THUMB6-NEXT: mov r5, r0
796 ; THUMB6-NEXT: lsls r5, r4
797 ; THUMB6-NEXT: ands r5, r1
798 ; THUMB6-NEXT: rsbs r1, r5, #0
799 ; THUMB6-NEXT: adcs r1, r5
800 ; THUMB6-NEXT: ldr r4, [sp, #24]
801 ; THUMB6-NEXT: ldr r5, .LCPI13_0
802 ; THUMB6-NEXT: lsls r5, r4
803 ; THUMB6-NEXT: ands r5, r2
804 ; THUMB6-NEXT: rsbs r2, r5, #0
805 ; THUMB6-NEXT: adcs r2, r5
806 ; THUMB6-NEXT: lsls r4, r0, #31
807 ; THUMB6-NEXT: ldr r5, [sp, #28]
808 ; THUMB6-NEXT: lsls r4, r5
809 ; THUMB6-NEXT: ands r4, r3
810 ; THUMB6-NEXT: rsbs r3, r4, #0
811 ; THUMB6-NEXT: adcs r3, r4
812 ; THUMB6-NEXT: pop {r4, r5, r7, pc}
813 ; THUMB6-NEXT: .p2align 2
814 ; THUMB6-NEXT: @ %bb.1:
815 ; THUMB6-NEXT: .LCPI13_0:
816 ; THUMB6-NEXT: .long 16776960 @ 0xffff00
817 ;
818 ; THUMB78-LABEL: vec_4xi32_nonsplat_eq:
819 ; THUMB78: @ %bb.0:
820 ; THUMB78-NEXT: mov r12, sp
821 ; THUMB78-NEXT: vld1.64 {d16, d17}, [r12]
822 ; THUMB78-NEXT: adr.w r12, .LCPI13_0
823 ; THUMB78-NEXT: vld1.64 {d18, d19}, [r12:128]
824 ; THUMB78-NEXT: vshl.u32 q8, q9, q8
825 ; THUMB78-NEXT: vmov d19, r2, r3
826 ; THUMB78-NEXT: vmov d18, r0, r1
827 ; THUMB78-NEXT: vtst.32 q8, q8, q9
828 ; THUMB78-NEXT: vmvn q8, q8
829 ; THUMB78-NEXT: vmovn.i32 d16, q8
830 ; THUMB78-NEXT: vmov r0, r1, d16
831 ; THUMB78-NEXT: bx lr
832 ; THUMB78-NEXT: .p2align 4
833 ; THUMB78-NEXT: @ %bb.1:
834 ; THUMB78-NEXT: .LCPI13_0:
835 ; THUMB78-NEXT: .long 0 @ 0x0
836 ; THUMB78-NEXT: .long 1 @ 0x1
837 ; THUMB78-NEXT: .long 16776960 @ 0xffff00
838 ; THUMB78-NEXT: .long 2147483648 @ 0x80000000
839 %t0 = shl <4 x i32> <i32 0, i32 1, i32 16776960, i32 2147483648>, %y
840 %t1 = and <4 x i32> %t0, %x
841 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>
842 ret <4 x i1> %res
843 }
845 define <4 x i1> @vec_4xi32_nonsplat_undef0_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
846 ; ARM6-LABEL: vec_4xi32_nonsplat_undef0_eq:
847 ; ARM6: @ %bb.0:
848 ; ARM6-NEXT: push {r11, lr}
849 ; ARM6-NEXT: ldr r2, [sp, #12]
850 ; ARM6-NEXT: mov lr, #1
851 ; ARM6-NEXT: ldr r12, [sp, #8]
852 ; ARM6-NEXT: and r1, r1, lr, lsl r2
853 ; ARM6-NEXT: ldr r2, [sp, #20]
854 ; ARM6-NEXT: and r0, r0, lr, lsl r12
855 ; ARM6-NEXT: clz r1, r1
856 ; ARM6-NEXT: clz r0, r0
857 ; ARM6-NEXT: and r2, r3, lr, lsl r2
858 ; ARM6-NEXT: lsr r1, r1, #5
859 ; ARM6-NEXT: clz r2, r2
860 ; ARM6-NEXT: lsr r0, r0, #5
861 ; ARM6-NEXT: lsr r3, r2, #5
862 ; ARM6-NEXT: mov r2, #1
863 ; ARM6-NEXT: pop {r11, pc}
864 ;
865 ; ARM78-LABEL: vec_4xi32_nonsplat_undef0_eq:
866 ; ARM78: @ %bb.0:
867 ; ARM78-NEXT: vmov.i32 q8, #0x1
868 ; ARM78-NEXT: mov r12, sp
869 ; ARM78-NEXT: vld1.64 {d18, d19}, [r12]
870 ; ARM78-NEXT: vshl.u32 q8, q8, q9
871 ; ARM78-NEXT: vmov d19, r2, r3
872 ; ARM78-NEXT: vmov d18, r0, r1
873 ; ARM78-NEXT: vtst.32 q8, q8, q9
874 ; ARM78-NEXT: vmvn q8, q8
875 ; ARM78-NEXT: vmovn.i32 d16, q8
876 ; ARM78-NEXT: vmov r0, r1, d16
877 ; ARM78-NEXT: bx lr
878 ;
879 ; THUMB6-LABEL: vec_4xi32_nonsplat_undef0_eq:
880 ; THUMB6: @ %bb.0:
881 ; THUMB6-NEXT: push {r4, r5, r7, lr}
882 ; THUMB6-NEXT: ldr r4, [sp, #16]
883 ; THUMB6-NEXT: movs r2, #1
884 ; THUMB6-NEXT: mov r5, r2
885 ; THUMB6-NEXT: lsls r5, r4
886 ; THUMB6-NEXT: ands r5, r0
887 ; THUMB6-NEXT: rsbs r0, r5, #0
888 ; THUMB6-NEXT: adcs r0, r5
889 ; THUMB6-NEXT: ldr r4, [sp, #20]
890 ; THUMB6-NEXT: mov r5, r2
891 ; THUMB6-NEXT: lsls r5, r4
892 ; THUMB6-NEXT: ands r5, r1
893 ; THUMB6-NEXT: rsbs r1, r5, #0
894 ; THUMB6-NEXT: adcs r1, r5
895 ; THUMB6-NEXT: ldr r4, [sp, #28]
896 ; THUMB6-NEXT: mov r5, r2
897 ; THUMB6-NEXT: lsls r5, r4
898 ; THUMB6-NEXT: ands r5, r3
899 ; THUMB6-NEXT: rsbs r3, r5, #0
900 ; THUMB6-NEXT: adcs r3, r5
901 ; THUMB6-NEXT: pop {r4, r5, r7, pc}
902 ;
903 ; THUMB78-LABEL: vec_4xi32_nonsplat_undef0_eq:
904 ; THUMB78: @ %bb.0:
905 ; THUMB78-NEXT: vmov.i32 q8, #0x1
906 ; THUMB78-NEXT: mov r12, sp
907 ; THUMB78-NEXT: vld1.64 {d18, d19}, [r12]
908 ; THUMB78-NEXT: vshl.u32 q8, q8, q9
909 ; THUMB78-NEXT: vmov d19, r2, r3
910 ; THUMB78-NEXT: vmov d18, r0, r1
911 ; THUMB78-NEXT: vtst.32 q8, q8, q9
912 ; THUMB78-NEXT: vmvn q8, q8
913 ; THUMB78-NEXT: vmovn.i32 d16, q8
914 ; THUMB78-NEXT: vmov r0, r1, d16
915 ; THUMB78-NEXT: bx lr
916 %t0 = shl <4 x i32> <i32 1, i32 1, i32 undef, i32 1>, %y
917 %t1 = and <4 x i32> %t0, %x
918 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>
919 ret <4 x i1> %res
920 }
921 define <4 x i1> @vec_4xi32_nonsplat_undef1_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
922 ; ARM6-LABEL: vec_4xi32_nonsplat_undef1_eq:
923 ; ARM6: @ %bb.0:
924 ; ARM6-NEXT: push {r11, lr}
925 ; ARM6-NEXT: ldr r2, [sp, #12]
926 ; ARM6-NEXT: mov lr, #1
927 ; ARM6-NEXT: ldr r12, [sp, #8]
928 ; ARM6-NEXT: and r1, r1, lr, lsl r2
929 ; ARM6-NEXT: ldr r2, [sp, #20]
930 ; ARM6-NEXT: and r0, r0, lr, lsl r12
931 ; ARM6-NEXT: clz r1, r1
932 ; ARM6-NEXT: clz r0, r0
933 ; ARM6-NEXT: and r2, r3, lr, lsl r2
934 ; ARM6-NEXT: lsr r1, r1, #5
935 ; ARM6-NEXT: clz r2, r2
936 ; ARM6-NEXT: lsr r0, r0, #5
937 ; ARM6-NEXT: lsr r3, r2, #5
938 ; ARM6-NEXT: pop {r11, pc}
939 ;
940 ; ARM78-LABEL: vec_4xi32_nonsplat_undef1_eq:
941 ; ARM78: @ %bb.0:
942 ; ARM78-NEXT: vmov.i32 q8, #0x1
943 ; ARM78-NEXT: mov r12, sp
944 ; ARM78-NEXT: vld1.64 {d18, d19}, [r12]
945 ; ARM78-NEXT: vshl.u32 q8, q8, q9
946 ; ARM78-NEXT: vmov d19, r2, r3
947 ; ARM78-NEXT: vmov d18, r0, r1
948 ; ARM78-NEXT: vtst.32 q8, q8, q9
949 ; ARM78-NEXT: vmvn q8, q8
950 ; ARM78-NEXT: vmovn.i32 d16, q8
951 ; ARM78-NEXT: vmov r0, r1, d16
952 ; ARM78-NEXT: bx lr
953 ;
954 ; THUMB6-LABEL: vec_4xi32_nonsplat_undef1_eq:
955 ; THUMB6: @ %bb.0:
956 ; THUMB6-NEXT: push {r4, r5, r7, lr}
957 ; THUMB6-NEXT: ldr r4, [sp, #16]
958 ; THUMB6-NEXT: movs r2, #1
959 ; THUMB6-NEXT: mov r5, r2
960 ; THUMB6-NEXT: lsls r5, r4
961 ; THUMB6-NEXT: ands r5, r0
962 ; THUMB6-NEXT: rsbs r0, r5, #0
963 ; THUMB6-NEXT: adcs r0, r5
964 ; THUMB6-NEXT: ldr r4, [sp, #20]
965 ; THUMB6-NEXT: mov r5, r2
966 ; THUMB6-NEXT: lsls r5, r4
967 ; THUMB6-NEXT: ands r5, r1
968 ; THUMB6-NEXT: rsbs r1, r5, #0
969 ; THUMB6-NEXT: adcs r1, r5
970 ; THUMB6-NEXT: ldr r4, [sp, #28]
971 ; THUMB6-NEXT: lsls r2, r4
972 ; THUMB6-NEXT: ands r2, r3
973 ; THUMB6-NEXT: rsbs r3, r2, #0
974 ; THUMB6-NEXT: adcs r3, r2
975 ; THUMB6-NEXT: pop {r4, r5, r7, pc}
976 ;
977 ; THUMB78-LABEL: vec_4xi32_nonsplat_undef1_eq:
978 ; THUMB78: @ %bb.0:
979 ; THUMB78-NEXT: vmov.i32 q8, #0x1
980 ; THUMB78-NEXT: mov r12, sp
981 ; THUMB78-NEXT: vld1.64 {d18, d19}, [r12]
982 ; THUMB78-NEXT: vshl.u32 q8, q8, q9
983 ; THUMB78-NEXT: vmov d19, r2, r3
984 ; THUMB78-NEXT: vmov d18, r0, r1
985 ; THUMB78-NEXT: vtst.32 q8, q8, q9
986 ; THUMB78-NEXT: vmvn q8, q8
987 ; THUMB78-NEXT: vmovn.i32 d16, q8
988 ; THUMB78-NEXT: vmov r0, r1, d16
989 ; THUMB78-NEXT: bx lr
990 %t0 = shl <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y
991 %t1 = and <4 x i32> %t0, %x
992 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 undef, i32 0>
993 ret <4 x i1> %res
994 }
995 define <4 x i1> @vec_4xi32_nonsplat_undef2_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
996 ; ARM6-LABEL: vec_4xi32_nonsplat_undef2_eq:
997 ; ARM6: @ %bb.0:
998 ; ARM6-NEXT: push {r11, lr}
999 ; ARM6-NEXT: ldr r2, [sp, #12]
1000 ; ARM6-NEXT: mov lr, #1
1001 ; ARM6-NEXT: ldr r12, [sp, #8]
1002 ; ARM6-NEXT: and r1, r1, lr, lsl r2
1003 ; ARM6-NEXT: ldr r2, [sp, #20]
1004 ; ARM6-NEXT: and r0, r0, lr, lsl r12
1005 ; ARM6-NEXT: clz r1, r1
1006 ; ARM6-NEXT: clz r0, r0
1007 ; ARM6-NEXT: and r2, r3, lr, lsl r2
1008 ; ARM6-NEXT: lsr r1, r1, #5
1009 ; ARM6-NEXT: clz r2, r2
1010 ; ARM6-NEXT: lsr r0, r0, #5
1011 ; ARM6-NEXT: lsr r3, r2, #5
1012 ; ARM6-NEXT: pop {r11, pc}
1013 ;
1014 ; ARM78-LABEL: vec_4xi32_nonsplat_undef2_eq:
1015 ; ARM78: @ %bb.0:
1016 ; ARM78-NEXT: vmov.i32 q8, #0x1
1017 ; ARM78-NEXT: mov r12, sp
1018 ; ARM78-NEXT: vld1.64 {d18, d19}, [r12]
1019 ; ARM78-NEXT: vshl.u32 q8, q8, q9
1020 ; ARM78-NEXT: vmov d19, r2, r3
1021 ; ARM78-NEXT: vmov d18, r0, r1
1022 ; ARM78-NEXT: vtst.32 q8, q8, q9
1023 ; ARM78-NEXT: vmvn q8, q8
1024 ; ARM78-NEXT: vmovn.i32 d16, q8
1025 ; ARM78-NEXT: vmov r0, r1, d16
1026 ; ARM78-NEXT: bx lr
1027 ;
1028 ; THUMB6-LABEL: vec_4xi32_nonsplat_undef2_eq:
1029 ; THUMB6: @ %bb.0:
1030 ; THUMB6-NEXT: push {r4, r5, r7, lr}
1031 ; THUMB6-NEXT: ldr r4, [sp, #16]
1032 ; THUMB6-NEXT: movs r2, #1
1033 ; THUMB6-NEXT: mov r5, r2
1034 ; THUMB6-NEXT: lsls r5, r4
1035 ; THUMB6-NEXT: ands r5, r0
1036 ; THUMB6-NEXT: rsbs r0, r5, #0
1037 ; THUMB6-NEXT: adcs r0, r5
1038 ; THUMB6-NEXT: ldr r4, [sp, #20]
1039 ; THUMB6-NEXT: mov r5, r2
1040 ; THUMB6-NEXT: lsls r5, r4
1041 ; THUMB6-NEXT: ands r5, r1
1042 ; THUMB6-NEXT: rsbs r1, r5, #0
1043 ; THUMB6-NEXT: adcs r1, r5
1044 ; THUMB6-NEXT: ldr r4, [sp, #28]
1045 ; THUMB6-NEXT: lsls r2, r4
1046 ; THUMB6-NEXT: ands r2, r3
1047 ; THUMB6-NEXT: rsbs r3, r2, #0
1048 ; THUMB6-NEXT: adcs r3, r2
1049 ; THUMB6-NEXT: pop {r4, r5, r7, pc}
1050 ;
1051 ; THUMB78-LABEL: vec_4xi32_nonsplat_undef2_eq:
1052 ; THUMB78: @ %bb.0:
1053 ; THUMB78-NEXT: vmov.i32 q8, #0x1
1054 ; THUMB78-NEXT: mov r12, sp
1055 ; THUMB78-NEXT: vld1.64 {d18, d19}, [r12]
1056 ; THUMB78-NEXT: vshl.u32 q8, q8, q9
1057 ; THUMB78-NEXT: vmov d19, r2, r3
1058 ; THUMB78-NEXT: vmov d18, r0, r1
1059 ; THUMB78-NEXT: vtst.32 q8, q8, q9
1060 ; THUMB78-NEXT: vmvn q8, q8
1061 ; THUMB78-NEXT: vmovn.i32 d16, q8
1062 ; THUMB78-NEXT: vmov r0, r1, d16
1063 ; THUMB78-NEXT: bx lr
1064 %t0 = shl <4 x i32> <i32 1, i32 1, i32 undef, i32 1>, %y
1065 %t1 = and <4 x i32> %t0, %x
1066 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 undef, i32 0>
1067 ret <4 x i1> %res
1068 }
1070 ;------------------------------------------------------------------------------;
1071 ; A special tests
1072 ;------------------------------------------------------------------------------;
1074 define i1 @scalar_i8_signbit_ne(i8 %x, i8 %y) nounwind {
1075 ; ARM6-LABEL: scalar_i8_signbit_ne:
1076 ; ARM6: @ %bb.0:
1077 ; ARM6-NEXT: uxtb r1, r1
1078 ; ARM6-NEXT: mvn r2, #127
1079 ; ARM6-NEXT: and r0, r0, r2, lsl r1
1080 ; ARM6-NEXT: uxtb r0, r0
1081 ; ARM6-NEXT: cmp r0, #0
1082 ; ARM6-NEXT: movne r0, #1
1083 ; ARM6-NEXT: bx lr
1084 ;
1085 ; ARM78-LABEL: scalar_i8_signbit_ne:
1086 ; ARM78: @ %bb.0:
1087 ; ARM78-NEXT: uxtb r1, r1
1088 ; ARM78-NEXT: mvn r2, #127
1089 ; ARM78-NEXT: and r0, r0, r2, lsl r1
1090 ; ARM78-NEXT: uxtb r0, r0
1091 ; ARM78-NEXT: cmp r0, #0
1092 ; ARM78-NEXT: movwne r0, #1
1093 ; ARM78-NEXT: bx lr
1094 ;
1095 ; THUMB6-LABEL: scalar_i8_signbit_ne:
1096 ; THUMB6: @ %bb.0:
1097 ; THUMB6-NEXT: uxtb r1, r1
1098 ; THUMB6-NEXT: movs r2, #127
1099 ; THUMB6-NEXT: mvns r2, r2
1100 ; THUMB6-NEXT: lsls r2, r1
1101 ; THUMB6-NEXT: ands r2, r0
1102 ; THUMB6-NEXT: uxtb r0, r2
1103 ; THUMB6-NEXT: subs r1, r0, #1
1104 ; THUMB6-NEXT: sbcs r0, r1
1105 ; THUMB6-NEXT: bx lr
1106 ;
1107 ; THUMB78-LABEL: scalar_i8_signbit_ne:
1108 ; THUMB78: @ %bb.0:
1109 ; THUMB78-NEXT: uxtb r1, r1
1110 ; THUMB78-NEXT: mvn r2, #127
1111 ; THUMB78-NEXT: lsl.w r1, r2, r1
1112 ; THUMB78-NEXT: ands r0, r1
1113 ; THUMB78-NEXT: uxtb r0, r0
1114 ; THUMB78-NEXT: cmp r0, #0
1115 ; THUMB78-NEXT: it ne
1116 ; THUMB78-NEXT: movne r0, #1
1117 ; THUMB78-NEXT: bx lr
1118 %t0 = shl i8 128, %y
1119 %t1 = and i8 %t0, %x
1120 %res = icmp ne i8 %t1, 0 ; we are perfectly happy with 'ne' predicate
1121 ret i1 %res
1122 }
1124 ;------------------------------------------------------------------------------;
1125 ; What if X is a constant too?
1126 ;------------------------------------------------------------------------------;
1128 define i1 @scalar_i32_x_is_const_eq(i32 %y) nounwind {
1129 ; ARM6-LABEL: scalar_i32_x_is_const_eq:
1130 ; ARM6: @ %bb.0:
1131 ; ARM6-NEXT: ldr r1, .LCPI18_0
1132 ; ARM6-NEXT: mov r2, #1
1133 ; ARM6-NEXT: bic r0, r2, r1, lsl r0
1134 ; ARM6-NEXT: bx lr
1135 ; ARM6-NEXT: .p2align 2
1136 ; ARM6-NEXT: @ %bb.1:
1137 ; ARM6-NEXT: .LCPI18_0:
1138 ; ARM6-NEXT: .long 2857740885 @ 0xaa55aa55
1139 ;
1140 ; ARM78-LABEL: scalar_i32_x_is_const_eq:
1141 ; ARM78: @ %bb.0:
1142 ; ARM78-NEXT: movw r1, #43605
1143 ; ARM78-NEXT: mov r2, #1
1144 ; ARM78-NEXT: movt r1, #43605
1145 ; ARM78-NEXT: bic r0, r2, r1, lsl r0
1146 ; ARM78-NEXT: bx lr
1147 ;
1148 ; THUMB6-LABEL: scalar_i32_x_is_const_eq:
1149 ; THUMB6: @ %bb.0:
1150 ; THUMB6-NEXT: ldr r1, .LCPI18_0
1151 ; THUMB6-NEXT: lsls r1, r0
1152 ; THUMB6-NEXT: movs r2, #1
1153 ; THUMB6-NEXT: ands r2, r1
1154 ; THUMB6-NEXT: rsbs r0, r2, #0
1155 ; THUMB6-NEXT: adcs r0, r2
1156 ; THUMB6-NEXT: bx lr
1157 ; THUMB6-NEXT: .p2align 2
1158 ; THUMB6-NEXT: @ %bb.1:
1159 ; THUMB6-NEXT: .LCPI18_0:
1160 ; THUMB6-NEXT: .long 2857740885 @ 0xaa55aa55
1161 ;
1162 ; THUMB78-LABEL: scalar_i32_x_is_const_eq:
1163 ; THUMB78: @ %bb.0:
1164 ; THUMB78-NEXT: movw r1, #43605
1165 ; THUMB78-NEXT: movt r1, #43605
1166 ; THUMB78-NEXT: lsl.w r0, r1, r0
1167 ; THUMB78-NEXT: movs r1, #1
1168 ; THUMB78-NEXT: bic.w r0, r1, r0
1169 ; THUMB78-NEXT: bx lr
1170 %t0 = shl i32 2857740885, %y
1171 %t1 = and i32 %t0, 1
1172 %res = icmp eq i32 %t1, 0
1173 ret i1 %res
1174 }
1175 define i1 @scalar_i32_x_is_const2_eq(i32 %y) nounwind {
1176 ; ARM6-LABEL: scalar_i32_x_is_const2_eq:
1177 ; ARM6: @ %bb.0:
1178 ; ARM6-NEXT: ldr r2, .LCPI19_0
1179 ; ARM6-NEXT: mov r1, #1
1180 ; ARM6-NEXT: and r0, r2, r1, lsl r0
1181 ; ARM6-NEXT: clz r0, r0
1182 ; ARM6-NEXT: lsr r0, r0, #5
1183 ; ARM6-NEXT: bx lr
1184 ; ARM6-NEXT: .p2align 2
1185 ; ARM6-NEXT: @ %bb.1:
1186 ; ARM6-NEXT: .LCPI19_0:
1187 ; ARM6-NEXT: .long 2857740885 @ 0xaa55aa55
1188 ;
1189 ; ARM78-LABEL: scalar_i32_x_is_const2_eq:
1190 ; ARM78: @ %bb.0:
1191 ; ARM78-NEXT: movw r1, #43605
1192 ; ARM78-NEXT: mov r2, #1
1193 ; ARM78-NEXT: movt r1, #43605
1194 ; ARM78-NEXT: and r0, r1, r2, lsl r0
1195 ; ARM78-NEXT: clz r0, r0
1196 ; ARM78-NEXT: lsr r0, r0, #5
1197 ; ARM78-NEXT: bx lr
1198 ;
1199 ; THUMB6-LABEL: scalar_i32_x_is_const2_eq:
1200 ; THUMB6: @ %bb.0:
1201 ; THUMB6-NEXT: movs r1, #1
1202 ; THUMB6-NEXT: lsls r1, r0
1203 ; THUMB6-NEXT: ldr r2, .LCPI19_0
1204 ; THUMB6-NEXT: ands r2, r1
1205 ; THUMB6-NEXT: rsbs r0, r2, #0
1206 ; THUMB6-NEXT: adcs r0, r2
1207 ; THUMB6-NEXT: bx lr
1208 ; THUMB6-NEXT: .p2align 2
1209 ; THUMB6-NEXT: @ %bb.1:
1210 ; THUMB6-NEXT: .LCPI19_0:
1211 ; THUMB6-NEXT: .long 2857740885 @ 0xaa55aa55
1212 ;
1213 ; THUMB78-LABEL: scalar_i32_x_is_const2_eq:
1214 ; THUMB78: @ %bb.0:
1215 ; THUMB78-NEXT: movs r1, #1
1216 ; THUMB78-NEXT: lsl.w r0, r1, r0
1217 ; THUMB78-NEXT: movw r1, #43605
1218 ; THUMB78-NEXT: movt r1, #43605
1219 ; THUMB78-NEXT: ands r0, r1
1220 ; THUMB78-NEXT: clz r0, r0
1221 ; THUMB78-NEXT: lsrs r0, r0, #5
1222 ; THUMB78-NEXT: bx lr
1223 %t0 = shl i32 1, %y
1224 %t1 = and i32 %t0, 2857740885
1225 %res = icmp eq i32 %t1, 0
1226 ret i1 %res
1227 }
1229 ;------------------------------------------------------------------------------;
1230 ; A few negative tests
1231 ;------------------------------------------------------------------------------;
1233 define i1 @negative_scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
1234 ; ARM6-LABEL: negative_scalar_i8_bitsinmiddle_slt:
1235 ; ARM6: @ %bb.0:
1236 ; ARM6-NEXT: uxtb r1, r1
1237 ; ARM6-NEXT: mov r2, #24
1238 ; ARM6-NEXT: and r0, r0, r2, lsl r1
1239 ; ARM6-NEXT: sxtb r1, r0
1240 ; ARM6-NEXT: mov r0, #0
1241 ; ARM6-NEXT: cmp r1, #0
1242 ; ARM6-NEXT: movmi r0, #1
1243 ; ARM6-NEXT: bx lr
1244 ;
1245 ; ARM78-LABEL: negative_scalar_i8_bitsinmiddle_slt:
1246 ; ARM78: @ %bb.0:
1247 ; ARM78-NEXT: uxtb r1, r1
1248 ; ARM78-NEXT: mov r2, #24
1249 ; ARM78-NEXT: and r0, r0, r2, lsl r1
1250 ; ARM78-NEXT: sxtb r1, r0
1251 ; ARM78-NEXT: mov r0, #0
1252 ; ARM78-NEXT: cmp r1, #0
1253 ; ARM78-NEXT: movwmi r0, #1
1254 ; ARM78-NEXT: bx lr
1255 ;
1256 ; THUMB6-LABEL: negative_scalar_i8_bitsinmiddle_slt:
1257 ; THUMB6: @ %bb.0:
1258 ; THUMB6-NEXT: uxtb r1, r1
1259 ; THUMB6-NEXT: movs r2, #24
1260 ; THUMB6-NEXT: lsls r2, r1
1261 ; THUMB6-NEXT: ands r2, r0
1262 ; THUMB6-NEXT: sxtb r0, r2
1263 ; THUMB6-NEXT: cmp r0, #0
1264 ; THUMB6-NEXT: bmi .LBB20_2
1265 ; THUMB6-NEXT: @ %bb.1:
1266 ; THUMB6-NEXT: movs r0, #0
1267 ; THUMB6-NEXT: bx lr
1268 ; THUMB6-NEXT: .LBB20_2:
1269 ; THUMB6-NEXT: movs r0, #1
1270 ; THUMB6-NEXT: bx lr
1271 ;
1272 ; THUMB78-LABEL: negative_scalar_i8_bitsinmiddle_slt:
1273 ; THUMB78: @ %bb.0:
1274 ; THUMB78-NEXT: uxtb r1, r1
1275 ; THUMB78-NEXT: movs r2, #24
1276 ; THUMB78-NEXT: lsl.w r1, r2, r1
1277 ; THUMB78-NEXT: ands r0, r1
1278 ; THUMB78-NEXT: sxtb r1, r0
1279 ; THUMB78-NEXT: movs r0, #0
1280 ; THUMB78-NEXT: cmp r1, #0
1281 ; THUMB78-NEXT: it mi
1282 ; THUMB78-NEXT: movmi r0, #1
1283 ; THUMB78-NEXT: bx lr
1284 %t0 = shl i8 24, %y
1285 %t1 = and i8 %t0, %x
1286 %res = icmp slt i8 %t1, 0
1287 ret i1 %res
1288 }
1290 define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {
1291 ; ARM-LABEL: scalar_i8_signbit_eq_with_nonzero:
1292 ; ARM: @ %bb.0:
1293 ; ARM-NEXT: uxtb r1, r1
1294 ; ARM-NEXT: mvn r2, #127
1295 ; ARM-NEXT: and r0, r0, r2, lsl r1
1296 ; ARM-NEXT: mvn r1, #0
1297 ; ARM-NEXT: uxtab r0, r1, r0
1298 ; ARM-NEXT: clz r0, r0
1299 ; ARM-NEXT: lsr r0, r0, #5
1300 ; ARM-NEXT: bx lr
1301 ;
1302 ; THUMB6-LABEL: scalar_i8_signbit_eq_with_nonzero:
1303 ; THUMB6: @ %bb.0:
1304 ; THUMB6-NEXT: uxtb r1, r1
1305 ; THUMB6-NEXT: movs r2, #127
1306 ; THUMB6-NEXT: mvns r2, r2
1307 ; THUMB6-NEXT: lsls r2, r1
1308 ; THUMB6-NEXT: ands r2, r0
1309 ; THUMB6-NEXT: uxtb r0, r2
1310 ; THUMB6-NEXT: subs r1, r0, #1
1311 ; THUMB6-NEXT: rsbs r0, r1, #0
1312 ; THUMB6-NEXT: adcs r0, r1
1313 ; THUMB6-NEXT: bx lr
1314 ;
1315 ; THUMB78-LABEL: scalar_i8_signbit_eq_with_nonzero:
1316 ; THUMB78: @ %bb.0:
1317 ; THUMB78-NEXT: uxtb r1, r1
1318 ; THUMB78-NEXT: mvn r2, #127
1319 ; THUMB78-NEXT: lsl.w r1, r2, r1
1320 ; THUMB78-NEXT: ands r0, r1
1321 ; THUMB78-NEXT: mov.w r1, #-1
1322 ; THUMB78-NEXT: uxtab r0, r1, r0
1323 ; THUMB78-NEXT: clz r0, r0
1324 ; THUMB78-NEXT: lsrs r0, r0, #5
1325 ; THUMB78-NEXT: bx lr
1326 %t0 = shl i8 128, %y
1327 %t1 = and i8 %t0, %x
1328 %res = icmp eq i8 %t1, 1 ; should be comparing with 0
1329 ret i1 %res
1330 }