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HEAD
[ARM] More MVE compare vector splat combines for ANDs
[llvm-complete.git]
/
test
/
CodeGen
/
MIR
/
Generic
/
register-info.mir
blob
84a6125abe883d8ae39f285ad5d574083a58c4a1
1
# RUN: llc -run-pass none -o - %s | FileCheck %s
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# This test ensures that the MIR parser parses machine register info properties
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# correctly.
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--- |
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define i32 @foo() {
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entry:
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ret i32 0
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}
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define i32 @bar() {
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start:
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ret i32 0
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}
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...
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---
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# CHECK: name: foo
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# CHECK: tracksRegLiveness: false
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# CHECK: ...
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name: foo
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...
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---
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# CHECK: name: bar
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# CHECK: tracksRegLiveness: true
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# CHECK: ...
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name: bar
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tracksRegLiveness: true
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...