| blob | adbd7622a80c81983c0f529dcc3bbe16a47fea13 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
3 ; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck -allow-deprecated-dag-overlap %s \
4 ; RUN: -check-prefix=P9BE -implicit-check-not frsp
5 ; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
6 ; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck -allow-deprecated-dag-overlap %s \
7 ; RUN: -check-prefix=P9LE -implicit-check-not frsp
8 ; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
9 ; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck -allow-deprecated-dag-overlap %s \
10 ; RUN: -check-prefix=P8BE -implicit-check-not frsp
11 ; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
12 ; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck -allow-deprecated-dag-overlap %s \
13 ; RUN: -check-prefix=P8LE -implicit-check-not frsp
15 ; This test case comes from the following C test case (included as it may be
16 ; slightly more readable than the LLVM IR.
18 ;/* This test case provides various ways of building vectors to ensure we
19 ; produce optimal code for all cases. The cases are (for each type):
20 ; - All zeros
21 ; - All ones
22 ; - Splat of a constant
23 ; - From different values already in registers
24 ; - From different constants
25 ; - From different values in memory
26 ; - Splat of a value in register
27 ; - Splat of a value in memory
28 ; - Inserting element into existing vector
29 ; - Inserting element from existing vector into existing vector
30 ;
31 ; With conversions (float <-> int)
32 ; - Splat of a constant
33 ; - From different values already in registers
34 ; - From different constants
35 ; - From different values in memory
36 ; - Splat of a value in register
37 ; - Splat of a value in memory
38 ; - Inserting element into existing vector
39 ; - Inserting element from existing vector into existing vector
40 ;*/
41 ;
42 ;/*=================================== int ===================================*/
43 ;// P8: xxlxor //
44 ;// P9: xxlxor //
45 ;vector int allZeroi() { //
46 ; return (vector int)0; //
47 ;} //
48 ;// P8: vspltisb -1 //
49 ;// P9: xxspltisb 255 //
50 ;vector int allOnei() { //
51 ; return (vector int)-1; //
52 ;} //
53 ;// P8: vspltisw 1 //
54 ;// P9: vspltisw 1 //
55 ;vector int spltConst1i() { //
56 ; return (vector int)1; //
57 ;} //
58 ;// P8: vspltisw -15; vsrw //
59 ;// P9: vspltisw -15; vsrw //
60 ;vector int spltConst16ki() { //
61 ; return (vector int)((1<<15) - 1); //
62 ;} //
63 ;// P8: vspltisw -16; vsrw //
64 ;// P9: vspltisw -16; vsrw //
65 ;vector int spltConst32ki() { //
66 ; return (vector int)((1<<16) - 1); //
67 ;} //
68 ;// P8: 4 x mtvsrwz, 2 x xxmrgh, vmrgow //
69 ;// P9: 2 x mtvsrdd, vmrgow //
70 ;vector int fromRegsi(int a, int b, int c, int d) { //
71 ; return (vector int){ a, b, c, d }; //
72 ;} //
73 ;// P8: lxvd2x, xxswapd //
74 ;// P9: lxvx (or even lxv) //
75 ;vector int fromDiffConstsi() { //
76 ; return (vector int) { 242, -113, 889, 19 }; //
77 ;} //
78 ;// P8: lxvd2x, xxswapd //
79 ;// P9: lxvx //
80 ;vector int fromDiffMemConsAi(int *arr) { //
81 ; return (vector int) { arr[0], arr[1], arr[2], arr[3] }; //
82 ;} //
83 ;// P8: 2 x lxvd2x, 2 x xxswapd, vperm //
84 ;// P9: 2 x lxvx, vperm //
85 ;vector int fromDiffMemConsDi(int *arr) { //
86 ; return (vector int) { arr[3], arr[2], arr[1], arr[0] }; //
87 ;} //
88 ;// P8: sldi 2, lxvd2x, xxswapd //
89 ;// P9: sldi 2, lxvx //
90 ;vector int fromDiffMemVarAi(int *arr, int elem) { //
91 ; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; //
92 ;} //
93 ;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm //
94 ;// P9: sldi 2, 2 x lxvx, vperm //
95 ;vector int fromDiffMemVarDi(int *arr, int elem) { //
96 ; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; //
97 ;} //
98 ;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow //
99 ;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow //
100 ;vector int fromRandMemConsi(int *arr) { //
101 ; return (vector int) { arr[4], arr[18], arr[2], arr[88] }; //
102 ;} //
103 ;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow //
104 ;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow //
105 ;vector int fromRandMemVari(int *arr, int elem) { //
106 ; return (vector int) { arr[elem+4], arr[elem+1], arr[elem+2], arr[elem+8] };//
107 ;} //
108 ;// P8: mtvsrwz, xxspltw //
109 ;// P9: mtvsrws //
110 ;vector int spltRegVali(int val) { //
111 ; return (vector int) val; //
112 ;} //
113 ;// P8: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw //
114 ;// P9: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw //
115 ;vector int spltMemVali(int *ptr) { //
116 ; return (vector int)*ptr; //
117 ;} //
118 ;// P8: vspltisw //
119 ;// P9: vspltisw //
120 ;vector int spltCnstConvftoi() { //
121 ; return (vector int) 4.74f; //
122 ;} //
123 ;// P8: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
124 ;// P9: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
125 ;vector int fromRegsConvftoi(float a, float b, float c, float d) { //
126 ; return (vector int) { a, b, c, d }; //
127 ;} //
128 ;// P8: lxvd2x, xxswapd //
129 ;// P9: lxvx (even lxv) //
130 ;vector int fromDiffConstsConvftoi() { //
131 ; return (vector int) { 24.46f, 234.f, 988.19f, 422.39f }; //
132 ;} //
133 ;// P8: lxvd2x, xxswapd, xvcvspsxws //
134 ;// P9: lxvx, xvcvspsxws //
135 ;vector int fromDiffMemConsAConvftoi(float *ptr) { //
136 ; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; //
137 ;} //
138 ;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspsxws //
139 ;// P9: 2 x lxvx, vperm, xvcvspsxws //
140 ;vector int fromDiffMemConsDConvftoi(float *ptr) { //
141 ; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; //
142 ;} //
143 ;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
144 ;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
145 ;// Note: if the consecutive loads learns to handle pre-inc, this can be: //
146 ;// sldi 2, load, xvcvspuxws //
147 ;vector int fromDiffMemVarAConvftoi(float *arr, int elem) { //
148 ; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; //
149 ;} //
150 ;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
151 ;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
152 ;// Note: if the consecutive loads learns to handle pre-inc, this can be: //
153 ;// sldi 2, 2 x load, vperm, xvcvspuxws //
154 ;vector int fromDiffMemVarDConvftoi(float *arr, int elem) { //
155 ; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; //
156 ;} //
157 ;// P8: xscvdpsxws, xxspltw //
158 ;// P9: xscvdpsxws, xxspltw //
159 ;vector int spltRegValConvftoi(float val) { //
160 ; return (vector int) val; //
161 ;} //
162 ;// P8: lxsspx, xscvdpsxws, xxspltw //
163 ;// P9: lxvwsx, xvcvspsxws //
164 ;vector int spltMemValConvftoi(float *ptr) { //
165 ; return (vector int)*ptr; //
166 ;} //
167 ;// P8: vspltisw //
168 ;// P9: vspltisw //
169 ;vector int spltCnstConvdtoi() { //
170 ; return (vector int) 4.74; //
171 ;} //
172 ;// P8: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
173 ;// P9: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
174 ;vector int fromRegsConvdtoi(double a, double b, double c, double d) { //
175 ; return (vector int) { a, b, c, d }; //
176 ;} //
177 ;// P8: lxvd2x, xxswapd //
178 ;// P9: lxvx (even lxv) //
179 ;vector int fromDiffConstsConvdtoi() { //
180 ; return (vector int) { 24.46, 234., 988.19, 422.39 }; //
181 ;} //
182 ;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspsxws, vmrgew //
183 ;// P9: 2 x lxvx, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspsxws, vmrgew //
184 ;vector int fromDiffMemConsAConvdtoi(double *ptr) { //
185 ; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; //
186 ;} //
187 ;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
188 ;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
189 ;vector int fromDiffMemConsDConvdtoi(double *ptr) { //
190 ; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; //
191 ;} //
192 ;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
193 ;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
194 ;vector int fromDiffMemVarAConvdtoi(double *arr, int elem) { //
195 ; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; //
196 ;} //
197 ;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
198 ;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
199 ;vector int fromDiffMemVarDConvdtoi(double *arr, int elem) { //
200 ; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; //
201 ;} //
202 ;// P8: xscvdpsxws, xxspltw //
203 ;// P9: xscvdpsxws, xxspltw //
204 ;vector int spltRegValConvdtoi(double val) { //
205 ; return (vector int) val; //
206 ;} //
207 ;// P8: lxsdx, xscvdpsxws, xxspltw //
208 ;// P9: lxssp, xscvdpsxws, xxspltw //
209 ;vector int spltMemValConvdtoi(double *ptr) { //
210 ; return (vector int)*ptr; //
211 ;} //
212 ;/*=================================== int ===================================*/
213 ;/*=============================== unsigned int ==============================*/
214 ;// P8: xxlxor //
215 ;// P9: xxlxor //
216 ;vector unsigned int allZeroui() { //
217 ; return (vector unsigned int)0; //
218 ;} //
219 ;// P8: vspltisb -1 //
220 ;// P9: xxspltisb 255 //
221 ;vector unsigned int allOneui() { //
222 ; return (vector unsigned int)-1; //
223 ;} //
224 ;// P8: vspltisw 1 //
225 ;// P9: vspltisw 1 //
226 ;vector unsigned int spltConst1ui() { //
227 ; return (vector unsigned int)1; //
228 ;} //
229 ;// P8: vspltisw -15; vsrw //
230 ;// P9: vspltisw -15; vsrw //
231 ;vector unsigned int spltConst16kui() { //
232 ; return (vector unsigned int)((1<<15) - 1); //
233 ;} //
234 ;// P8: vspltisw -16; vsrw //
235 ;// P9: vspltisw -16; vsrw //
236 ;vector unsigned int spltConst32kui() { //
237 ; return (vector unsigned int)((1<<16) - 1); //
238 ;} //
239 ;// P8: 4 x mtvsrwz, 2 x xxmrghd, vmrgow //
240 ;// P9: 2 x mtvsrdd, vmrgow //
241 ;vector unsigned int fromRegsui(unsigned int a, unsigned int b, //
242 ; unsigned int c, unsigned int d) { //
243 ; return (vector unsigned int){ a, b, c, d }; //
244 ;} //
245 ;// P8: lxvd2x, xxswapd //
246 ;// P9: lxvx (or even lxv) //
247 ;vector unsigned int fromDiffConstsui() { //
248 ; return (vector unsigned int) { 242, -113, 889, 19 }; //
249 ;} //
250 ;// P8: lxvd2x, xxswapd //
251 ;// P9: lxvx //
252 ;vector unsigned int fromDiffMemConsAui(unsigned int *arr) { //
253 ; return (vector unsigned int) { arr[0], arr[1], arr[2], arr[3] }; //
254 ;} //
255 ;// P8: 2 x lxvd2x, 2 x xxswapd, vperm //
256 ;// P9: 2 x lxvx, vperm //
257 ;vector unsigned int fromDiffMemConsDui(unsigned int *arr) { //
258 ; return (vector unsigned int) { arr[3], arr[2], arr[1], arr[0] }; //
259 ;} //
260 ;// P8: sldi 2, lxvd2x, xxswapd //
261 ;// P9: sldi 2, lxvx //
262 ;vector unsigned int fromDiffMemVarAui(unsigned int *arr, int elem) { //
263 ; return (vector unsigned int) { arr[elem], arr[elem+1], //
264 ; arr[elem+2], arr[elem+3] }; //
265 ;} //
266 ;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm //
267 ;// P9: sldi 2, 2 x lxvx, vperm //
268 ;vector unsigned int fromDiffMemVarDui(unsigned int *arr, int elem) { //
269 ; return (vector unsigned int) { arr[elem], arr[elem-1], //
270 ; arr[elem-2], arr[elem-3] }; //
271 ;} //
272 ;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow //
273 ;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow //
274 ;vector unsigned int fromRandMemConsui(unsigned int *arr) { //
275 ; return (vector unsigned int) { arr[4], arr[18], arr[2], arr[88] }; //
276 ;} //
277 ;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow //
278 ;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow //
279 ;vector unsigned int fromRandMemVarui(unsigned int *arr, int elem) { //
280 ; return (vector unsigned int) { arr[elem+4], arr[elem+1], //
281 ; arr[elem+2], arr[elem+8] }; //
282 ;} //
283 ;// P8: mtvsrwz, xxspltw //
284 ;// P9: mtvsrws //
285 ;vector unsigned int spltRegValui(unsigned int val) { //
286 ; return (vector unsigned int) val; //
287 ;} //
288 ;// P8: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw //
289 ;// P9: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw //
290 ;vector unsigned int spltMemValui(unsigned int *ptr) { //
291 ; return (vector unsigned int)*ptr; //
292 ;} //
293 ;// P8: vspltisw //
294 ;// P9: vspltisw //
295 ;vector unsigned int spltCnstConvftoui() { //
296 ; return (vector unsigned int) 4.74f; //
297 ;} //
298 ;// P8: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
299 ;// P9: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
300 ;vector unsigned int fromRegsConvftoui(float a, float b, float c, float d) { //
301 ; return (vector unsigned int) { a, b, c, d }; //
302 ;} //
303 ;// P8: lxvd2x, xxswapd //
304 ;// P9: lxvx (even lxv) //
305 ;vector unsigned int fromDiffConstsConvftoui() { //
306 ; return (vector unsigned int) { 24.46f, 234.f, 988.19f, 422.39f }; //
307 ;} //
308 ;// P8: lxvd2x, xxswapd, xvcvspuxws //
309 ;// P9: lxvx, xvcvspuxws //
310 ;vector unsigned int fromDiffMemConsAConvftoui(float *ptr) { //
311 ; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; //
312 ;} //
313 ;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspuxws //
314 ;// P9: 2 x lxvx, vperm, xvcvspuxws //
315 ;vector unsigned int fromDiffMemConsDConvftoui(float *ptr) { //
316 ; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; //
317 ;} //
318 ;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
319 ;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
320 ;// Note: if the consecutive loads learns to handle pre-inc, this can be: //
321 ;// sldi 2, load, xvcvspuxws //
322 ;vector unsigned int fromDiffMemVarAConvftoui(float *arr, int elem) { //
323 ; return (vector unsigned int) { arr[elem], arr[elem+1], //
324 ; arr[elem+2], arr[elem+3] }; //
325 ;} //
326 ;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
327 ;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
328 ;// Note: if the consecutive loads learns to handle pre-inc, this can be: //
329 ;// sldi 2, 2 x load, vperm, xvcvspuxws //
330 ;vector unsigned int fromDiffMemVarDConvftoui(float *arr, int elem) { //
331 ; return (vector unsigned int) { arr[elem], arr[elem-1], //
332 ; arr[elem-2], arr[elem-3] }; //
333 ;} //
334 ;// P8: xscvdpuxws, xxspltw //
335 ;// P9: xscvdpuxws, xxspltw //
336 ;vector unsigned int spltRegValConvftoui(float val) { //
337 ; return (vector unsigned int) val; //
338 ;} //
339 ;// P8: lxsspx, xscvdpuxws, xxspltw //
340 ;// P9: lxvwsx, xvcvspuxws //
341 ;vector unsigned int spltMemValConvftoui(float *ptr) { //
342 ; return (vector unsigned int)*ptr; //
343 ;} //
344 ;// P8: vspltisw //
345 ;// P9: vspltisw //
346 ;vector unsigned int spltCnstConvdtoui() { //
347 ; return (vector unsigned int) 4.74; //
348 ;} //
349 ;// P8: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
350 ;// P9: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
351 ;vector unsigned int fromRegsConvdtoui(double a, double b, //
352 ; double c, double d) { //
353 ; return (vector unsigned int) { a, b, c, d }; //
354 ;} //
355 ;// P8: lxvd2x, xxswapd //
356 ;// P9: lxvx (even lxv) //
357 ;vector unsigned int fromDiffConstsConvdtoui() { //
358 ; return (vector unsigned int) { 24.46, 234., 988.19, 422.39 }; //
359 ;} //
360 ;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspuxws, vmrgew //
361 ;// P9: 2 x lxvx, xxmrgld, xxmrghd, 2 x xvcvspuxws, vmrgew //
362 ;vector unsigned int fromDiffMemConsAConvdtoui(double *ptr) { //
363 ; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; //
364 ;} //
365 ;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
366 ;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
367 ;vector unsigned int fromDiffMemConsDConvdtoui(double *ptr) { //
368 ; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; //
369 ;} //
370 ;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
371 ;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
372 ;vector unsigned int fromDiffMemVarAConvdtoui(double *arr, int elem) { //
373 ; return (vector unsigned int) { arr[elem], arr[elem+1], //
374 ; arr[elem+2], arr[elem+3] }; //
375 ;} //
376 ;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
377 ;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
378 ;vector unsigned int fromDiffMemVarDConvdtoui(double *arr, int elem) { //
379 ; return (vector unsigned int) { arr[elem], arr[elem-1], //
380 ; arr[elem-2], arr[elem-3] }; //
381 ;} //
382 ;// P8: xscvdpuxws, xxspltw //
383 ;// P9: xscvdpuxws, xxspltw //
384 ;vector unsigned int spltRegValConvdtoui(double val) { //
385 ; return (vector unsigned int) val; //
386 ;} //
387 ;// P8: lxsspx, xscvdpuxws, xxspltw //
388 ;// P9: lfd, xscvdpuxws, xxspltw //
389 ;vector unsigned int spltMemValConvdtoui(double *ptr) { //
390 ; return (vector unsigned int)*ptr; //
391 ;} //
392 ;/*=============================== unsigned int ==============================*/
393 ;/*=============================== long long =================================*/
394 ;// P8: xxlxor //
395 ;// P9: xxlxor //
396 ;vector long long allZeroll() { //
397 ; return (vector long long)0; //
398 ;} //
399 ;// P8: vspltisb -1 //
400 ;// P9: xxspltisb 255 //
401 ;vector long long allOnell() { //
402 ; return (vector long long)-1; //
403 ;} //
404 ;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
405 ;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
406 ;vector long long spltConst1ll() { //
407 ; return (vector long long)1; //
408 ;} //
409 ;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
410 ;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
411 ;vector long long spltConst16kll() { //
412 ; return (vector long long)((1<<15) - 1); //
413 ;} //
414 ;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
415 ;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
416 ;vector long long spltConst32kll() { //
417 ; return (vector long long)((1<<16) - 1); //
418 ;} //
419 ;// P8: 2 x mtvsrd, xxmrghd //
420 ;// P9: mtvsrdd //
421 ;vector long long fromRegsll(long long a, long long b) { //
422 ; return (vector long long){ a, b }; //
423 ;} //
424 ;// P8: lxvd2x, xxswapd //
425 ;// P9: lxvx (or even lxv) //
426 ;vector long long fromDiffConstsll() { //
427 ; return (vector long long) { 242, -113 }; //
428 ;} //
429 ;// P8: lxvd2x, xxswapd //
430 ;// P9: lxvx //
431 ;vector long long fromDiffMemConsAll(long long *arr) { //
432 ; return (vector long long) { arr[0], arr[1] }; //
433 ;} //
434 ;// P8: lxvd2x //
435 ;// P9: lxvx, xxswapd (maybe just use lxvd2x) //
436 ;vector long long fromDiffMemConsDll(long long *arr) { //
437 ; return (vector long long) { arr[3], arr[2] }; //
438 ;} //
439 ;// P8: sldi 3, lxvd2x, xxswapd //
440 ;// P9: sldi 3, lxvx //
441 ;vector long long fromDiffMemVarAll(long long *arr, int elem) { //
442 ; return (vector long long) { arr[elem], arr[elem+1] }; //
443 ;} //
444 ;// P8: sldi 3, lxvd2x //
445 ;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) //
446 ;vector long long fromDiffMemVarDll(long long *arr, int elem) { //
447 ; return (vector long long) { arr[elem], arr[elem-1] }; //
448 ;} //
449 ;// P8: 2 x ld, 2 x mtvsrd, xxmrghd //
450 ;// P9: 2 x ld, mtvsrdd //
451 ;vector long long fromRandMemConsll(long long *arr) { //
452 ; return (vector long long) { arr[4], arr[18] }; //
453 ;} //
454 ;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd //
455 ;// P9: sldi 3, add, 2 x ld, mtvsrdd //
456 ;vector long long fromRandMemVarll(long long *arr, int elem) { //
457 ; return (vector long long) { arr[elem+4], arr[elem+1] }; //
458 ;} //
459 ;// P8: mtvsrd, xxspltd //
460 ;// P9: mtvsrdd //
461 ;vector long long spltRegValll(long long val) { //
462 ; return (vector long long) val; //
463 ;} //
464 ;// P8: lxvdsx //
465 ;// P9: lxvdsx //
466 ;vector long long spltMemValll(long long *ptr) { //
467 ; return (vector long long)*ptr; //
468 ;} //
469 ;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
470 ;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
471 ;vector long long spltCnstConvftoll() { //
472 ; return (vector long long) 4.74f; //
473 ;} //
474 ;// P8: xxmrghd, xvcvdpsxds //
475 ;// P9: xxmrghd, xvcvdpsxds //
476 ;vector long long fromRegsConvftoll(float a, float b) { //
477 ; return (vector long long) { a, b }; //
478 ;} //
479 ;// P8: lxvd2x, xxswapd //
480 ;// P9: lxvx (even lxv) //
481 ;vector long long fromDiffConstsConvftoll() { //
482 ; return (vector long long) { 24.46f, 234.f }; //
483 ;} //
484 ;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds //
485 ;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds //
486 ;vector long long fromDiffMemConsAConvftoll(float *ptr) { //
487 ; return (vector long long) { ptr[0], ptr[1] }; //
488 ;} //
489 ;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds //
490 ;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds //
491 ;vector long long fromDiffMemConsDConvftoll(float *ptr) { //
492 ; return (vector long long) { ptr[3], ptr[2] }; //
493 ;} //
494 ;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds //
495 ;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds //
496 ;vector long long fromDiffMemVarAConvftoll(float *arr, int elem) { //
497 ; return (vector long long) { arr[elem], arr[elem+1] }; //
498 ;} //
499 ;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds //
500 ;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds //
501 ;vector long long fromDiffMemVarDConvftoll(float *arr, int elem) { //
502 ; return (vector long long) { arr[elem], arr[elem-1] }; //
503 ;} //
504 ;// P8: xscvdpsxds, xxspltd //
505 ;// P9: xscvdpsxds, xxspltd //
506 ;vector long long spltRegValConvftoll(float val) { //
507 ; return (vector long long) val; //
508 ;} //
509 ;// P8: lxsspx, xscvdpsxds, xxspltd //
510 ;// P9: lfs, xscvdpsxds, xxspltd //
511 ;vector long long spltMemValConvftoll(float *ptr) { //
512 ; return (vector long long)*ptr; //
513 ;} //
514 ;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
515 ;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
516 ;vector long long spltCnstConvdtoll() { //
517 ; return (vector long long) 4.74; //
518 ;} //
519 ;// P8: xxmrghd, xvcvdpsxds //
520 ;// P9: xxmrghd, xvcvdpsxds //
521 ;vector long long fromRegsConvdtoll(double a, double b) { //
522 ; return (vector long long) { a, b }; //
523 ;} //
524 ;// P8: lxvd2x, xxswapd //
525 ;// P9: lxvx (even lxv) //
526 ;vector long long fromDiffConstsConvdtoll() { //
527 ; return (vector long long) { 24.46, 234. }; //
528 ;} //
529 ;// P8: lxvd2x, xxswapd, xvcvdpsxds //
530 ;// P9: lxvx, xvcvdpsxds //
531 ;vector long long fromDiffMemConsAConvdtoll(double *ptr) { //
532 ; return (vector long long) { ptr[0], ptr[1] }; //
533 ;} //
534 ;// P8: lxvd2x, xvcvdpsxds //
535 ;// P9: lxvx, xxswapd, xvcvdpsxds //
536 ;vector long long fromDiffMemConsDConvdtoll(double *ptr) { //
537 ; return (vector long long) { ptr[3], ptr[2] }; //
538 ;} //
539 ;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpsxds //
540 ;// P9: sldi 3, lxvx, xvcvdpsxds //
541 ;vector long long fromDiffMemVarAConvdtoll(double *arr, int elem) { //
542 ; return (vector long long) { arr[elem], arr[elem+1] }; //
543 ;} //
544 ;// P8: sldi 3, lxvd2x, xvcvdpsxds //
545 ;// P9: sldi 3, lxvx, xxswapd, xvcvdpsxds //
546 ;vector long long fromDiffMemVarDConvdtoll(double *arr, int elem) { //
547 ; return (vector long long) { arr[elem], arr[elem-1] }; //
548 ;} //
549 ;// P8: xscvdpsxds, xxspltd //
550 ;// P9: xscvdpsxds, xxspltd //
551 ;vector long long spltRegValConvdtoll(double val) { //
552 ; return (vector long long) val; //
553 ;} //
554 ;// P8: lxvdsx, xvcvdpsxds //
555 ;// P9: lxvdsx, xvcvdpsxds //
556 ;vector long long spltMemValConvdtoll(double *ptr) { //
557 ; return (vector long long)*ptr; //
558 ;} //
559 ;/*=============================== long long =================================*/
560 ;/*========================== unsigned long long =============================*/
561 ;// P8: xxlxor //
562 ;// P9: xxlxor //
563 ;vector unsigned long long allZeroull() { //
564 ; return (vector unsigned long long)0; //
565 ;} //
566 ;// P8: vspltisb -1 //
567 ;// P9: xxspltisb 255 //
568 ;vector unsigned long long allOneull() { //
569 ; return (vector unsigned long long)-1; //
570 ;} //
571 ;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
572 ;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
573 ;vector unsigned long long spltConst1ull() { //
574 ; return (vector unsigned long long)1; //
575 ;} //
576 ;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
577 ;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
578 ;vector unsigned long long spltConst16kull() { //
579 ; return (vector unsigned long long)((1<<15) - 1); //
580 ;} //
581 ;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
582 ;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
583 ;vector unsigned long long spltConst32kull() { //
584 ; return (vector unsigned long long)((1<<16) - 1); //
585 ;} //
586 ;// P8: 2 x mtvsrd, xxmrghd //
587 ;// P9: mtvsrdd //
588 ;vector unsigned long long fromRegsull(unsigned long long a, //
589 ; unsigned long long b) { //
590 ; return (vector unsigned long long){ a, b }; //
591 ;} //
592 ;// P8: lxvd2x, xxswapd //
593 ;// P9: lxvx (or even lxv) //
594 ;vector unsigned long long fromDiffConstsull() { //
595 ; return (vector unsigned long long) { 242, -113 }; //
596 ;} //
597 ;// P8: lxvd2x, xxswapd //
598 ;// P9: lxvx //
599 ;vector unsigned long long fromDiffMemConsAull(unsigned long long *arr) { //
600 ; return (vector unsigned long long) { arr[0], arr[1] }; //
601 ;} //
602 ;// P8: lxvd2x //
603 ;// P9: lxvx, xxswapd (maybe just use lxvd2x) //
604 ;vector unsigned long long fromDiffMemConsDull(unsigned long long *arr) { //
605 ; return (vector unsigned long long) { arr[3], arr[2] }; //
606 ;} //
607 ;// P8: sldi 3, lxvd2x, xxswapd //
608 ;// P9: sldi 3, lxvx //
609 ;vector unsigned long long fromDiffMemVarAull(unsigned long long *arr, //
610 ; int elem) { //
611 ; return (vector unsigned long long) { arr[elem], arr[elem+1] }; //
612 ;} //
613 ;// P8: sldi 3, lxvd2x //
614 ;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) //
615 ;vector unsigned long long fromDiffMemVarDull(unsigned long long *arr, //
616 ; int elem) { //
617 ; return (vector unsigned long long) { arr[elem], arr[elem-1] }; //
618 ;} //
619 ;// P8: 2 x ld, 2 x mtvsrd, xxmrghd //
620 ;// P9: 2 x ld, mtvsrdd //
621 ;vector unsigned long long fromRandMemConsull(unsigned long long *arr) { //
622 ; return (vector unsigned long long) { arr[4], arr[18] }; //
623 ;} //
624 ;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd //
625 ;// P9: sldi 3, add, 2 x ld, mtvsrdd //
626 ;vector unsigned long long fromRandMemVarull(unsigned long long *arr, //
627 ; int elem) { //
628 ; return (vector unsigned long long) { arr[elem+4], arr[elem+1] }; //
629 ;} //
630 ;// P8: mtvsrd, xxspltd //
631 ;// P9: mtvsrdd //
632 ;vector unsigned long long spltRegValull(unsigned long long val) { //
633 ; return (vector unsigned long long) val; //
634 ;} //
635 ;// P8: lxvdsx //
636 ;// P9: lxvdsx //
637 ;vector unsigned long long spltMemValull(unsigned long long *ptr) { //
638 ; return (vector unsigned long long)*ptr; //
639 ;} //
640 ;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
641 ;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
642 ;vector unsigned long long spltCnstConvftoull() { //
643 ; return (vector unsigned long long) 4.74f; //
644 ;} //
645 ;// P8: xxmrghd, xvcvdpuxds //
646 ;// P9: xxmrghd, xvcvdpuxds //
647 ;vector unsigned long long fromRegsConvftoull(float a, float b) { //
648 ; return (vector unsigned long long) { a, b }; //
649 ;} //
650 ;// P8: lxvd2x, xxswapd //
651 ;// P9: lxvx (even lxv) //
652 ;vector unsigned long long fromDiffConstsConvftoull() { //
653 ; return (vector unsigned long long) { 24.46f, 234.f }; //
654 ;} //
655 ;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds //
656 ;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds //
657 ;vector unsigned long long fromDiffMemConsAConvftoull(float *ptr) { //
658 ; return (vector unsigned long long) { ptr[0], ptr[1] }; //
659 ;} //
660 ;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds //
661 ;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds //
662 ;vector unsigned long long fromDiffMemConsDConvftoull(float *ptr) { //
663 ; return (vector unsigned long long) { ptr[3], ptr[2] }; //
664 ;} //
665 ;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds //
666 ;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds //
667 ;vector unsigned long long fromDiffMemVarAConvftoull(float *arr, int elem) { //
668 ; return (vector unsigned long long) { arr[elem], arr[elem+1] }; //
669 ;} //
670 ;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds //
671 ;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds //
672 ;vector unsigned long long fromDiffMemVarDConvftoull(float *arr, int elem) { //
673 ; return (vector unsigned long long) { arr[elem], arr[elem-1] }; //
674 ;} //
675 ;// P8: xscvdpuxds, xxspltd //
676 ;// P9: xscvdpuxds, xxspltd //
677 ;vector unsigned long long spltRegValConvftoull(float val) { //
678 ; return (vector unsigned long long) val; //
679 ;} //
680 ;// P8: lxsspx, xscvdpuxds, xxspltd //
681 ;// P9: lfs, xscvdpuxds, xxspltd //
682 ;vector unsigned long long spltMemValConvftoull(float *ptr) { //
683 ; return (vector unsigned long long)*ptr; //
684 ;} //
685 ;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
686 ;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
687 ;vector unsigned long long spltCnstConvdtoull() { //
688 ; return (vector unsigned long long) 4.74; //
689 ;} //
690 ;// P8: xxmrghd, xvcvdpuxds //
691 ;// P9: xxmrghd, xvcvdpuxds //
692 ;vector unsigned long long fromRegsConvdtoull(double a, double b) { //
693 ; return (vector unsigned long long) { a, b }; //
694 ;} //
695 ;// P8: lxvd2x, xxswapd //
696 ;// P9: lxvx (even lxv) //
697 ;vector unsigned long long fromDiffConstsConvdtoull() { //
698 ; return (vector unsigned long long) { 24.46, 234. }; //
699 ;} //
700 ;// P8: lxvd2x, xxswapd, xvcvdpuxds //
701 ;// P9: lxvx, xvcvdpuxds //
702 ;vector unsigned long long fromDiffMemConsAConvdtoull(double *ptr) { //
703 ; return (vector unsigned long long) { ptr[0], ptr[1] }; //
704 ;} //
705 ;// P8: lxvd2x, xvcvdpuxds //
706 ;// P9: lxvx, xxswapd, xvcvdpuxds //
707 ;vector unsigned long long fromDiffMemConsDConvdtoull(double *ptr) { //
708 ; return (vector unsigned long long) { ptr[3], ptr[2] }; //
709 ;} //
710 ;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpuxds //
711 ;// P9: sldi 3, lxvx, xvcvdpuxds //
712 ;vector unsigned long long fromDiffMemVarAConvdtoull(double *arr, int elem) { //
713 ; return (vector unsigned long long) { arr[elem], arr[elem+1] }; //
714 ;} //
715 ;// P8: sldi 3, lxvd2x, xvcvdpuxds //
716 ;// P9: sldi 3, lxvx, xxswapd, xvcvdpuxds //
717 ;vector unsigned long long fromDiffMemVarDConvdtoull(double *arr, int elem) { //
718 ; return (vector unsigned long long) { arr[elem], arr[elem-1] }; //
719 ;} //
720 ;// P8: xscvdpuxds, xxspltd //
721 ;// P9: xscvdpuxds, xxspltd //
722 ;vector unsigned long long spltRegValConvdtoull(double val) { //
723 ; return (vector unsigned long long) val; //
724 ;} //
725 ;// P8: lxvdsx, xvcvdpuxds //
726 ;// P9: lxvdsx, xvcvdpuxds //
727 ;vector unsigned long long spltMemValConvdtoull(double *ptr) { //
728 ; return (vector unsigned long long)*ptr; //
729 ;} //
730 ;/*========================== unsigned long long ==============================*/
732 ; Function Attrs: norecurse nounwind readnone
733 define <4 x i32> @allZeroi() {
734 ; P9BE-LABEL: allZeroi:
735 ; P9BE: # %bb.0: # %entry
736 ; P9BE-NEXT: xxlxor v2, v2, v2
737 ; P9BE-NEXT: blr
738 ;
739 ; P9LE-LABEL: allZeroi:
740 ; P9LE: # %bb.0: # %entry
741 ; P9LE-NEXT: xxlxor v2, v2, v2
742 ; P9LE-NEXT: blr
743 ;
744 ; P8BE-LABEL: allZeroi:
745 ; P8BE: # %bb.0: # %entry
746 ; P8BE-NEXT: xxlxor v2, v2, v2
747 ; P8BE-NEXT: blr
748 ;
749 ; P8LE-LABEL: allZeroi:
750 ; P8LE: # %bb.0: # %entry
751 ; P8LE-NEXT: xxlxor v2, v2, v2
752 ; P8LE-NEXT: blr
753 entry:
754 ret <4 x i32> zeroinitializer
755 }
757 ; Function Attrs: norecurse nounwind readnone
758 define <4 x i32> @allOnei() {
759 ; P9BE-LABEL: allOnei:
760 ; P9BE: # %bb.0: # %entry
761 ; P9BE-NEXT: xxspltib v2, 255
762 ; P9BE-NEXT: blr
763 ;
764 ; P9LE-LABEL: allOnei:
765 ; P9LE: # %bb.0: # %entry
766 ; P9LE-NEXT: xxspltib v2, 255
767 ; P9LE-NEXT: blr
768 ;
769 ; P8BE-LABEL: allOnei:
770 ; P8BE: # %bb.0: # %entry
771 ; P8BE-NEXT: vspltisb v2, -1
772 ; P8BE-NEXT: blr
773 ;
774 ; P8LE-LABEL: allOnei:
775 ; P8LE: # %bb.0: # %entry
776 ; P8LE-NEXT: vspltisb v2, -1
777 ; P8LE-NEXT: blr
778 entry:
779 ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
780 }
782 ; Function Attrs: norecurse nounwind readnone
783 define <4 x i32> @spltConst1i() {
784 ; P9BE-LABEL: spltConst1i:
785 ; P9BE: # %bb.0: # %entry
786 ; P9BE-NEXT: vspltisw v2, 1
787 ; P9BE-NEXT: blr
788 ;
789 ; P9LE-LABEL: spltConst1i:
790 ; P9LE: # %bb.0: # %entry
791 ; P9LE-NEXT: vspltisw v2, 1
792 ; P9LE-NEXT: blr
793 ;
794 ; P8BE-LABEL: spltConst1i:
795 ; P8BE: # %bb.0: # %entry
796 ; P8BE-NEXT: vspltisw v2, 1
797 ; P8BE-NEXT: blr
798 ;
799 ; P8LE-LABEL: spltConst1i:
800 ; P8LE: # %bb.0: # %entry
801 ; P8LE-NEXT: vspltisw v2, 1
802 ; P8LE-NEXT: blr
803 entry:
804 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1>
805 }
807 ; Function Attrs: norecurse nounwind readnone
808 define <4 x i32> @spltConst16ki() {
809 ; P9BE-LABEL: spltConst16ki:
810 ; P9BE: # %bb.0: # %entry
811 ; P9BE-NEXT: vspltisw v2, -15
812 ; P9BE-NEXT: vsrw v2, v2, v2
813 ; P9BE-NEXT: blr
814 ;
815 ; P9LE-LABEL: spltConst16ki:
816 ; P9LE: # %bb.0: # %entry
817 ; P9LE-NEXT: vspltisw v2, -15
818 ; P9LE-NEXT: vsrw v2, v2, v2
819 ; P9LE-NEXT: blr
820 ;
821 ; P8BE-LABEL: spltConst16ki:
822 ; P8BE: # %bb.0: # %entry
823 ; P8BE-NEXT: vspltisw v2, -15
824 ; P8BE-NEXT: vsrw v2, v2, v2
825 ; P8BE-NEXT: blr
826 ;
827 ; P8LE-LABEL: spltConst16ki:
828 ; P8LE: # %bb.0: # %entry
829 ; P8LE-NEXT: vspltisw v2, -15
830 ; P8LE-NEXT: vsrw v2, v2, v2
831 ; P8LE-NEXT: blr
832 entry:
833 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>
834 }
836 ; Function Attrs: norecurse nounwind readnone
837 define <4 x i32> @spltConst32ki() {
838 ; P9BE-LABEL: spltConst32ki:
839 ; P9BE: # %bb.0: # %entry
840 ; P9BE-NEXT: vspltisw v2, -16
841 ; P9BE-NEXT: vsrw v2, v2, v2
842 ; P9BE-NEXT: blr
843 ;
844 ; P9LE-LABEL: spltConst32ki:
845 ; P9LE: # %bb.0: # %entry
846 ; P9LE-NEXT: vspltisw v2, -16
847 ; P9LE-NEXT: vsrw v2, v2, v2
848 ; P9LE-NEXT: blr
849 ;
850 ; P8BE-LABEL: spltConst32ki:
851 ; P8BE: # %bb.0: # %entry
852 ; P8BE-NEXT: vspltisw v2, -16
853 ; P8BE-NEXT: vsrw v2, v2, v2
854 ; P8BE-NEXT: blr
855 ;
856 ; P8LE-LABEL: spltConst32ki:
857 ; P8LE: # %bb.0: # %entry
858 ; P8LE-NEXT: vspltisw v2, -16
859 ; P8LE-NEXT: vsrw v2, v2, v2
860 ; P8LE-NEXT: blr
861 entry:
862 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
863 }
865 ; Function Attrs: norecurse nounwind readnone
866 define <4 x i32> @fromRegsi(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) {
867 ; P9BE-LABEL: fromRegsi:
868 ; P9BE: # %bb.0: # %entry
869 ; P9BE-NEXT: rldimi r6, r5, 32, 0
870 ; P9BE-NEXT: rldimi r4, r3, 32, 0
871 ; P9BE-NEXT: mtvsrdd v2, r4, r6
872 ; P9BE-NEXT: blr
873 ;
874 ; P9LE-LABEL: fromRegsi:
875 ; P9LE: # %bb.0: # %entry
876 ; P9LE-NEXT: rldimi r3, r4, 32, 0
877 ; P9LE-NEXT: rldimi r5, r6, 32, 0
878 ; P9LE-NEXT: mtvsrdd v2, r5, r3
879 ; P9LE-NEXT: blr
880 ;
881 ; P8BE-LABEL: fromRegsi:
882 ; P8BE: # %bb.0: # %entry
883 ; P8BE-NEXT: rldimi r6, r5, 32, 0
884 ; P8BE-NEXT: rldimi r4, r3, 32, 0
885 ; P8BE-NEXT: mtvsrd f0, r6
886 ; P8BE-NEXT: mtvsrd f1, r4
887 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
888 ; P8BE-NEXT: blr
889 ;
890 ; P8LE-LABEL: fromRegsi:
891 ; P8LE: # %bb.0: # %entry
892 ; P8LE-NEXT: rldimi r3, r4, 32, 0
893 ; P8LE-NEXT: rldimi r5, r6, 32, 0
894 ; P8LE-NEXT: mtvsrd f0, r3
895 ; P8LE-NEXT: mtvsrd f1, r5
896 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
897 ; P8LE-NEXT: blr
898 entry:
899 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0
900 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1
901 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2
902 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3
903 ret <4 x i32> %vecinit3
904 }
906 ; Function Attrs: norecurse nounwind readnone
907 define <4 x i32> @fromDiffConstsi() {
908 ; P9BE-LABEL: fromDiffConstsi:
909 ; P9BE: # %bb.0: # %entry
910 ; P9BE-NEXT: addis r3, r2, .LCPI6_0@toc@ha
911 ; P9BE-NEXT: addi r3, r3, .LCPI6_0@toc@l
912 ; P9BE-NEXT: lxvx v2, 0, r3
913 ; P9BE-NEXT: blr
914 ;
915 ; P9LE-LABEL: fromDiffConstsi:
916 ; P9LE: # %bb.0: # %entry
917 ; P9LE-NEXT: addis r3, r2, .LCPI6_0@toc@ha
918 ; P9LE-NEXT: addi r3, r3, .LCPI6_0@toc@l
919 ; P9LE-NEXT: lxvx v2, 0, r3
920 ; P9LE-NEXT: blr
921 ;
922 ; P8BE-LABEL: fromDiffConstsi:
923 ; P8BE: # %bb.0: # %entry
924 ; P8BE-NEXT: addis r3, r2, .LCPI6_0@toc@ha
925 ; P8BE-NEXT: addi r3, r3, .LCPI6_0@toc@l
926 ; P8BE-NEXT: lxvw4x v2, 0, r3
927 ; P8BE-NEXT: blr
928 ;
929 ; P8LE-LABEL: fromDiffConstsi:
930 ; P8LE: # %bb.0: # %entry
931 ; P8LE-NEXT: addis r3, r2, .LCPI6_0@toc@ha
932 ; P8LE-NEXT: addi r3, r3, .LCPI6_0@toc@l
933 ; P8LE-NEXT: lvx v2, 0, r3
934 ; P8LE-NEXT: blr
935 entry:
936 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19>
937 }
939 ; Function Attrs: norecurse nounwind readonly
940 define <4 x i32> @fromDiffMemConsAi(i32* nocapture readonly %arr) {
941 ; P9BE-LABEL: fromDiffMemConsAi:
942 ; P9BE: # %bb.0: # %entry
943 ; P9BE-NEXT: lxv v2, 0(r3)
944 ; P9BE-NEXT: blr
945 ;
946 ; P9LE-LABEL: fromDiffMemConsAi:
947 ; P9LE: # %bb.0: # %entry
948 ; P9LE-NEXT: lxv v2, 0(r3)
949 ; P9LE-NEXT: blr
950 ;
951 ; P8BE-LABEL: fromDiffMemConsAi:
952 ; P8BE: # %bb.0: # %entry
953 ; P8BE-NEXT: lxvw4x v2, 0, r3
954 ; P8BE-NEXT: blr
955 ;
956 ; P8LE-LABEL: fromDiffMemConsAi:
957 ; P8LE: # %bb.0: # %entry
958 ; P8LE-NEXT: lxvd2x vs0, 0, r3
959 ; P8LE-NEXT: xxswapd v2, vs0
960 ; P8LE-NEXT: blr
961 entry:
962 %0 = load i32, i32* %arr, align 4
963 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
964 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 1
965 %1 = load i32, i32* %arrayidx1, align 4
966 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
967 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2
968 %2 = load i32, i32* %arrayidx3, align 4
969 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2
970 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 3
971 %3 = load i32, i32* %arrayidx5, align 4
972 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3
973 ret <4 x i32> %vecinit6
974 }
976 ; Function Attrs: norecurse nounwind readonly
977 define <4 x i32> @fromDiffMemConsDi(i32* nocapture readonly %arr) {
978 ; P9BE-LABEL: fromDiffMemConsDi:
979 ; P9BE: # %bb.0: # %entry
980 ; P9BE-NEXT: lxv v2, 0(r3)
981 ; P9BE-NEXT: addis r3, r2, .LCPI8_0@toc@ha
982 ; P9BE-NEXT: addi r3, r3, .LCPI8_0@toc@l
983 ; P9BE-NEXT: lxvx v3, 0, r3
984 ; P9BE-NEXT: vperm v2, v2, v2, v3
985 ; P9BE-NEXT: blr
986 ;
987 ; P9LE-LABEL: fromDiffMemConsDi:
988 ; P9LE: # %bb.0: # %entry
989 ; P9LE-NEXT: lxv v2, 0(r3)
990 ; P9LE-NEXT: addis r3, r2, .LCPI8_0@toc@ha
991 ; P9LE-NEXT: addi r3, r3, .LCPI8_0@toc@l
992 ; P9LE-NEXT: lxvx v3, 0, r3
993 ; P9LE-NEXT: vperm v2, v2, v2, v3
994 ; P9LE-NEXT: blr
995 ;
996 ; P8BE-LABEL: fromDiffMemConsDi:
997 ; P8BE: # %bb.0: # %entry
998 ; P8BE-NEXT: addis r4, r2, .LCPI8_0@toc@ha
999 ; P8BE-NEXT: lxvw4x v2, 0, r3
1000 ; P8BE-NEXT: addi r4, r4, .LCPI8_0@toc@l
1001 ; P8BE-NEXT: lxvw4x v3, 0, r4
1002 ; P8BE-NEXT: vperm v2, v2, v2, v3
1003 ; P8BE-NEXT: blr
1004 ;
1005 ; P8LE-LABEL: fromDiffMemConsDi:
1006 ; P8LE: # %bb.0: # %entry
1007 ; P8LE-NEXT: lxvd2x vs0, 0, r3
1008 ; P8LE-NEXT: addis r4, r2, .LCPI8_0@toc@ha
1009 ; P8LE-NEXT: addi r3, r4, .LCPI8_0@toc@l
1010 ; P8LE-NEXT: lvx v2, 0, r3
1011 ; P8LE-NEXT: xxswapd v3, vs0
1012 ; P8LE-NEXT: vperm v2, v3, v3, v2
1013 ; P8LE-NEXT: blr
1014 entry:
1015 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 3
1016 %0 = load i32, i32* %arrayidx, align 4
1017 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
1018 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2
1019 %1 = load i32, i32* %arrayidx1, align 4
1020 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
1021 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 1
1022 %2 = load i32, i32* %arrayidx3, align 4
1023 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2
1024 %3 = load i32, i32* %arr, align 4
1025 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3
1026 ret <4 x i32> %vecinit6
1027 }
1029 ; Function Attrs: norecurse nounwind readonly
1030 define <4 x i32> @fromDiffMemVarAi(i32* nocapture readonly %arr, i32 signext %elem) {
1031 ; P9BE-LABEL: fromDiffMemVarAi:
1032 ; P9BE: # %bb.0: # %entry
1033 ; P9BE-NEXT: sldi r4, r4, 2
1034 ; P9BE-NEXT: lxvx v2, r3, r4
1035 ; P9BE-NEXT: blr
1036 ;
1037 ; P9LE-LABEL: fromDiffMemVarAi:
1038 ; P9LE: # %bb.0: # %entry
1039 ; P9LE-NEXT: sldi r4, r4, 2
1040 ; P9LE-NEXT: lxvx v2, r3, r4
1041 ; P9LE-NEXT: blr
1042 ;
1043 ; P8BE-LABEL: fromDiffMemVarAi:
1044 ; P8BE: # %bb.0: # %entry
1045 ; P8BE-NEXT: sldi r4, r4, 2
1046 ; P8BE-NEXT: lxvw4x v2, r3, r4
1047 ; P8BE-NEXT: blr
1048 ;
1049 ; P8LE-LABEL: fromDiffMemVarAi:
1050 ; P8LE: # %bb.0: # %entry
1051 ; P8LE-NEXT: sldi r4, r4, 2
1052 ; P8LE-NEXT: lxvd2x vs0, r3, r4
1053 ; P8LE-NEXT: xxswapd v2, vs0
1054 ; P8LE-NEXT: blr
1055 entry:
1056 %idxprom = sext i32 %elem to i64
1057 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom
1058 %0 = load i32, i32* %arrayidx, align 4
1059 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
1060 %add = add nsw i32 %elem, 1
1061 %idxprom1 = sext i32 %add to i64
1062 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1
1063 %1 = load i32, i32* %arrayidx2, align 4
1064 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
1065 %add4 = add nsw i32 %elem, 2
1066 %idxprom5 = sext i32 %add4 to i64
1067 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5
1068 %2 = load i32, i32* %arrayidx6, align 4
1069 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2
1070 %add8 = add nsw i32 %elem, 3
1071 %idxprom9 = sext i32 %add8 to i64
1072 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9
1073 %3 = load i32, i32* %arrayidx10, align 4
1074 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3
1075 ret <4 x i32> %vecinit11
1076 }
1078 ; Function Attrs: norecurse nounwind readonly
1079 define <4 x i32> @fromDiffMemVarDi(i32* nocapture readonly %arr, i32 signext %elem) {
1080 ; P9BE-LABEL: fromDiffMemVarDi:
1081 ; P9BE: # %bb.0: # %entry
1082 ; P9BE-NEXT: sldi r4, r4, 2
1083 ; P9BE-NEXT: add r3, r3, r4
1084 ; P9BE-NEXT: addi r3, r3, -12
1085 ; P9BE-NEXT: lxvx v2, 0, r3
1086 ; P9BE-NEXT: addis r3, r2, .LCPI10_0@toc@ha
1087 ; P9BE-NEXT: addi r3, r3, .LCPI10_0@toc@l
1088 ; P9BE-NEXT: lxvx v3, 0, r3
1089 ; P9BE-NEXT: vperm v2, v2, v2, v3
1090 ; P9BE-NEXT: blr
1091 ;
1092 ; P9LE-LABEL: fromDiffMemVarDi:
1093 ; P9LE: # %bb.0: # %entry
1094 ; P9LE-NEXT: sldi r4, r4, 2
1095 ; P9LE-NEXT: add r3, r3, r4
1096 ; P9LE-NEXT: addi r3, r3, -12
1097 ; P9LE-NEXT: lxvx v2, 0, r3
1098 ; P9LE-NEXT: addis r3, r2, .LCPI10_0@toc@ha
1099 ; P9LE-NEXT: addi r3, r3, .LCPI10_0@toc@l
1100 ; P9LE-NEXT: lxvx v3, 0, r3
1101 ; P9LE-NEXT: vperm v2, v2, v2, v3
1102 ; P9LE-NEXT: blr
1103 ;
1104 ; P8BE-LABEL: fromDiffMemVarDi:
1105 ; P8BE: # %bb.0: # %entry
1106 ; P8BE-NEXT: sldi r4, r4, 2
1107 ; P8BE-NEXT: addis r5, r2, .LCPI10_0@toc@ha
1108 ; P8BE-NEXT: add r3, r3, r4
1109 ; P8BE-NEXT: addi r4, r5, .LCPI10_0@toc@l
1110 ; P8BE-NEXT: addi r3, r3, -12
1111 ; P8BE-NEXT: lxvw4x v3, 0, r4
1112 ; P8BE-NEXT: lxvw4x v2, 0, r3
1113 ; P8BE-NEXT: vperm v2, v2, v2, v3
1114 ; P8BE-NEXT: blr
1115 ;
1116 ; P8LE-LABEL: fromDiffMemVarDi:
1117 ; P8LE: # %bb.0: # %entry
1118 ; P8LE-NEXT: sldi r4, r4, 2
1119 ; P8LE-NEXT: addis r5, r2, .LCPI10_0@toc@ha
1120 ; P8LE-NEXT: add r3, r3, r4
1121 ; P8LE-NEXT: addi r3, r3, -12
1122 ; P8LE-NEXT: lxvd2x vs0, 0, r3
1123 ; P8LE-NEXT: addi r3, r5, .LCPI10_0@toc@l
1124 ; P8LE-NEXT: lvx v3, 0, r3
1125 ; P8LE-NEXT: xxswapd v2, vs0
1126 ; P8LE-NEXT: vperm v2, v2, v2, v3
1127 ; P8LE-NEXT: blr
1128 entry:
1129 %idxprom = sext i32 %elem to i64
1130 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom
1131 %0 = load i32, i32* %arrayidx, align 4
1132 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
1133 %sub = add nsw i32 %elem, -1
1134 %idxprom1 = sext i32 %sub to i64
1135 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1
1136 %1 = load i32, i32* %arrayidx2, align 4
1137 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
1138 %sub4 = add nsw i32 %elem, -2
1139 %idxprom5 = sext i32 %sub4 to i64
1140 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5
1141 %2 = load i32, i32* %arrayidx6, align 4
1142 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2
1143 %sub8 = add nsw i32 %elem, -3
1144 %idxprom9 = sext i32 %sub8 to i64
1145 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9
1146 %3 = load i32, i32* %arrayidx10, align 4
1147 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3
1148 ret <4 x i32> %vecinit11
1149 }
1151 ; Function Attrs: norecurse nounwind readonly
1152 define <4 x i32> @fromRandMemConsi(i32* nocapture readonly %arr) {
1153 ; P9BE-LABEL: fromRandMemConsi:
1154 ; P9BE: # %bb.0: # %entry
1155 ; P9BE-NEXT: lwz r4, 16(r3)
1156 ; P9BE-NEXT: lwz r5, 72(r3)
1157 ; P9BE-NEXT: lwz r6, 8(r3)
1158 ; P9BE-NEXT: lwz r3, 352(r3)
1159 ; P9BE-NEXT: rldimi r3, r6, 32, 0
1160 ; P9BE-NEXT: rldimi r5, r4, 32, 0
1161 ; P9BE-NEXT: mtvsrdd v2, r5, r3
1162 ; P9BE-NEXT: blr
1163 ;
1164 ; P9LE-LABEL: fromRandMemConsi:
1165 ; P9LE: # %bb.0: # %entry
1166 ; P9LE-NEXT: lwz r4, 16(r3)
1167 ; P9LE-NEXT: lwz r5, 72(r3)
1168 ; P9LE-NEXT: lwz r6, 8(r3)
1169 ; P9LE-NEXT: lwz r3, 352(r3)
1170 ; P9LE-NEXT: rldimi r4, r5, 32, 0
1171 ; P9LE-NEXT: rldimi r6, r3, 32, 0
1172 ; P9LE-NEXT: mtvsrdd v2, r6, r4
1173 ; P9LE-NEXT: blr
1174 ;
1175 ; P8BE-LABEL: fromRandMemConsi:
1176 ; P8BE: # %bb.0: # %entry
1177 ; P8BE-NEXT: lwz r4, 8(r3)
1178 ; P8BE-NEXT: lwz r5, 352(r3)
1179 ; P8BE-NEXT: lwz r6, 16(r3)
1180 ; P8BE-NEXT: lwz r3, 72(r3)
1181 ; P8BE-NEXT: rldimi r5, r4, 32, 0
1182 ; P8BE-NEXT: rldimi r3, r6, 32, 0
1183 ; P8BE-NEXT: mtvsrd f0, r5
1184 ; P8BE-NEXT: mtvsrd f1, r3
1185 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
1186 ; P8BE-NEXT: blr
1187 ;
1188 ; P8LE-LABEL: fromRandMemConsi:
1189 ; P8LE: # %bb.0: # %entry
1190 ; P8LE-NEXT: lwz r4, 16(r3)
1191 ; P8LE-NEXT: lwz r5, 72(r3)
1192 ; P8LE-NEXT: lwz r6, 8(r3)
1193 ; P8LE-NEXT: lwz r3, 352(r3)
1194 ; P8LE-NEXT: rldimi r4, r5, 32, 0
1195 ; P8LE-NEXT: rldimi r6, r3, 32, 0
1196 ; P8LE-NEXT: mtvsrd f0, r4
1197 ; P8LE-NEXT: mtvsrd f1, r6
1198 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
1199 ; P8LE-NEXT: blr
1200 entry:
1201 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 4
1202 %0 = load i32, i32* %arrayidx, align 4
1203 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
1204 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 18
1205 %1 = load i32, i32* %arrayidx1, align 4
1206 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
1207 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2
1208 %2 = load i32, i32* %arrayidx3, align 4
1209 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2
1210 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 88
1211 %3 = load i32, i32* %arrayidx5, align 4
1212 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3
1213 ret <4 x i32> %vecinit6
1214 }
1216 ; Function Attrs: norecurse nounwind readonly
1217 define <4 x i32> @fromRandMemVari(i32* nocapture readonly %arr, i32 signext %elem) {
1218 ; P9BE-LABEL: fromRandMemVari:
1219 ; P9BE: # %bb.0: # %entry
1220 ; P9BE-NEXT: sldi r4, r4, 2
1221 ; P9BE-NEXT: add r3, r3, r4
1222 ; P9BE-NEXT: lwz r4, 16(r3)
1223 ; P9BE-NEXT: lwz r5, 4(r3)
1224 ; P9BE-NEXT: lwz r6, 8(r3)
1225 ; P9BE-NEXT: lwz r3, 32(r3)
1226 ; P9BE-NEXT: rldimi r3, r6, 32, 0
1227 ; P9BE-NEXT: rldimi r5, r4, 32, 0
1228 ; P9BE-NEXT: mtvsrdd v2, r5, r3
1229 ; P9BE-NEXT: blr
1230 ;
1231 ; P9LE-LABEL: fromRandMemVari:
1232 ; P9LE: # %bb.0: # %entry
1233 ; P9LE-NEXT: sldi r4, r4, 2
1234 ; P9LE-NEXT: add r3, r3, r4
1235 ; P9LE-NEXT: lwz r4, 16(r3)
1236 ; P9LE-NEXT: lwz r5, 4(r3)
1237 ; P9LE-NEXT: lwz r6, 8(r3)
1238 ; P9LE-NEXT: lwz r3, 32(r3)
1239 ; P9LE-NEXT: rldimi r4, r5, 32, 0
1240 ; P9LE-NEXT: rldimi r6, r3, 32, 0
1241 ; P9LE-NEXT: mtvsrdd v2, r6, r4
1242 ; P9LE-NEXT: blr
1243 ;
1244 ; P8BE-LABEL: fromRandMemVari:
1245 ; P8BE: # %bb.0: # %entry
1246 ; P8BE-NEXT: sldi r4, r4, 2
1247 ; P8BE-NEXT: add r3, r3, r4
1248 ; P8BE-NEXT: lwz r4, 8(r3)
1249 ; P8BE-NEXT: lwz r5, 32(r3)
1250 ; P8BE-NEXT: lwz r6, 16(r3)
1251 ; P8BE-NEXT: lwz r3, 4(r3)
1252 ; P8BE-NEXT: rldimi r5, r4, 32, 0
1253 ; P8BE-NEXT: rldimi r3, r6, 32, 0
1254 ; P8BE-NEXT: mtvsrd f0, r5
1255 ; P8BE-NEXT: mtvsrd f1, r3
1256 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
1257 ; P8BE-NEXT: blr
1258 ;
1259 ; P8LE-LABEL: fromRandMemVari:
1260 ; P8LE: # %bb.0: # %entry
1261 ; P8LE-NEXT: sldi r4, r4, 2
1262 ; P8LE-NEXT: add r3, r3, r4
1263 ; P8LE-NEXT: lwz r4, 16(r3)
1264 ; P8LE-NEXT: lwz r5, 4(r3)
1265 ; P8LE-NEXT: lwz r6, 8(r3)
1266 ; P8LE-NEXT: lwz r3, 32(r3)
1267 ; P8LE-NEXT: rldimi r4, r5, 32, 0
1268 ; P8LE-NEXT: rldimi r6, r3, 32, 0
1269 ; P8LE-NEXT: mtvsrd f0, r4
1270 ; P8LE-NEXT: mtvsrd f1, r6
1271 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
1272 ; P8LE-NEXT: blr
1273 entry:
1274 %add = add nsw i32 %elem, 4
1275 %idxprom = sext i32 %add to i64
1276 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom
1277 %0 = load i32, i32* %arrayidx, align 4
1278 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
1279 %add1 = add nsw i32 %elem, 1
1280 %idxprom2 = sext i32 %add1 to i64
1281 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 %idxprom2
1282 %1 = load i32, i32* %arrayidx3, align 4
1283 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
1284 %add5 = add nsw i32 %elem, 2
1285 %idxprom6 = sext i32 %add5 to i64
1286 %arrayidx7 = getelementptr inbounds i32, i32* %arr, i64 %idxprom6
1287 %2 = load i32, i32* %arrayidx7, align 4
1288 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2
1289 %add9 = add nsw i32 %elem, 8
1290 %idxprom10 = sext i32 %add9 to i64
1291 %arrayidx11 = getelementptr inbounds i32, i32* %arr, i64 %idxprom10
1292 %3 = load i32, i32* %arrayidx11, align 4
1293 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3
1294 ret <4 x i32> %vecinit12
1295 }
1297 ; Function Attrs: norecurse nounwind readnone
1298 define <4 x i32> @spltRegVali(i32 signext %val) {
1299 ; P9BE-LABEL: spltRegVali:
1300 ; P9BE: # %bb.0: # %entry
1301 ; P9BE-NEXT: mtvsrws v2, r3
1302 ; P9BE-NEXT: blr
1303 ;
1304 ; P9LE-LABEL: spltRegVali:
1305 ; P9LE: # %bb.0: # %entry
1306 ; P9LE-NEXT: mtvsrws v2, r3
1307 ; P9LE-NEXT: blr
1308 ;
1309 ; P8BE-LABEL: spltRegVali:
1310 ; P8BE: # %bb.0: # %entry
1311 ; P8BE-NEXT: mtvsrwz f0, r3
1312 ; P8BE-NEXT: xxspltw v2, vs0, 1
1313 ; P8BE-NEXT: blr
1314 ;
1315 ; P8LE-LABEL: spltRegVali:
1316 ; P8LE: # %bb.0: # %entry
1317 ; P8LE-NEXT: mtvsrwz f0, r3
1318 ; P8LE-NEXT: xxspltw v2, vs0, 1
1319 ; P8LE-NEXT: blr
1320 entry:
1321 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0
1322 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
1323 ret <4 x i32> %splat.splat
1324 }
1326 ; Function Attrs: norecurse nounwind readonly
1327 define <4 x i32> @spltMemVali(i32* nocapture readonly %ptr) {
1328 ; P9BE-LABEL: spltMemVali:
1329 ; P9BE: # %bb.0: # %entry
1330 ; P9BE-NEXT: lfiwzx f0, 0, r3
1331 ; P9BE-NEXT: xxsldwi vs0, f0, f0, 1
1332 ; P9BE-NEXT: xxspltw v2, vs0, 0
1333 ; P9BE-NEXT: blr
1334 ;
1335 ; P9LE-LABEL: spltMemVali:
1336 ; P9LE: # %bb.0: # %entry
1337 ; P9LE-NEXT: lfiwzx f0, 0, r3
1338 ; P9LE-NEXT: xxpermdi vs0, f0, f0, 2
1339 ; P9LE-NEXT: xxspltw v2, vs0, 3
1340 ; P9LE-NEXT: blr
1341 ;
1342 ; P8BE-LABEL: spltMemVali:
1343 ; P8BE: # %bb.0: # %entry
1344 ; P8BE-NEXT: lfiwzx f0, 0, r3
1345 ; P8BE-NEXT: xxsldwi vs0, f0, f0, 1
1346 ; P8BE-NEXT: xxspltw v2, vs0, 0
1347 ; P8BE-NEXT: blr
1348 ;
1349 ; P8LE-LABEL: spltMemVali:
1350 ; P8LE: # %bb.0: # %entry
1351 ; P8LE-NEXT: lfiwzx f0, 0, r3
1352 ; P8LE-NEXT: xxpermdi vs0, f0, f0, 2
1353 ; P8LE-NEXT: xxspltw v2, vs0, 3
1354 ; P8LE-NEXT: blr
1355 entry:
1356 %0 = load i32, i32* %ptr, align 4
1357 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0
1358 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
1359 ret <4 x i32> %splat.splat
1360 }
1362 ; Function Attrs: norecurse nounwind readnone
1363 define <4 x i32> @spltCnstConvftoi() {
1364 ; P9BE-LABEL: spltCnstConvftoi:
1365 ; P9BE: # %bb.0: # %entry
1366 ; P9BE-NEXT: vspltisw v2, 4
1367 ; P9BE-NEXT: blr
1368 ;
1369 ; P9LE-LABEL: spltCnstConvftoi:
1370 ; P9LE: # %bb.0: # %entry
1371 ; P9LE-NEXT: vspltisw v2, 4
1372 ; P9LE-NEXT: blr
1373 ;
1374 ; P8BE-LABEL: spltCnstConvftoi:
1375 ; P8BE: # %bb.0: # %entry
1376 ; P8BE-NEXT: vspltisw v2, 4
1377 ; P8BE-NEXT: blr
1378 ;
1379 ; P8LE-LABEL: spltCnstConvftoi:
1380 ; P8LE: # %bb.0: # %entry
1381 ; P8LE-NEXT: vspltisw v2, 4
1382 ; P8LE-NEXT: blr
1383 entry:
1384 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4>
1385 }
1387 ; Function Attrs: norecurse nounwind readnone
1388 define <4 x i32> @fromRegsConvftoi(float %a, float %b, float %c, float %d) {
1389 ; P9BE-LABEL: fromRegsConvftoi:
1390 ; P9BE: # %bb.0: # %entry
1391 ; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4
1392 ; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
1393 ; P9BE-NEXT: xxmrghd vs0, vs2, vs4
1394 ; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3
1395 ; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
1396 ; P9BE-NEXT: xvcvdpsxws v2, vs0
1397 ; P9BE-NEXT: xxmrghd vs0, vs1, vs3
1398 ; P9BE-NEXT: xvcvdpsxws v3, vs0
1399 ; P9BE-NEXT: vmrgew v2, v3, v2
1400 ; P9BE-NEXT: blr
1401 ;
1402 ; P9LE-LABEL: fromRegsConvftoi:
1403 ; P9LE: # %bb.0: # %entry
1404 ; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3
1405 ; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
1406 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
1407 ; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4
1408 ; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
1409 ; P9LE-NEXT: xvcvdpsxws v2, vs0
1410 ; P9LE-NEXT: xxmrghd vs0, vs4, vs2
1411 ; P9LE-NEXT: xvcvdpsxws v3, vs0
1412 ; P9LE-NEXT: vmrgew v2, v3, v2
1413 ; P9LE-NEXT: blr
1414 ;
1415 ; P8BE-LABEL: fromRegsConvftoi:
1416 ; P8BE: # %bb.0: # %entry
1417 ; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
1418 ; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4
1419 ; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3
1420 ; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
1421 ; P8BE-NEXT: xxmrghd vs0, vs2, vs4
1422 ; P8BE-NEXT: xxmrghd vs1, vs1, vs3
1423 ; P8BE-NEXT: xvcvdpsxws v2, vs0
1424 ; P8BE-NEXT: xvcvdpsxws v3, vs1
1425 ; P8BE-NEXT: vmrgew v2, v3, v2
1426 ; P8BE-NEXT: blr
1427 ;
1428 ; P8LE-LABEL: fromRegsConvftoi:
1429 ; P8LE: # %bb.0: # %entry
1430 ; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
1431 ; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4
1432 ; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3
1433 ; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
1434 ; P8LE-NEXT: xxmrghd vs0, vs3, vs1
1435 ; P8LE-NEXT: xxmrghd vs1, vs4, vs2
1436 ; P8LE-NEXT: xvcvdpsxws v2, vs0
1437 ; P8LE-NEXT: xvcvdpsxws v3, vs1
1438 ; P8LE-NEXT: vmrgew v2, v3, v2
1439 ; P8LE-NEXT: blr
1440 entry:
1441 %conv = fptosi float %a to i32
1442 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
1443 %conv1 = fptosi float %b to i32
1444 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1
1445 %conv3 = fptosi float %c to i32
1446 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2
1447 %conv5 = fptosi float %d to i32
1448 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3
1449 ret <4 x i32> %vecinit6
1450 }
1452 ; Function Attrs: norecurse nounwind readnone
1453 define <4 x i32> @fromDiffConstsConvftoi() {
1454 ; P9BE-LABEL: fromDiffConstsConvftoi:
1455 ; P9BE: # %bb.0: # %entry
1456 ; P9BE-NEXT: addis r3, r2, .LCPI17_0@toc@ha
1457 ; P9BE-NEXT: addi r3, r3, .LCPI17_0@toc@l
1458 ; P9BE-NEXT: lxvx v2, 0, r3
1459 ; P9BE-NEXT: blr
1460 ;
1461 ; P9LE-LABEL: fromDiffConstsConvftoi:
1462 ; P9LE: # %bb.0: # %entry
1463 ; P9LE-NEXT: addis r3, r2, .LCPI17_0@toc@ha
1464 ; P9LE-NEXT: addi r3, r3, .LCPI17_0@toc@l
1465 ; P9LE-NEXT: lxvx v2, 0, r3
1466 ; P9LE-NEXT: blr
1467 ;
1468 ; P8BE-LABEL: fromDiffConstsConvftoi:
1469 ; P8BE: # %bb.0: # %entry
1470 ; P8BE-NEXT: addis r3, r2, .LCPI17_0@toc@ha
1471 ; P8BE-NEXT: addi r3, r3, .LCPI17_0@toc@l
1472 ; P8BE-NEXT: lxvw4x v2, 0, r3
1473 ; P8BE-NEXT: blr
1474 ;
1475 ; P8LE-LABEL: fromDiffConstsConvftoi:
1476 ; P8LE: # %bb.0: # %entry
1477 ; P8LE-NEXT: addis r3, r2, .LCPI17_0@toc@ha
1478 ; P8LE-NEXT: addi r3, r3, .LCPI17_0@toc@l
1479 ; P8LE-NEXT: lvx v2, 0, r3
1480 ; P8LE-NEXT: blr
1481 entry:
1482 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422>
1483 }
1485 ; Function Attrs: norecurse nounwind readonly
1486 define <4 x i32> @fromDiffMemConsAConvftoi(float* nocapture readonly %ptr) {
1487 ; P9BE-LABEL: fromDiffMemConsAConvftoi:
1488 ; P9BE: # %bb.0: # %entry
1489 ; P9BE-NEXT: lxv vs0, 0(r3)
1490 ; P9BE-NEXT: xvcvspsxws v2, vs0
1491 ; P9BE-NEXT: blr
1492 ;
1493 ; P9LE-LABEL: fromDiffMemConsAConvftoi:
1494 ; P9LE: # %bb.0: # %entry
1495 ; P9LE-NEXT: lxv vs0, 0(r3)
1496 ; P9LE-NEXT: xvcvspsxws v2, vs0
1497 ; P9LE-NEXT: blr
1498 ;
1499 ; P8BE-LABEL: fromDiffMemConsAConvftoi:
1500 ; P8BE: # %bb.0: # %entry
1501 ; P8BE-NEXT: lxvw4x vs0, 0, r3
1502 ; P8BE-NEXT: xvcvspsxws v2, vs0
1503 ; P8BE-NEXT: blr
1504 ;
1505 ; P8LE-LABEL: fromDiffMemConsAConvftoi:
1506 ; P8LE: # %bb.0: # %entry
1507 ; P8LE-NEXT: lxvd2x vs0, 0, r3
1508 ; P8LE-NEXT: xxswapd v2, vs0
1509 ; P8LE-NEXT: xvcvspsxws v2, v2
1510 ; P8LE-NEXT: blr
1511 entry:
1512 %0 = bitcast float* %ptr to <4 x float>*
1513 %1 = load <4 x float>, <4 x float>* %0, align 4
1514 %2 = fptosi <4 x float> %1 to <4 x i32>
1515 ret <4 x i32> %2
1516 }
1518 ; Function Attrs: norecurse nounwind readonly
1519 define <4 x i32> @fromDiffMemConsDConvftoi(float* nocapture readonly %ptr) {
1520 ; P9BE-LABEL: fromDiffMemConsDConvftoi:
1521 ; P9BE: # %bb.0: # %entry
1522 ; P9BE-NEXT: lxv v2, 0(r3)
1523 ; P9BE-NEXT: addis r3, r2, .LCPI19_0@toc@ha
1524 ; P9BE-NEXT: addi r3, r3, .LCPI19_0@toc@l
1525 ; P9BE-NEXT: lxvx v3, 0, r3
1526 ; P9BE-NEXT: vperm v2, v2, v2, v3
1527 ; P9BE-NEXT: xvcvspsxws v2, v2
1528 ; P9BE-NEXT: blr
1529 ;
1530 ; P9LE-LABEL: fromDiffMemConsDConvftoi:
1531 ; P9LE: # %bb.0: # %entry
1532 ; P9LE-NEXT: lxv v2, 0(r3)
1533 ; P9LE-NEXT: addis r3, r2, .LCPI19_0@toc@ha
1534 ; P9LE-NEXT: addi r3, r3, .LCPI19_0@toc@l
1535 ; P9LE-NEXT: lxvx v3, 0, r3
1536 ; P9LE-NEXT: vperm v2, v2, v2, v3
1537 ; P9LE-NEXT: xvcvspsxws v2, v2
1538 ; P9LE-NEXT: blr
1539 ;
1540 ; P8BE-LABEL: fromDiffMemConsDConvftoi:
1541 ; P8BE: # %bb.0: # %entry
1542 ; P8BE-NEXT: addis r4, r2, .LCPI19_0@toc@ha
1543 ; P8BE-NEXT: lxvw4x v2, 0, r3
1544 ; P8BE-NEXT: addi r4, r4, .LCPI19_0@toc@l
1545 ; P8BE-NEXT: lxvw4x v3, 0, r4
1546 ; P8BE-NEXT: vperm v2, v2, v2, v3
1547 ; P8BE-NEXT: xvcvspsxws v2, v2
1548 ; P8BE-NEXT: blr
1549 ;
1550 ; P8LE-LABEL: fromDiffMemConsDConvftoi:
1551 ; P8LE: # %bb.0: # %entry
1552 ; P8LE-NEXT: lxvd2x vs0, 0, r3
1553 ; P8LE-NEXT: addis r4, r2, .LCPI19_0@toc@ha
1554 ; P8LE-NEXT: addi r3, r4, .LCPI19_0@toc@l
1555 ; P8LE-NEXT: lvx v2, 0, r3
1556 ; P8LE-NEXT: xxswapd v3, vs0
1557 ; P8LE-NEXT: vperm v2, v3, v3, v2
1558 ; P8LE-NEXT: xvcvspsxws v2, v2
1559 ; P8LE-NEXT: blr
1560 entry:
1561 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3
1562 %0 = load float, float* %arrayidx, align 4
1563 %conv = fptosi float %0 to i32
1564 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
1565 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2
1566 %1 = load float, float* %arrayidx1, align 4
1567 %conv2 = fptosi float %1 to i32
1568 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
1569 %arrayidx4 = getelementptr inbounds float, float* %ptr, i64 1
1570 %2 = load float, float* %arrayidx4, align 4
1571 %conv5 = fptosi float %2 to i32
1572 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
1573 %3 = load float, float* %ptr, align 4
1574 %conv8 = fptosi float %3 to i32
1575 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
1576 ret <4 x i32> %vecinit9
1577 }
1579 ; Function Attrs: norecurse nounwind readonly
1580 define <4 x i32> @fromDiffMemVarAConvftoi(float* nocapture readonly %arr, i32 signext %elem) {
1581 ; P9BE-LABEL: fromDiffMemVarAConvftoi:
1582 ; P9BE: # %bb.0: # %entry
1583 ; P9BE-NEXT: sldi r4, r4, 2
1584 ; P9BE-NEXT: lfsux f0, r3, r4
1585 ; P9BE-NEXT: lfs f1, 12(r3)
1586 ; P9BE-NEXT: lfs f2, 4(r3)
1587 ; P9BE-NEXT: xxmrghd vs1, vs2, vs1
1588 ; P9BE-NEXT: xvcvdpsp v2, vs1
1589 ; P9BE-NEXT: lfs f1, 8(r3)
1590 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
1591 ; P9BE-NEXT: xvcvdpsp v3, vs0
1592 ; P9BE-NEXT: vmrgew v2, v3, v2
1593 ; P9BE-NEXT: xvcvspsxws v2, v2
1594 ; P9BE-NEXT: blr
1595 ;
1596 ; P9LE-LABEL: fromDiffMemVarAConvftoi:
1597 ; P9LE: # %bb.0: # %entry
1598 ; P9LE-NEXT: sldi r4, r4, 2
1599 ; P9LE-NEXT: lfsux f0, r3, r4
1600 ; P9LE-NEXT: lfs f1, 8(r3)
1601 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
1602 ; P9LE-NEXT: lfs f1, 12(r3)
1603 ; P9LE-NEXT: xvcvdpsp v2, vs0
1604 ; P9LE-NEXT: lfs f0, 4(r3)
1605 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
1606 ; P9LE-NEXT: xvcvdpsp v3, vs0
1607 ; P9LE-NEXT: vmrgew v2, v3, v2
1608 ; P9LE-NEXT: xvcvspsxws v2, v2
1609 ; P9LE-NEXT: blr
1610 ;
1611 ; P8BE-LABEL: fromDiffMemVarAConvftoi:
1612 ; P8BE: # %bb.0: # %entry
1613 ; P8BE-NEXT: sldi r4, r4, 2
1614 ; P8BE-NEXT: lfsux f0, r3, r4
1615 ; P8BE-NEXT: lfs f1, 12(r3)
1616 ; P8BE-NEXT: lfs f2, 4(r3)
1617 ; P8BE-NEXT: lfs f3, 8(r3)
1618 ; P8BE-NEXT: xxmrghd vs1, vs2, vs1
1619 ; P8BE-NEXT: xxmrghd vs0, vs0, vs3
1620 ; P8BE-NEXT: xvcvdpsp v2, vs1
1621 ; P8BE-NEXT: xvcvdpsp v3, vs0
1622 ; P8BE-NEXT: vmrgew v2, v3, v2
1623 ; P8BE-NEXT: xvcvspsxws v2, v2
1624 ; P8BE-NEXT: blr
1625 ;
1626 ; P8LE-LABEL: fromDiffMemVarAConvftoi:
1627 ; P8LE: # %bb.0: # %entry
1628 ; P8LE-NEXT: sldi r4, r4, 2
1629 ; P8LE-NEXT: lfsux f0, r3, r4
1630 ; P8LE-NEXT: lfs f1, 8(r3)
1631 ; P8LE-NEXT: lfs f2, 4(r3)
1632 ; P8LE-NEXT: lfs f3, 12(r3)
1633 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
1634 ; P8LE-NEXT: xxmrghd vs1, vs3, vs2
1635 ; P8LE-NEXT: xvcvdpsp v2, vs0
1636 ; P8LE-NEXT: xvcvdpsp v3, vs1
1637 ; P8LE-NEXT: vmrgew v2, v3, v2
1638 ; P8LE-NEXT: xvcvspsxws v2, v2
1639 ; P8LE-NEXT: blr
1640 entry:
1641 %idxprom = sext i32 %elem to i64
1642 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom
1643 %0 = load float, float* %arrayidx, align 4
1644 %conv = fptosi float %0 to i32
1645 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
1646 %add = add nsw i32 %elem, 1
1647 %idxprom1 = sext i32 %add to i64
1648 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1
1649 %1 = load float, float* %arrayidx2, align 4
1650 %conv3 = fptosi float %1 to i32
1651 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
1652 %add5 = add nsw i32 %elem, 2
1653 %idxprom6 = sext i32 %add5 to i64
1654 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6
1655 %2 = load float, float* %arrayidx7, align 4
1656 %conv8 = fptosi float %2 to i32
1657 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
1658 %add10 = add nsw i32 %elem, 3
1659 %idxprom11 = sext i32 %add10 to i64
1660 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11
1661 %3 = load float, float* %arrayidx12, align 4
1662 %conv13 = fptosi float %3 to i32
1663 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
1664 ret <4 x i32> %vecinit14
1665 ; FIXME: implement finding consecutive loads with pre-inc
1666 }
1668 ; Function Attrs: norecurse nounwind readonly
1669 define <4 x i32> @fromDiffMemVarDConvftoi(float* nocapture readonly %arr, i32 signext %elem) {
1670 ; P9BE-LABEL: fromDiffMemVarDConvftoi:
1671 ; P9BE: # %bb.0: # %entry
1672 ; P9BE-NEXT: sldi r4, r4, 2
1673 ; P9BE-NEXT: lfsux f0, r3, r4
1674 ; P9BE-NEXT: lfs f1, -12(r3)
1675 ; P9BE-NEXT: lfs f2, -4(r3)
1676 ; P9BE-NEXT: xxmrghd vs1, vs2, vs1
1677 ; P9BE-NEXT: xvcvdpsp v2, vs1
1678 ; P9BE-NEXT: lfs f1, -8(r3)
1679 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
1680 ; P9BE-NEXT: xvcvdpsp v3, vs0
1681 ; P9BE-NEXT: vmrgew v2, v3, v2
1682 ; P9BE-NEXT: xvcvspsxws v2, v2
1683 ; P9BE-NEXT: blr
1684 ;
1685 ; P9LE-LABEL: fromDiffMemVarDConvftoi:
1686 ; P9LE: # %bb.0: # %entry
1687 ; P9LE-NEXT: sldi r4, r4, 2
1688 ; P9LE-NEXT: lfsux f0, r3, r4
1689 ; P9LE-NEXT: lfs f1, -8(r3)
1690 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
1691 ; P9LE-NEXT: lfs f1, -12(r3)
1692 ; P9LE-NEXT: xvcvdpsp v2, vs0
1693 ; P9LE-NEXT: lfs f0, -4(r3)
1694 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
1695 ; P9LE-NEXT: xvcvdpsp v3, vs0
1696 ; P9LE-NEXT: vmrgew v2, v3, v2
1697 ; P9LE-NEXT: xvcvspsxws v2, v2
1698 ; P9LE-NEXT: blr
1699 ;
1700 ; P8BE-LABEL: fromDiffMemVarDConvftoi:
1701 ; P8BE: # %bb.0: # %entry
1702 ; P8BE-NEXT: sldi r4, r4, 2
1703 ; P8BE-NEXT: lfsux f0, r3, r4
1704 ; P8BE-NEXT: lfs f1, -12(r3)
1705 ; P8BE-NEXT: lfs f2, -4(r3)
1706 ; P8BE-NEXT: lfs f3, -8(r3)
1707 ; P8BE-NEXT: xxmrghd vs1, vs2, vs1
1708 ; P8BE-NEXT: xxmrghd vs0, vs0, vs3
1709 ; P8BE-NEXT: xvcvdpsp v2, vs1
1710 ; P8BE-NEXT: xvcvdpsp v3, vs0
1711 ; P8BE-NEXT: vmrgew v2, v3, v2
1712 ; P8BE-NEXT: xvcvspsxws v2, v2
1713 ; P8BE-NEXT: blr
1714 ;
1715 ; P8LE-LABEL: fromDiffMemVarDConvftoi:
1716 ; P8LE: # %bb.0: # %entry
1717 ; P8LE-NEXT: sldi r4, r4, 2
1718 ; P8LE-NEXT: lfsux f0, r3, r4
1719 ; P8LE-NEXT: lfs f1, -8(r3)
1720 ; P8LE-NEXT: lfs f2, -4(r3)
1721 ; P8LE-NEXT: lfs f3, -12(r3)
1722 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
1723 ; P8LE-NEXT: xxmrghd vs1, vs3, vs2
1724 ; P8LE-NEXT: xvcvdpsp v2, vs0
1725 ; P8LE-NEXT: xvcvdpsp v3, vs1
1726 ; P8LE-NEXT: vmrgew v2, v3, v2
1727 ; P8LE-NEXT: xvcvspsxws v2, v2
1728 ; P8LE-NEXT: blr
1729 entry:
1730 %idxprom = sext i32 %elem to i64
1731 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom
1732 %0 = load float, float* %arrayidx, align 4
1733 %conv = fptosi float %0 to i32
1734 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
1735 %sub = add nsw i32 %elem, -1
1736 %idxprom1 = sext i32 %sub to i64
1737 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1
1738 %1 = load float, float* %arrayidx2, align 4
1739 %conv3 = fptosi float %1 to i32
1740 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
1741 %sub5 = add nsw i32 %elem, -2
1742 %idxprom6 = sext i32 %sub5 to i64
1743 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6
1744 %2 = load float, float* %arrayidx7, align 4
1745 %conv8 = fptosi float %2 to i32
1746 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
1747 %sub10 = add nsw i32 %elem, -3
1748 %idxprom11 = sext i32 %sub10 to i64
1749 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11
1750 %3 = load float, float* %arrayidx12, align 4
1751 %conv13 = fptosi float %3 to i32
1752 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
1753 ret <4 x i32> %vecinit14
1754 ; FIXME: implement finding consecutive loads with pre-inc
1755 }
1757 ; Function Attrs: norecurse nounwind readnone
1758 define <4 x i32> @spltRegValConvftoi(float %val) {
1759 ; P9BE-LABEL: spltRegValConvftoi:
1760 ; P9BE: # %bb.0: # %entry
1761 ; P9BE-NEXT: xscvdpsxws f0, f1
1762 ; P9BE-NEXT: xxspltw v2, vs0, 1
1763 ; P9BE-NEXT: blr
1764 ;
1765 ; P9LE-LABEL: spltRegValConvftoi:
1766 ; P9LE: # %bb.0: # %entry
1767 ; P9LE-NEXT: xscvdpsxws f0, f1
1768 ; P9LE-NEXT: xxspltw v2, vs0, 1
1769 ; P9LE-NEXT: blr
1770 ;
1771 ; P8BE-LABEL: spltRegValConvftoi:
1772 ; P8BE: # %bb.0: # %entry
1773 ; P8BE-NEXT: xscvdpsxws f0, f1
1774 ; P8BE-NEXT: xxspltw v2, vs0, 1
1775 ; P8BE-NEXT: blr
1776 ;
1777 ; P8LE-LABEL: spltRegValConvftoi:
1778 ; P8LE: # %bb.0: # %entry
1779 ; P8LE-NEXT: xscvdpsxws f0, f1
1780 ; P8LE-NEXT: xxspltw v2, vs0, 1
1781 ; P8LE-NEXT: blr
1782 entry:
1783 %conv = fptosi float %val to i32
1784 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
1785 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
1786 ret <4 x i32> %splat.splat
1787 }
1789 ; Function Attrs: norecurse nounwind readonly
1790 define <4 x i32> @spltMemValConvftoi(float* nocapture readonly %ptr) {
1791 ; P9BE-LABEL: spltMemValConvftoi:
1792 ; P9BE: # %bb.0: # %entry
1793 ; P9BE-NEXT: lxvwsx vs0, 0, r3
1794 ; P9BE-NEXT: xvcvspsxws v2, vs0
1795 ; P9BE-NEXT: blr
1796 ;
1797 ; P9LE-LABEL: spltMemValConvftoi:
1798 ; P9LE: # %bb.0: # %entry
1799 ; P9LE-NEXT: lxvwsx vs0, 0, r3
1800 ; P9LE-NEXT: xvcvspsxws v2, vs0
1801 ; P9LE-NEXT: blr
1802 ;
1803 ; P8BE-LABEL: spltMemValConvftoi:
1804 ; P8BE: # %bb.0: # %entry
1805 ; P8BE-NEXT: lfsx f0, 0, r3
1806 ; P8BE-NEXT: xscvdpsxws f0, f0
1807 ; P8BE-NEXT: xxspltw v2, vs0, 1
1808 ; P8BE-NEXT: blr
1809 ;
1810 ; P8LE-LABEL: spltMemValConvftoi:
1811 ; P8LE: # %bb.0: # %entry
1812 ; P8LE-NEXT: lfsx f0, 0, r3
1813 ; P8LE-NEXT: xscvdpsxws f0, f0
1814 ; P8LE-NEXT: xxspltw v2, vs0, 1
1815 ; P8LE-NEXT: blr
1816 entry:
1817 %0 = load float, float* %ptr, align 4
1818 %conv = fptosi float %0 to i32
1819 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
1820 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
1821 ret <4 x i32> %splat.splat
1822 }
1824 ; Function Attrs: norecurse nounwind readnone
1825 define <4 x i32> @spltCnstConvdtoi() {
1826 ; P9BE-LABEL: spltCnstConvdtoi:
1827 ; P9BE: # %bb.0: # %entry
1828 ; P9BE-NEXT: vspltisw v2, 4
1829 ; P9BE-NEXT: blr
1830 ;
1831 ; P9LE-LABEL: spltCnstConvdtoi:
1832 ; P9LE: # %bb.0: # %entry
1833 ; P9LE-NEXT: vspltisw v2, 4
1834 ; P9LE-NEXT: blr
1835 ;
1836 ; P8BE-LABEL: spltCnstConvdtoi:
1837 ; P8BE: # %bb.0: # %entry
1838 ; P8BE-NEXT: vspltisw v2, 4
1839 ; P8BE-NEXT: blr
1840 ;
1841 ; P8LE-LABEL: spltCnstConvdtoi:
1842 ; P8LE: # %bb.0: # %entry
1843 ; P8LE-NEXT: vspltisw v2, 4
1844 ; P8LE-NEXT: blr
1845 entry:
1846 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4>
1847 }
1849 ; Function Attrs: norecurse nounwind readnone
1850 define <4 x i32> @fromRegsConvdtoi(double %a, double %b, double %c, double %d) {
1851 ; P9BE-LABEL: fromRegsConvdtoi:
1852 ; P9BE: # %bb.0: # %entry
1853 ; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4
1854 ; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
1855 ; P9BE-NEXT: xxmrghd vs0, vs2, vs4
1856 ; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3
1857 ; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
1858 ; P9BE-NEXT: xvcvdpsxws v2, vs0
1859 ; P9BE-NEXT: xxmrghd vs0, vs1, vs3
1860 ; P9BE-NEXT: xvcvdpsxws v3, vs0
1861 ; P9BE-NEXT: vmrgew v2, v3, v2
1862 ; P9BE-NEXT: blr
1863 ;
1864 ; P9LE-LABEL: fromRegsConvdtoi:
1865 ; P9LE: # %bb.0: # %entry
1866 ; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3
1867 ; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
1868 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
1869 ; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4
1870 ; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
1871 ; P9LE-NEXT: xvcvdpsxws v2, vs0
1872 ; P9LE-NEXT: xxmrghd vs0, vs4, vs2
1873 ; P9LE-NEXT: xvcvdpsxws v3, vs0
1874 ; P9LE-NEXT: vmrgew v2, v3, v2
1875 ; P9LE-NEXT: blr
1876 ;
1877 ; P8BE-LABEL: fromRegsConvdtoi:
1878 ; P8BE: # %bb.0: # %entry
1879 ; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
1880 ; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4
1881 ; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3
1882 ; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
1883 ; P8BE-NEXT: xxmrghd vs0, vs2, vs4
1884 ; P8BE-NEXT: xxmrghd vs1, vs1, vs3
1885 ; P8BE-NEXT: xvcvdpsxws v2, vs0
1886 ; P8BE-NEXT: xvcvdpsxws v3, vs1
1887 ; P8BE-NEXT: vmrgew v2, v3, v2
1888 ; P8BE-NEXT: blr
1889 ;
1890 ; P8LE-LABEL: fromRegsConvdtoi:
1891 ; P8LE: # %bb.0: # %entry
1892 ; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
1893 ; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4
1894 ; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3
1895 ; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
1896 ; P8LE-NEXT: xxmrghd vs0, vs3, vs1
1897 ; P8LE-NEXT: xxmrghd vs1, vs4, vs2
1898 ; P8LE-NEXT: xvcvdpsxws v2, vs0
1899 ; P8LE-NEXT: xvcvdpsxws v3, vs1
1900 ; P8LE-NEXT: vmrgew v2, v3, v2
1901 ; P8LE-NEXT: blr
1902 entry:
1903 %conv = fptosi double %a to i32
1904 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
1905 %conv1 = fptosi double %b to i32
1906 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1
1907 %conv3 = fptosi double %c to i32
1908 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2
1909 %conv5 = fptosi double %d to i32
1910 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3
1911 ret <4 x i32> %vecinit6
1912 }
1914 ; Function Attrs: norecurse nounwind readnone
1915 define <4 x i32> @fromDiffConstsConvdtoi() {
1916 ; P9BE-LABEL: fromDiffConstsConvdtoi:
1917 ; P9BE: # %bb.0: # %entry
1918 ; P9BE-NEXT: addis r3, r2, .LCPI26_0@toc@ha
1919 ; P9BE-NEXT: addi r3, r3, .LCPI26_0@toc@l
1920 ; P9BE-NEXT: lxvx v2, 0, r3
1921 ; P9BE-NEXT: blr
1922 ;
1923 ; P9LE-LABEL: fromDiffConstsConvdtoi:
1924 ; P9LE: # %bb.0: # %entry
1925 ; P9LE-NEXT: addis r3, r2, .LCPI26_0@toc@ha
1926 ; P9LE-NEXT: addi r3, r3, .LCPI26_0@toc@l
1927 ; P9LE-NEXT: lxvx v2, 0, r3
1928 ; P9LE-NEXT: blr
1929 ;
1930 ; P8BE-LABEL: fromDiffConstsConvdtoi:
1931 ; P8BE: # %bb.0: # %entry
1932 ; P8BE-NEXT: addis r3, r2, .LCPI26_0@toc@ha
1933 ; P8BE-NEXT: addi r3, r3, .LCPI26_0@toc@l
1934 ; P8BE-NEXT: lxvw4x v2, 0, r3
1935 ; P8BE-NEXT: blr
1936 ;
1937 ; P8LE-LABEL: fromDiffConstsConvdtoi:
1938 ; P8LE: # %bb.0: # %entry
1939 ; P8LE-NEXT: addis r3, r2, .LCPI26_0@toc@ha
1940 ; P8LE-NEXT: addi r3, r3, .LCPI26_0@toc@l
1941 ; P8LE-NEXT: lvx v2, 0, r3
1942 ; P8LE-NEXT: blr
1943 entry:
1944 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422>
1945 }
1947 ; Function Attrs: norecurse nounwind readonly
1948 define <4 x i32> @fromDiffMemConsAConvdtoi(double* nocapture readonly %ptr) {
1949 ; P9BE-LABEL: fromDiffMemConsAConvdtoi:
1950 ; P9BE: # %bb.0: # %entry
1951 ; P9BE-NEXT: lxv vs0, 0(r3)
1952 ; P9BE-NEXT: lxv vs1, 16(r3)
1953 ; P9BE-NEXT: xxmrgld vs2, vs0, vs1
1954 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
1955 ; P9BE-NEXT: xvcvdpsxws v2, vs2
1956 ; P9BE-NEXT: xvcvdpsxws v3, vs0
1957 ; P9BE-NEXT: vmrgew v2, v3, v2
1958 ; P9BE-NEXT: blr
1959 ;
1960 ; P9LE-LABEL: fromDiffMemConsAConvdtoi:
1961 ; P9LE: # %bb.0: # %entry
1962 ; P9LE-NEXT: lxv vs0, 0(r3)
1963 ; P9LE-NEXT: lxv vs1, 16(r3)
1964 ; P9LE-NEXT: xxmrgld vs2, vs1, vs0
1965 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
1966 ; P9LE-NEXT: xvcvdpsxws v2, vs2
1967 ; P9LE-NEXT: xvcvdpsxws v3, vs0
1968 ; P9LE-NEXT: vmrgew v2, v3, v2
1969 ; P9LE-NEXT: blr
1970 ;
1971 ; P8BE-LABEL: fromDiffMemConsAConvdtoi:
1972 ; P8BE: # %bb.0: # %entry
1973 ; P8BE-NEXT: li r4, 16
1974 ; P8BE-NEXT: lxvd2x vs0, 0, r3
1975 ; P8BE-NEXT: lxvd2x vs1, r3, r4
1976 ; P8BE-NEXT: xxmrgld vs2, vs0, vs1
1977 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
1978 ; P8BE-NEXT: xvcvdpsxws v2, vs2
1979 ; P8BE-NEXT: xvcvdpsxws v3, vs0
1980 ; P8BE-NEXT: vmrgew v2, v3, v2
1981 ; P8BE-NEXT: blr
1982 ;
1983 ; P8LE-LABEL: fromDiffMemConsAConvdtoi:
1984 ; P8LE: # %bb.0: # %entry
1985 ; P8LE-NEXT: li r4, 16
1986 ; P8LE-NEXT: lxvd2x vs0, 0, r3
1987 ; P8LE-NEXT: lxvd2x vs1, r3, r4
1988 ; P8LE-NEXT: xxswapd vs0, vs0
1989 ; P8LE-NEXT: xxswapd vs1, vs1
1990 ; P8LE-NEXT: xxmrgld vs2, vs1, vs0
1991 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
1992 ; P8LE-NEXT: xvcvdpsxws v2, vs2
1993 ; P8LE-NEXT: xvcvdpsxws v3, vs0
1994 ; P8LE-NEXT: vmrgew v2, v3, v2
1995 ; P8LE-NEXT: blr
1996 entry:
1997 %0 = bitcast double* %ptr to <2 x double>*
1998 %1 = load <2 x double>, <2 x double>* %0, align 8
1999 %2 = fptosi <2 x double> %1 to <2 x i32>
2000 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 2
2001 %3 = bitcast double* %arrayidx4 to <2 x double>*
2002 %4 = load <2 x double>, <2 x double>* %3, align 8
2003 %5 = fptosi <2 x double> %4 to <2 x i32>
2004 %vecinit9 = shufflevector <2 x i32> %2, <2 x i32> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
2005 ret <4 x i32> %vecinit9
2006 }
2008 ; Function Attrs: norecurse nounwind readonly
2009 define <4 x i32> @fromDiffMemConsDConvdtoi(double* nocapture readonly %ptr) {
2010 ; P9BE-LABEL: fromDiffMemConsDConvdtoi:
2011 ; P9BE: # %bb.0: # %entry
2012 ; P9BE-NEXT: lfd f0, 24(r3)
2013 ; P9BE-NEXT: lfd f1, 16(r3)
2014 ; P9BE-NEXT: lfd f2, 8(r3)
2015 ; P9BE-NEXT: xxmrghd vs0, vs0, vs2
2016 ; P9BE-NEXT: lfd f3, 0(r3)
2017 ; P9BE-NEXT: xxmrghd vs1, vs1, vs3
2018 ; P9BE-NEXT: xvcvdpsxws v2, vs1
2019 ; P9BE-NEXT: xvcvdpsxws v3, vs0
2020 ; P9BE-NEXT: vmrgew v2, v3, v2
2021 ; P9BE-NEXT: blr
2022 ;
2023 ; P9LE-LABEL: fromDiffMemConsDConvdtoi:
2024 ; P9LE: # %bb.0: # %entry
2025 ; P9LE-NEXT: lfd f0, 24(r3)
2026 ; P9LE-NEXT: lfd f2, 8(r3)
2027 ; P9LE-NEXT: xxmrghd vs0, vs2, vs0
2028 ; P9LE-NEXT: lfd f1, 16(r3)
2029 ; P9LE-NEXT: lfd f3, 0(r3)
2030 ; P9LE-NEXT: xvcvdpsxws v2, vs0
2031 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
2032 ; P9LE-NEXT: xvcvdpsxws v3, vs0
2033 ; P9LE-NEXT: vmrgew v2, v3, v2
2034 ; P9LE-NEXT: blr
2035 ;
2036 ; P8BE-LABEL: fromDiffMemConsDConvdtoi:
2037 ; P8BE: # %bb.0: # %entry
2038 ; P8BE-NEXT: lfdx f3, 0, r3
2039 ; P8BE-NEXT: lfd f0, 24(r3)
2040 ; P8BE-NEXT: lfd f1, 8(r3)
2041 ; P8BE-NEXT: lfd f2, 16(r3)
2042 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
2043 ; P8BE-NEXT: xxmrghd vs1, vs2, vs3
2044 ; P8BE-NEXT: xvcvdpsxws v2, vs0
2045 ; P8BE-NEXT: xvcvdpsxws v3, vs1
2046 ; P8BE-NEXT: vmrgew v2, v2, v3
2047 ; P8BE-NEXT: blr
2048 ;
2049 ; P8LE-LABEL: fromDiffMemConsDConvdtoi:
2050 ; P8LE: # %bb.0: # %entry
2051 ; P8LE-NEXT: lfdx f3, 0, r3
2052 ; P8LE-NEXT: lfd f0, 24(r3)
2053 ; P8LE-NEXT: lfd f1, 8(r3)
2054 ; P8LE-NEXT: lfd f2, 16(r3)
2055 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
2056 ; P8LE-NEXT: xxmrghd vs1, vs3, vs2
2057 ; P8LE-NEXT: xvcvdpsxws v2, vs0
2058 ; P8LE-NEXT: xvcvdpsxws v3, vs1
2059 ; P8LE-NEXT: vmrgew v2, v3, v2
2060 ; P8LE-NEXT: blr
2061 entry:
2062 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3
2063 %0 = load double, double* %arrayidx, align 8
2064 %conv = fptosi double %0 to i32
2065 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
2066 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2
2067 %1 = load double, double* %arrayidx1, align 8
2068 %conv2 = fptosi double %1 to i32
2069 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
2070 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 1
2071 %2 = load double, double* %arrayidx4, align 8
2072 %conv5 = fptosi double %2 to i32
2073 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
2074 %3 = load double, double* %ptr, align 8
2075 %conv8 = fptosi double %3 to i32
2076 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
2077 ret <4 x i32> %vecinit9
2078 }
2080 ; Function Attrs: norecurse nounwind readonly
2081 define <4 x i32> @fromDiffMemVarAConvdtoi(double* nocapture readonly %arr, i32 signext %elem) {
2082 ; P9BE-LABEL: fromDiffMemVarAConvdtoi:
2083 ; P9BE: # %bb.0: # %entry
2084 ; P9BE-NEXT: sldi r4, r4, 3
2085 ; P9BE-NEXT: lfdux f0, r3, r4
2086 ; P9BE-NEXT: lfd f1, 8(r3)
2087 ; P9BE-NEXT: lfd f2, 16(r3)
2088 ; P9BE-NEXT: lfd f3, 24(r3)
2089 ; P9BE-NEXT: xxmrghd vs1, vs1, vs3
2090 ; P9BE-NEXT: xxmrghd vs0, vs0, vs2
2091 ; P9BE-NEXT: xvcvdpsxws v2, vs1
2092 ; P9BE-NEXT: xvcvdpsxws v3, vs0
2093 ; P9BE-NEXT: vmrgew v2, v3, v2
2094 ; P9BE-NEXT: blr
2095 ;
2096 ; P9LE-LABEL: fromDiffMemVarAConvdtoi:
2097 ; P9LE: # %bb.0: # %entry
2098 ; P9LE-NEXT: sldi r4, r4, 3
2099 ; P9LE-NEXT: lfdux f0, r3, r4
2100 ; P9LE-NEXT: lfd f2, 16(r3)
2101 ; P9LE-NEXT: lfd f1, 8(r3)
2102 ; P9LE-NEXT: lfd f3, 24(r3)
2103 ; P9LE-NEXT: xxmrghd vs0, vs2, vs0
2104 ; P9LE-NEXT: xvcvdpsxws v2, vs0
2105 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
2106 ; P9LE-NEXT: xvcvdpsxws v3, vs0
2107 ; P9LE-NEXT: vmrgew v2, v3, v2
2108 ; P9LE-NEXT: blr
2109 ;
2110 ; P8BE-LABEL: fromDiffMemVarAConvdtoi:
2111 ; P8BE: # %bb.0: # %entry
2112 ; P8BE-NEXT: sldi r4, r4, 3
2113 ; P8BE-NEXT: lfdux f0, r3, r4
2114 ; P8BE-NEXT: lfd f1, 8(r3)
2115 ; P8BE-NEXT: lfd f2, 24(r3)
2116 ; P8BE-NEXT: lfd f3, 16(r3)
2117 ; P8BE-NEXT: xxmrghd vs1, vs1, vs2
2118 ; P8BE-NEXT: xxmrghd vs0, vs0, vs3
2119 ; P8BE-NEXT: xvcvdpsxws v2, vs1
2120 ; P8BE-NEXT: xvcvdpsxws v3, vs0
2121 ; P8BE-NEXT: vmrgew v2, v3, v2
2122 ; P8BE-NEXT: blr
2123 ;
2124 ; P8LE-LABEL: fromDiffMemVarAConvdtoi:
2125 ; P8LE: # %bb.0: # %entry
2126 ; P8LE-NEXT: sldi r4, r4, 3
2127 ; P8LE-NEXT: lfdux f0, r3, r4
2128 ; P8LE-NEXT: lfd f1, 16(r3)
2129 ; P8LE-NEXT: lfd f2, 8(r3)
2130 ; P8LE-NEXT: lfd f3, 24(r3)
2131 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
2132 ; P8LE-NEXT: xxmrghd vs1, vs3, vs2
2133 ; P8LE-NEXT: xvcvdpsxws v2, vs0
2134 ; P8LE-NEXT: xvcvdpsxws v3, vs1
2135 ; P8LE-NEXT: vmrgew v2, v3, v2
2136 ; P8LE-NEXT: blr
2137 entry:
2138 %idxprom = sext i32 %elem to i64
2139 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom
2140 %0 = load double, double* %arrayidx, align 8
2141 %conv = fptosi double %0 to i32
2142 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
2143 %add = add nsw i32 %elem, 1
2144 %idxprom1 = sext i32 %add to i64
2145 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1
2146 %1 = load double, double* %arrayidx2, align 8
2147 %conv3 = fptosi double %1 to i32
2148 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
2149 %add5 = add nsw i32 %elem, 2
2150 %idxprom6 = sext i32 %add5 to i64
2151 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6
2152 %2 = load double, double* %arrayidx7, align 8
2153 %conv8 = fptosi double %2 to i32
2154 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
2155 %add10 = add nsw i32 %elem, 3
2156 %idxprom11 = sext i32 %add10 to i64
2157 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11
2158 %3 = load double, double* %arrayidx12, align 8
2159 %conv13 = fptosi double %3 to i32
2160 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
2161 ret <4 x i32> %vecinit14
2162 }
2164 ; Function Attrs: norecurse nounwind readonly
2165 define <4 x i32> @fromDiffMemVarDConvdtoi(double* nocapture readonly %arr, i32 signext %elem) {
2166 ; P9BE-LABEL: fromDiffMemVarDConvdtoi:
2167 ; P9BE: # %bb.0: # %entry
2168 ; P9BE-NEXT: sldi r4, r4, 3
2169 ; P9BE-NEXT: lfdux f0, r3, r4
2170 ; P9BE-NEXT: lfd f1, -8(r3)
2171 ; P9BE-NEXT: lfd f2, -16(r3)
2172 ; P9BE-NEXT: lfd f3, -24(r3)
2173 ; P9BE-NEXT: xxmrghd vs1, vs1, vs3
2174 ; P9BE-NEXT: xxmrghd vs0, vs0, vs2
2175 ; P9BE-NEXT: xvcvdpsxws v2, vs1
2176 ; P9BE-NEXT: xvcvdpsxws v3, vs0
2177 ; P9BE-NEXT: vmrgew v2, v3, v2
2178 ; P9BE-NEXT: blr
2179 ;
2180 ; P9LE-LABEL: fromDiffMemVarDConvdtoi:
2181 ; P9LE: # %bb.0: # %entry
2182 ; P9LE-NEXT: sldi r4, r4, 3
2183 ; P9LE-NEXT: lfdux f0, r3, r4
2184 ; P9LE-NEXT: lfd f2, -16(r3)
2185 ; P9LE-NEXT: lfd f1, -8(r3)
2186 ; P9LE-NEXT: lfd f3, -24(r3)
2187 ; P9LE-NEXT: xxmrghd vs0, vs2, vs0
2188 ; P9LE-NEXT: xvcvdpsxws v2, vs0
2189 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
2190 ; P9LE-NEXT: xvcvdpsxws v3, vs0
2191 ; P9LE-NEXT: vmrgew v2, v3, v2
2192 ; P9LE-NEXT: blr
2193 ;
2194 ; P8BE-LABEL: fromDiffMemVarDConvdtoi:
2195 ; P8BE: # %bb.0: # %entry
2196 ; P8BE-NEXT: sldi r4, r4, 3
2197 ; P8BE-NEXT: lfdux f0, r3, r4
2198 ; P8BE-NEXT: lfd f1, -8(r3)
2199 ; P8BE-NEXT: lfd f2, -24(r3)
2200 ; P8BE-NEXT: lfd f3, -16(r3)
2201 ; P8BE-NEXT: xxmrghd vs1, vs1, vs2
2202 ; P8BE-NEXT: xxmrghd vs0, vs0, vs3
2203 ; P8BE-NEXT: xvcvdpsxws v2, vs1
2204 ; P8BE-NEXT: xvcvdpsxws v3, vs0
2205 ; P8BE-NEXT: vmrgew v2, v3, v2
2206 ; P8BE-NEXT: blr
2207 ;
2208 ; P8LE-LABEL: fromDiffMemVarDConvdtoi:
2209 ; P8LE: # %bb.0: # %entry
2210 ; P8LE-NEXT: sldi r4, r4, 3
2211 ; P8LE-NEXT: lfdux f0, r3, r4
2212 ; P8LE-NEXT: lfd f1, -16(r3)
2213 ; P8LE-NEXT: lfd f2, -8(r3)
2214 ; P8LE-NEXT: lfd f3, -24(r3)
2215 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
2216 ; P8LE-NEXT: xxmrghd vs1, vs3, vs2
2217 ; P8LE-NEXT: xvcvdpsxws v2, vs0
2218 ; P8LE-NEXT: xvcvdpsxws v3, vs1
2219 ; P8LE-NEXT: vmrgew v2, v3, v2
2220 ; P8LE-NEXT: blr
2221 entry:
2222 %idxprom = sext i32 %elem to i64
2223 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom
2224 %0 = load double, double* %arrayidx, align 8
2225 %conv = fptosi double %0 to i32
2226 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
2227 %sub = add nsw i32 %elem, -1
2228 %idxprom1 = sext i32 %sub to i64
2229 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1
2230 %1 = load double, double* %arrayidx2, align 8
2231 %conv3 = fptosi double %1 to i32
2232 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
2233 %sub5 = add nsw i32 %elem, -2
2234 %idxprom6 = sext i32 %sub5 to i64
2235 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6
2236 %2 = load double, double* %arrayidx7, align 8
2237 %conv8 = fptosi double %2 to i32
2238 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
2239 %sub10 = add nsw i32 %elem, -3
2240 %idxprom11 = sext i32 %sub10 to i64
2241 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11
2242 %3 = load double, double* %arrayidx12, align 8
2243 %conv13 = fptosi double %3 to i32
2244 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
2245 ret <4 x i32> %vecinit14
2246 }
2248 ; Function Attrs: norecurse nounwind readnone
2249 define <4 x i32> @spltRegValConvdtoi(double %val) {
2250 ; P9BE-LABEL: spltRegValConvdtoi:
2251 ; P9BE: # %bb.0: # %entry
2252 ; P9BE-NEXT: xscvdpsxws f0, f1
2253 ; P9BE-NEXT: xxspltw v2, vs0, 1
2254 ; P9BE-NEXT: blr
2255 ;
2256 ; P9LE-LABEL: spltRegValConvdtoi:
2257 ; P9LE: # %bb.0: # %entry
2258 ; P9LE-NEXT: xscvdpsxws f0, f1
2259 ; P9LE-NEXT: xxspltw v2, vs0, 1
2260 ; P9LE-NEXT: blr
2261 ;
2262 ; P8BE-LABEL: spltRegValConvdtoi:
2263 ; P8BE: # %bb.0: # %entry
2264 ; P8BE-NEXT: xscvdpsxws f0, f1
2265 ; P8BE-NEXT: xxspltw v2, vs0, 1
2266 ; P8BE-NEXT: blr
2267 ;
2268 ; P8LE-LABEL: spltRegValConvdtoi:
2269 ; P8LE: # %bb.0: # %entry
2270 ; P8LE-NEXT: xscvdpsxws f0, f1
2271 ; P8LE-NEXT: xxspltw v2, vs0, 1
2272 ; P8LE-NEXT: blr
2273 entry:
2274 %conv = fptosi double %val to i32
2275 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
2276 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
2277 ret <4 x i32> %splat.splat
2278 }
2280 ; Function Attrs: norecurse nounwind readonly
2281 define <4 x i32> @spltMemValConvdtoi(double* nocapture readonly %ptr) {
2282 ; P9BE-LABEL: spltMemValConvdtoi:
2283 ; P9BE: # %bb.0: # %entry
2284 ; P9BE-NEXT: lfd f0, 0(r3)
2285 ; P9BE-NEXT: xscvdpsxws f0, f0
2286 ; P9BE-NEXT: xxspltw v2, vs0, 1
2287 ; P9BE-NEXT: blr
2288 ;
2289 ; P9LE-LABEL: spltMemValConvdtoi:
2290 ; P9LE: # %bb.0: # %entry
2291 ; P9LE-NEXT: lfd f0, 0(r3)
2292 ; P9LE-NEXT: xscvdpsxws f0, f0
2293 ; P9LE-NEXT: xxspltw v2, vs0, 1
2294 ; P9LE-NEXT: blr
2295 ;
2296 ; P8BE-LABEL: spltMemValConvdtoi:
2297 ; P8BE: # %bb.0: # %entry
2298 ; P8BE-NEXT: lfdx f0, 0, r3
2299 ; P8BE-NEXT: xscvdpsxws f0, f0
2300 ; P8BE-NEXT: xxspltw v2, vs0, 1
2301 ; P8BE-NEXT: blr
2302 ;
2303 ; P8LE-LABEL: spltMemValConvdtoi:
2304 ; P8LE: # %bb.0: # %entry
2305 ; P8LE-NEXT: lfdx f0, 0, r3
2306 ; P8LE-NEXT: xscvdpsxws f0, f0
2307 ; P8LE-NEXT: xxspltw v2, vs0, 1
2308 ; P8LE-NEXT: blr
2309 entry:
2310 %0 = load double, double* %ptr, align 8
2311 %conv = fptosi double %0 to i32
2312 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
2313 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
2314 ret <4 x i32> %splat.splat
2315 }
2316 ; Function Attrs: norecurse nounwind readnone
2317 define <4 x i32> @allZeroui() {
2318 ; P9BE-LABEL: allZeroui:
2319 ; P9BE: # %bb.0: # %entry
2320 ; P9BE-NEXT: xxlxor v2, v2, v2
2321 ; P9BE-NEXT: blr
2322 ;
2323 ; P9LE-LABEL: allZeroui:
2324 ; P9LE: # %bb.0: # %entry
2325 ; P9LE-NEXT: xxlxor v2, v2, v2
2326 ; P9LE-NEXT: blr
2327 ;
2328 ; P8BE-LABEL: allZeroui:
2329 ; P8BE: # %bb.0: # %entry
2330 ; P8BE-NEXT: xxlxor v2, v2, v2
2331 ; P8BE-NEXT: blr
2332 ;
2333 ; P8LE-LABEL: allZeroui:
2334 ; P8LE: # %bb.0: # %entry
2335 ; P8LE-NEXT: xxlxor v2, v2, v2
2336 ; P8LE-NEXT: blr
2337 entry:
2338 ret <4 x i32> zeroinitializer
2339 }
2341 ; Function Attrs: norecurse nounwind readnone
2342 define <4 x i32> @allOneui() {
2343 ; P9BE-LABEL: allOneui:
2344 ; P9BE: # %bb.0: # %entry
2345 ; P9BE-NEXT: xxspltib v2, 255
2346 ; P9BE-NEXT: blr
2347 ;
2348 ; P9LE-LABEL: allOneui:
2349 ; P9LE: # %bb.0: # %entry
2350 ; P9LE-NEXT: xxspltib v2, 255
2351 ; P9LE-NEXT: blr
2352 ;
2353 ; P8BE-LABEL: allOneui:
2354 ; P8BE: # %bb.0: # %entry
2355 ; P8BE-NEXT: vspltisb v2, -1
2356 ; P8BE-NEXT: blr
2357 ;
2358 ; P8LE-LABEL: allOneui:
2359 ; P8LE: # %bb.0: # %entry
2360 ; P8LE-NEXT: vspltisb v2, -1
2361 ; P8LE-NEXT: blr
2362 entry:
2363 ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
2364 }
2366 ; Function Attrs: norecurse nounwind readnone
2367 define <4 x i32> @spltConst1ui() {
2368 ; P9BE-LABEL: spltConst1ui:
2369 ; P9BE: # %bb.0: # %entry
2370 ; P9BE-NEXT: vspltisw v2, 1
2371 ; P9BE-NEXT: blr
2372 ;
2373 ; P9LE-LABEL: spltConst1ui:
2374 ; P9LE: # %bb.0: # %entry
2375 ; P9LE-NEXT: vspltisw v2, 1
2376 ; P9LE-NEXT: blr
2377 ;
2378 ; P8BE-LABEL: spltConst1ui:
2379 ; P8BE: # %bb.0: # %entry
2380 ; P8BE-NEXT: vspltisw v2, 1
2381 ; P8BE-NEXT: blr
2382 ;
2383 ; P8LE-LABEL: spltConst1ui:
2384 ; P8LE: # %bb.0: # %entry
2385 ; P8LE-NEXT: vspltisw v2, 1
2386 ; P8LE-NEXT: blr
2387 entry:
2388 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1>
2389 }
2391 ; Function Attrs: norecurse nounwind readnone
2392 define <4 x i32> @spltConst16kui() {
2393 ; P9BE-LABEL: spltConst16kui:
2394 ; P9BE: # %bb.0: # %entry
2395 ; P9BE-NEXT: vspltisw v2, -15
2396 ; P9BE-NEXT: vsrw v2, v2, v2
2397 ; P9BE-NEXT: blr
2398 ;
2399 ; P9LE-LABEL: spltConst16kui:
2400 ; P9LE: # %bb.0: # %entry
2401 ; P9LE-NEXT: vspltisw v2, -15
2402 ; P9LE-NEXT: vsrw v2, v2, v2
2403 ; P9LE-NEXT: blr
2404 ;
2405 ; P8BE-LABEL: spltConst16kui:
2406 ; P8BE: # %bb.0: # %entry
2407 ; P8BE-NEXT: vspltisw v2, -15
2408 ; P8BE-NEXT: vsrw v2, v2, v2
2409 ; P8BE-NEXT: blr
2410 ;
2411 ; P8LE-LABEL: spltConst16kui:
2412 ; P8LE: # %bb.0: # %entry
2413 ; P8LE-NEXT: vspltisw v2, -15
2414 ; P8LE-NEXT: vsrw v2, v2, v2
2415 ; P8LE-NEXT: blr
2416 entry:
2417 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>
2418 }
2420 ; Function Attrs: norecurse nounwind readnone
2421 define <4 x i32> @spltConst32kui() {
2422 ; P9BE-LABEL: spltConst32kui:
2423 ; P9BE: # %bb.0: # %entry
2424 ; P9BE-NEXT: vspltisw v2, -16
2425 ; P9BE-NEXT: vsrw v2, v2, v2
2426 ; P9BE-NEXT: blr
2427 ;
2428 ; P9LE-LABEL: spltConst32kui:
2429 ; P9LE: # %bb.0: # %entry
2430 ; P9LE-NEXT: vspltisw v2, -16
2431 ; P9LE-NEXT: vsrw v2, v2, v2
2432 ; P9LE-NEXT: blr
2433 ;
2434 ; P8BE-LABEL: spltConst32kui:
2435 ; P8BE: # %bb.0: # %entry
2436 ; P8BE-NEXT: vspltisw v2, -16
2437 ; P8BE-NEXT: vsrw v2, v2, v2
2438 ; P8BE-NEXT: blr
2439 ;
2440 ; P8LE-LABEL: spltConst32kui:
2441 ; P8LE: # %bb.0: # %entry
2442 ; P8LE-NEXT: vspltisw v2, -16
2443 ; P8LE-NEXT: vsrw v2, v2, v2
2444 ; P8LE-NEXT: blr
2445 entry:
2446 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
2447 }
2449 ; Function Attrs: norecurse nounwind readnone
2450 define <4 x i32> @fromRegsui(i32 zeroext %a, i32 zeroext %b, i32 zeroext %c, i32 zeroext %d) {
2451 ; P9BE-LABEL: fromRegsui:
2452 ; P9BE: # %bb.0: # %entry
2453 ; P9BE-NEXT: rldimi r6, r5, 32, 0
2454 ; P9BE-NEXT: rldimi r4, r3, 32, 0
2455 ; P9BE-NEXT: mtvsrdd v2, r4, r6
2456 ; P9BE-NEXT: blr
2457 ;
2458 ; P9LE-LABEL: fromRegsui:
2459 ; P9LE: # %bb.0: # %entry
2460 ; P9LE-NEXT: rldimi r3, r4, 32, 0
2461 ; P9LE-NEXT: rldimi r5, r6, 32, 0
2462 ; P9LE-NEXT: mtvsrdd v2, r5, r3
2463 ; P9LE-NEXT: blr
2464 ;
2465 ; P8BE-LABEL: fromRegsui:
2466 ; P8BE: # %bb.0: # %entry
2467 ; P8BE-NEXT: rldimi r6, r5, 32, 0
2468 ; P8BE-NEXT: rldimi r4, r3, 32, 0
2469 ; P8BE-NEXT: mtvsrd f0, r6
2470 ; P8BE-NEXT: mtvsrd f1, r4
2471 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
2472 ; P8BE-NEXT: blr
2473 ;
2474 ; P8LE-LABEL: fromRegsui:
2475 ; P8LE: # %bb.0: # %entry
2476 ; P8LE-NEXT: rldimi r3, r4, 32, 0
2477 ; P8LE-NEXT: rldimi r5, r6, 32, 0
2478 ; P8LE-NEXT: mtvsrd f0, r3
2479 ; P8LE-NEXT: mtvsrd f1, r5
2480 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
2481 ; P8LE-NEXT: blr
2482 entry:
2483 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0
2484 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1
2485 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2
2486 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3
2487 ret <4 x i32> %vecinit3
2488 }
2490 ; Function Attrs: norecurse nounwind readnone
2491 define <4 x i32> @fromDiffConstsui() {
2492 ; P9BE-LABEL: fromDiffConstsui:
2493 ; P9BE: # %bb.0: # %entry
2494 ; P9BE-NEXT: addis r3, r2, .LCPI39_0@toc@ha
2495 ; P9BE-NEXT: addi r3, r3, .LCPI39_0@toc@l
2496 ; P9BE-NEXT: lxvx v2, 0, r3
2497 ; P9BE-NEXT: blr
2498 ;
2499 ; P9LE-LABEL: fromDiffConstsui:
2500 ; P9LE: # %bb.0: # %entry
2501 ; P9LE-NEXT: addis r3, r2, .LCPI39_0@toc@ha
2502 ; P9LE-NEXT: addi r3, r3, .LCPI39_0@toc@l
2503 ; P9LE-NEXT: lxvx v2, 0, r3
2504 ; P9LE-NEXT: blr
2505 ;
2506 ; P8BE-LABEL: fromDiffConstsui:
2507 ; P8BE: # %bb.0: # %entry
2508 ; P8BE-NEXT: addis r3, r2, .LCPI39_0@toc@ha
2509 ; P8BE-NEXT: addi r3, r3, .LCPI39_0@toc@l
2510 ; P8BE-NEXT: lxvw4x v2, 0, r3
2511 ; P8BE-NEXT: blr
2512 ;
2513 ; P8LE-LABEL: fromDiffConstsui:
2514 ; P8LE: # %bb.0: # %entry
2515 ; P8LE-NEXT: addis r3, r2, .LCPI39_0@toc@ha
2516 ; P8LE-NEXT: addi r3, r3, .LCPI39_0@toc@l
2517 ; P8LE-NEXT: lvx v2, 0, r3
2518 ; P8LE-NEXT: blr
2519 entry:
2520 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19>
2521 }
2523 ; Function Attrs: norecurse nounwind readonly
2524 define <4 x i32> @fromDiffMemConsAui(i32* nocapture readonly %arr) {
2525 ; P9BE-LABEL: fromDiffMemConsAui:
2526 ; P9BE: # %bb.0: # %entry
2527 ; P9BE-NEXT: lxv v2, 0(r3)
2528 ; P9BE-NEXT: blr
2529 ;
2530 ; P9LE-LABEL: fromDiffMemConsAui:
2531 ; P9LE: # %bb.0: # %entry
2532 ; P9LE-NEXT: lxv v2, 0(r3)
2533 ; P9LE-NEXT: blr
2534 ;
2535 ; P8BE-LABEL: fromDiffMemConsAui:
2536 ; P8BE: # %bb.0: # %entry
2537 ; P8BE-NEXT: lxvw4x v2, 0, r3
2538 ; P8BE-NEXT: blr
2539 ;
2540 ; P8LE-LABEL: fromDiffMemConsAui:
2541 ; P8LE: # %bb.0: # %entry
2542 ; P8LE-NEXT: lxvd2x vs0, 0, r3
2543 ; P8LE-NEXT: xxswapd v2, vs0
2544 ; P8LE-NEXT: blr
2545 entry:
2546 %0 = load i32, i32* %arr, align 4
2547 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
2548 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 1
2549 %1 = load i32, i32* %arrayidx1, align 4
2550 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
2551 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2
2552 %2 = load i32, i32* %arrayidx3, align 4
2553 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2
2554 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 3
2555 %3 = load i32, i32* %arrayidx5, align 4
2556 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3
2557 ret <4 x i32> %vecinit6
2558 }
2560 ; Function Attrs: norecurse nounwind readonly
2561 define <4 x i32> @fromDiffMemConsDui(i32* nocapture readonly %arr) {
2562 ; P9BE-LABEL: fromDiffMemConsDui:
2563 ; P9BE: # %bb.0: # %entry
2564 ; P9BE-NEXT: lxv v2, 0(r3)
2565 ; P9BE-NEXT: addis r3, r2, .LCPI41_0@toc@ha
2566 ; P9BE-NEXT: addi r3, r3, .LCPI41_0@toc@l
2567 ; P9BE-NEXT: lxvx v3, 0, r3
2568 ; P9BE-NEXT: vperm v2, v2, v2, v3
2569 ; P9BE-NEXT: blr
2570 ;
2571 ; P9LE-LABEL: fromDiffMemConsDui:
2572 ; P9LE: # %bb.0: # %entry
2573 ; P9LE-NEXT: lxv v2, 0(r3)
2574 ; P9LE-NEXT: addis r3, r2, .LCPI41_0@toc@ha
2575 ; P9LE-NEXT: addi r3, r3, .LCPI41_0@toc@l
2576 ; P9LE-NEXT: lxvx v3, 0, r3
2577 ; P9LE-NEXT: vperm v2, v2, v2, v3
2578 ; P9LE-NEXT: blr
2579 ;
2580 ; P8BE-LABEL: fromDiffMemConsDui:
2581 ; P8BE: # %bb.0: # %entry
2582 ; P8BE-NEXT: addis r4, r2, .LCPI41_0@toc@ha
2583 ; P8BE-NEXT: lxvw4x v2, 0, r3
2584 ; P8BE-NEXT: addi r4, r4, .LCPI41_0@toc@l
2585 ; P8BE-NEXT: lxvw4x v3, 0, r4
2586 ; P8BE-NEXT: vperm v2, v2, v2, v3
2587 ; P8BE-NEXT: blr
2588 ;
2589 ; P8LE-LABEL: fromDiffMemConsDui:
2590 ; P8LE: # %bb.0: # %entry
2591 ; P8LE-NEXT: lxvd2x vs0, 0, r3
2592 ; P8LE-NEXT: addis r4, r2, .LCPI41_0@toc@ha
2593 ; P8LE-NEXT: addi r3, r4, .LCPI41_0@toc@l
2594 ; P8LE-NEXT: lvx v2, 0, r3
2595 ; P8LE-NEXT: xxswapd v3, vs0
2596 ; P8LE-NEXT: vperm v2, v3, v3, v2
2597 ; P8LE-NEXT: blr
2598 entry:
2599 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 3
2600 %0 = load i32, i32* %arrayidx, align 4
2601 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
2602 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2
2603 %1 = load i32, i32* %arrayidx1, align 4
2604 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
2605 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 1
2606 %2 = load i32, i32* %arrayidx3, align 4
2607 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2
2608 %3 = load i32, i32* %arr, align 4
2609 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3
2610 ret <4 x i32> %vecinit6
2611 }
2613 ; Function Attrs: norecurse nounwind readonly
2614 define <4 x i32> @fromDiffMemVarAui(i32* nocapture readonly %arr, i32 signext %elem) {
2615 ; P9BE-LABEL: fromDiffMemVarAui:
2616 ; P9BE: # %bb.0: # %entry
2617 ; P9BE-NEXT: sldi r4, r4, 2
2618 ; P9BE-NEXT: lxvx v2, r3, r4
2619 ; P9BE-NEXT: blr
2620 ;
2621 ; P9LE-LABEL: fromDiffMemVarAui:
2622 ; P9LE: # %bb.0: # %entry
2623 ; P9LE-NEXT: sldi r4, r4, 2
2624 ; P9LE-NEXT: lxvx v2, r3, r4
2625 ; P9LE-NEXT: blr
2626 ;
2627 ; P8BE-LABEL: fromDiffMemVarAui:
2628 ; P8BE: # %bb.0: # %entry
2629 ; P8BE-NEXT: sldi r4, r4, 2
2630 ; P8BE-NEXT: lxvw4x v2, r3, r4
2631 ; P8BE-NEXT: blr
2632 ;
2633 ; P8LE-LABEL: fromDiffMemVarAui:
2634 ; P8LE: # %bb.0: # %entry
2635 ; P8LE-NEXT: sldi r4, r4, 2
2636 ; P8LE-NEXT: lxvd2x vs0, r3, r4
2637 ; P8LE-NEXT: xxswapd v2, vs0
2638 ; P8LE-NEXT: blr
2639 entry:
2640 %idxprom = sext i32 %elem to i64
2641 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom
2642 %0 = load i32, i32* %arrayidx, align 4
2643 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
2644 %add = add nsw i32 %elem, 1
2645 %idxprom1 = sext i32 %add to i64
2646 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1
2647 %1 = load i32, i32* %arrayidx2, align 4
2648 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
2649 %add4 = add nsw i32 %elem, 2
2650 %idxprom5 = sext i32 %add4 to i64
2651 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5
2652 %2 = load i32, i32* %arrayidx6, align 4
2653 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2
2654 %add8 = add nsw i32 %elem, 3
2655 %idxprom9 = sext i32 %add8 to i64
2656 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9
2657 %3 = load i32, i32* %arrayidx10, align 4
2658 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3
2659 ret <4 x i32> %vecinit11
2660 }
2662 ; Function Attrs: norecurse nounwind readonly
2663 define <4 x i32> @fromDiffMemVarDui(i32* nocapture readonly %arr, i32 signext %elem) {
2664 ; P9BE-LABEL: fromDiffMemVarDui:
2665 ; P9BE: # %bb.0: # %entry
2666 ; P9BE-NEXT: sldi r4, r4, 2
2667 ; P9BE-NEXT: add r3, r3, r4
2668 ; P9BE-NEXT: addi r3, r3, -12
2669 ; P9BE-NEXT: lxvx v2, 0, r3
2670 ; P9BE-NEXT: addis r3, r2, .LCPI43_0@toc@ha
2671 ; P9BE-NEXT: addi r3, r3, .LCPI43_0@toc@l
2672 ; P9BE-NEXT: lxvx v3, 0, r3
2673 ; P9BE-NEXT: vperm v2, v2, v2, v3
2674 ; P9BE-NEXT: blr
2675 ;
2676 ; P9LE-LABEL: fromDiffMemVarDui:
2677 ; P9LE: # %bb.0: # %entry
2678 ; P9LE-NEXT: sldi r4, r4, 2
2679 ; P9LE-NEXT: add r3, r3, r4
2680 ; P9LE-NEXT: addi r3, r3, -12
2681 ; P9LE-NEXT: lxvx v2, 0, r3
2682 ; P9LE-NEXT: addis r3, r2, .LCPI43_0@toc@ha
2683 ; P9LE-NEXT: addi r3, r3, .LCPI43_0@toc@l
2684 ; P9LE-NEXT: lxvx v3, 0, r3
2685 ; P9LE-NEXT: vperm v2, v2, v2, v3
2686 ; P9LE-NEXT: blr
2687 ;
2688 ; P8BE-LABEL: fromDiffMemVarDui:
2689 ; P8BE: # %bb.0: # %entry
2690 ; P8BE-NEXT: sldi r4, r4, 2
2691 ; P8BE-NEXT: addis r5, r2, .LCPI43_0@toc@ha
2692 ; P8BE-NEXT: add r3, r3, r4
2693 ; P8BE-NEXT: addi r4, r5, .LCPI43_0@toc@l
2694 ; P8BE-NEXT: addi r3, r3, -12
2695 ; P8BE-NEXT: lxvw4x v3, 0, r4
2696 ; P8BE-NEXT: lxvw4x v2, 0, r3
2697 ; P8BE-NEXT: vperm v2, v2, v2, v3
2698 ; P8BE-NEXT: blr
2699 ;
2700 ; P8LE-LABEL: fromDiffMemVarDui:
2701 ; P8LE: # %bb.0: # %entry
2702 ; P8LE-NEXT: sldi r4, r4, 2
2703 ; P8LE-NEXT: addis r5, r2, .LCPI43_0@toc@ha
2704 ; P8LE-NEXT: add r3, r3, r4
2705 ; P8LE-NEXT: addi r3, r3, -12
2706 ; P8LE-NEXT: lxvd2x vs0, 0, r3
2707 ; P8LE-NEXT: addi r3, r5, .LCPI43_0@toc@l
2708 ; P8LE-NEXT: lvx v3, 0, r3
2709 ; P8LE-NEXT: xxswapd v2, vs0
2710 ; P8LE-NEXT: vperm v2, v2, v2, v3
2711 ; P8LE-NEXT: blr
2712 entry:
2713 %idxprom = sext i32 %elem to i64
2714 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom
2715 %0 = load i32, i32* %arrayidx, align 4
2716 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
2717 %sub = add nsw i32 %elem, -1
2718 %idxprom1 = sext i32 %sub to i64
2719 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1
2720 %1 = load i32, i32* %arrayidx2, align 4
2721 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
2722 %sub4 = add nsw i32 %elem, -2
2723 %idxprom5 = sext i32 %sub4 to i64
2724 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5
2725 %2 = load i32, i32* %arrayidx6, align 4
2726 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2
2727 %sub8 = add nsw i32 %elem, -3
2728 %idxprom9 = sext i32 %sub8 to i64
2729 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9
2730 %3 = load i32, i32* %arrayidx10, align 4
2731 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3
2732 ret <4 x i32> %vecinit11
2733 }
2735 ; Function Attrs: norecurse nounwind readonly
2736 define <4 x i32> @fromRandMemConsui(i32* nocapture readonly %arr) {
2737 ; P9BE-LABEL: fromRandMemConsui:
2738 ; P9BE: # %bb.0: # %entry
2739 ; P9BE-NEXT: lwz r4, 16(r3)
2740 ; P9BE-NEXT: lwz r5, 72(r3)
2741 ; P9BE-NEXT: lwz r6, 8(r3)
2742 ; P9BE-NEXT: lwz r3, 352(r3)
2743 ; P9BE-NEXT: rldimi r3, r6, 32, 0
2744 ; P9BE-NEXT: rldimi r5, r4, 32, 0
2745 ; P9BE-NEXT: mtvsrdd v2, r5, r3
2746 ; P9BE-NEXT: blr
2747 ;
2748 ; P9LE-LABEL: fromRandMemConsui:
2749 ; P9LE: # %bb.0: # %entry
2750 ; P9LE-NEXT: lwz r4, 16(r3)
2751 ; P9LE-NEXT: lwz r5, 72(r3)
2752 ; P9LE-NEXT: lwz r6, 8(r3)
2753 ; P9LE-NEXT: lwz r3, 352(r3)
2754 ; P9LE-NEXT: rldimi r4, r5, 32, 0
2755 ; P9LE-NEXT: rldimi r6, r3, 32, 0
2756 ; P9LE-NEXT: mtvsrdd v2, r6, r4
2757 ; P9LE-NEXT: blr
2758 ;
2759 ; P8BE-LABEL: fromRandMemConsui:
2760 ; P8BE: # %bb.0: # %entry
2761 ; P8BE-NEXT: lwz r4, 8(r3)
2762 ; P8BE-NEXT: lwz r5, 352(r3)
2763 ; P8BE-NEXT: lwz r6, 16(r3)
2764 ; P8BE-NEXT: lwz r3, 72(r3)
2765 ; P8BE-NEXT: rldimi r5, r4, 32, 0
2766 ; P8BE-NEXT: rldimi r3, r6, 32, 0
2767 ; P8BE-NEXT: mtvsrd f0, r5
2768 ; P8BE-NEXT: mtvsrd f1, r3
2769 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
2770 ; P8BE-NEXT: blr
2771 ;
2772 ; P8LE-LABEL: fromRandMemConsui:
2773 ; P8LE: # %bb.0: # %entry
2774 ; P8LE-NEXT: lwz r4, 16(r3)
2775 ; P8LE-NEXT: lwz r5, 72(r3)
2776 ; P8LE-NEXT: lwz r6, 8(r3)
2777 ; P8LE-NEXT: lwz r3, 352(r3)
2778 ; P8LE-NEXT: rldimi r4, r5, 32, 0
2779 ; P8LE-NEXT: rldimi r6, r3, 32, 0
2780 ; P8LE-NEXT: mtvsrd f0, r4
2781 ; P8LE-NEXT: mtvsrd f1, r6
2782 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
2783 ; P8LE-NEXT: blr
2784 entry:
2785 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 4
2786 %0 = load i32, i32* %arrayidx, align 4
2787 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
2788 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 18
2789 %1 = load i32, i32* %arrayidx1, align 4
2790 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
2791 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2
2792 %2 = load i32, i32* %arrayidx3, align 4
2793 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2
2794 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 88
2795 %3 = load i32, i32* %arrayidx5, align 4
2796 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3
2797 ret <4 x i32> %vecinit6
2798 }
2800 ; Function Attrs: norecurse nounwind readonly
2801 define <4 x i32> @fromRandMemVarui(i32* nocapture readonly %arr, i32 signext %elem) {
2802 ; P9BE-LABEL: fromRandMemVarui:
2803 ; P9BE: # %bb.0: # %entry
2804 ; P9BE-NEXT: sldi r4, r4, 2
2805 ; P9BE-NEXT: add r3, r3, r4
2806 ; P9BE-NEXT: lwz r4, 16(r3)
2807 ; P9BE-NEXT: lwz r5, 4(r3)
2808 ; P9BE-NEXT: lwz r6, 8(r3)
2809 ; P9BE-NEXT: lwz r3, 32(r3)
2810 ; P9BE-NEXT: rldimi r3, r6, 32, 0
2811 ; P9BE-NEXT: rldimi r5, r4, 32, 0
2812 ; P9BE-NEXT: mtvsrdd v2, r5, r3
2813 ; P9BE-NEXT: blr
2814 ;
2815 ; P9LE-LABEL: fromRandMemVarui:
2816 ; P9LE: # %bb.0: # %entry
2817 ; P9LE-NEXT: sldi r4, r4, 2
2818 ; P9LE-NEXT: add r3, r3, r4
2819 ; P9LE-NEXT: lwz r4, 16(r3)
2820 ; P9LE-NEXT: lwz r5, 4(r3)
2821 ; P9LE-NEXT: lwz r6, 8(r3)
2822 ; P9LE-NEXT: lwz r3, 32(r3)
2823 ; P9LE-NEXT: rldimi r4, r5, 32, 0
2824 ; P9LE-NEXT: rldimi r6, r3, 32, 0
2825 ; P9LE-NEXT: mtvsrdd v2, r6, r4
2826 ; P9LE-NEXT: blr
2827 ;
2828 ; P8BE-LABEL: fromRandMemVarui:
2829 ; P8BE: # %bb.0: # %entry
2830 ; P8BE-NEXT: sldi r4, r4, 2
2831 ; P8BE-NEXT: add r3, r3, r4
2832 ; P8BE-NEXT: lwz r4, 8(r3)
2833 ; P8BE-NEXT: lwz r5, 32(r3)
2834 ; P8BE-NEXT: lwz r6, 16(r3)
2835 ; P8BE-NEXT: lwz r3, 4(r3)
2836 ; P8BE-NEXT: rldimi r5, r4, 32, 0
2837 ; P8BE-NEXT: rldimi r3, r6, 32, 0
2838 ; P8BE-NEXT: mtvsrd f0, r5
2839 ; P8BE-NEXT: mtvsrd f1, r3
2840 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
2841 ; P8BE-NEXT: blr
2842 ;
2843 ; P8LE-LABEL: fromRandMemVarui:
2844 ; P8LE: # %bb.0: # %entry
2845 ; P8LE-NEXT: sldi r4, r4, 2
2846 ; P8LE-NEXT: add r3, r3, r4
2847 ; P8LE-NEXT: lwz r4, 16(r3)
2848 ; P8LE-NEXT: lwz r5, 4(r3)
2849 ; P8LE-NEXT: lwz r6, 8(r3)
2850 ; P8LE-NEXT: lwz r3, 32(r3)
2851 ; P8LE-NEXT: rldimi r4, r5, 32, 0
2852 ; P8LE-NEXT: rldimi r6, r3, 32, 0
2853 ; P8LE-NEXT: mtvsrd f0, r4
2854 ; P8LE-NEXT: mtvsrd f1, r6
2855 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
2856 ; P8LE-NEXT: blr
2857 entry:
2858 %add = add nsw i32 %elem, 4
2859 %idxprom = sext i32 %add to i64
2860 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom
2861 %0 = load i32, i32* %arrayidx, align 4
2862 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
2863 %add1 = add nsw i32 %elem, 1
2864 %idxprom2 = sext i32 %add1 to i64
2865 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 %idxprom2
2866 %1 = load i32, i32* %arrayidx3, align 4
2867 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
2868 %add5 = add nsw i32 %elem, 2
2869 %idxprom6 = sext i32 %add5 to i64
2870 %arrayidx7 = getelementptr inbounds i32, i32* %arr, i64 %idxprom6
2871 %2 = load i32, i32* %arrayidx7, align 4
2872 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2
2873 %add9 = add nsw i32 %elem, 8
2874 %idxprom10 = sext i32 %add9 to i64
2875 %arrayidx11 = getelementptr inbounds i32, i32* %arr, i64 %idxprom10
2876 %3 = load i32, i32* %arrayidx11, align 4
2877 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3
2878 ret <4 x i32> %vecinit12
2879 }
2881 ; Function Attrs: norecurse nounwind readnone
2882 define <4 x i32> @spltRegValui(i32 zeroext %val) {
2883 ; P9BE-LABEL: spltRegValui:
2884 ; P9BE: # %bb.0: # %entry
2885 ; P9BE-NEXT: mtvsrws v2, r3
2886 ; P9BE-NEXT: blr
2887 ;
2888 ; P9LE-LABEL: spltRegValui:
2889 ; P9LE: # %bb.0: # %entry
2890 ; P9LE-NEXT: mtvsrws v2, r3
2891 ; P9LE-NEXT: blr
2892 ;
2893 ; P8BE-LABEL: spltRegValui:
2894 ; P8BE: # %bb.0: # %entry
2895 ; P8BE-NEXT: mtvsrwz f0, r3
2896 ; P8BE-NEXT: xxspltw v2, vs0, 1
2897 ; P8BE-NEXT: blr
2898 ;
2899 ; P8LE-LABEL: spltRegValui:
2900 ; P8LE: # %bb.0: # %entry
2901 ; P8LE-NEXT: mtvsrwz f0, r3
2902 ; P8LE-NEXT: xxspltw v2, vs0, 1
2903 ; P8LE-NEXT: blr
2904 entry:
2905 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0
2906 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
2907 ret <4 x i32> %splat.splat
2908 }
2910 ; Function Attrs: norecurse nounwind readonly
2911 define <4 x i32> @spltMemValui(i32* nocapture readonly %ptr) {
2912 ; P9BE-LABEL: spltMemValui:
2913 ; P9BE: # %bb.0: # %entry
2914 ; P9BE-NEXT: lfiwzx f0, 0, r3
2915 ; P9BE-NEXT: xxsldwi vs0, f0, f0, 1
2916 ; P9BE-NEXT: xxspltw v2, vs0, 0
2917 ; P9BE-NEXT: blr
2918 ;
2919 ; P9LE-LABEL: spltMemValui:
2920 ; P9LE: # %bb.0: # %entry
2921 ; P9LE-NEXT: lfiwzx f0, 0, r3
2922 ; P9LE-NEXT: xxpermdi vs0, f0, f0, 2
2923 ; P9LE-NEXT: xxspltw v2, vs0, 3
2924 ; P9LE-NEXT: blr
2925 ;
2926 ; P8BE-LABEL: spltMemValui:
2927 ; P8BE: # %bb.0: # %entry
2928 ; P8BE-NEXT: lfiwzx f0, 0, r3
2929 ; P8BE-NEXT: xxsldwi vs0, f0, f0, 1
2930 ; P8BE-NEXT: xxspltw v2, vs0, 0
2931 ; P8BE-NEXT: blr
2932 ;
2933 ; P8LE-LABEL: spltMemValui:
2934 ; P8LE: # %bb.0: # %entry
2935 ; P8LE-NEXT: lfiwzx f0, 0, r3
2936 ; P8LE-NEXT: xxpermdi vs0, f0, f0, 2
2937 ; P8LE-NEXT: xxspltw v2, vs0, 3
2938 ; P8LE-NEXT: blr
2939 entry:
2940 %0 = load i32, i32* %ptr, align 4
2941 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0
2942 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
2943 ret <4 x i32> %splat.splat
2944 }
2946 ; Function Attrs: norecurse nounwind readnone
2947 define <4 x i32> @spltCnstConvftoui() {
2948 ; P9BE-LABEL: spltCnstConvftoui:
2949 ; P9BE: # %bb.0: # %entry
2950 ; P9BE-NEXT: vspltisw v2, 4
2951 ; P9BE-NEXT: blr
2952 ;
2953 ; P9LE-LABEL: spltCnstConvftoui:
2954 ; P9LE: # %bb.0: # %entry
2955 ; P9LE-NEXT: vspltisw v2, 4
2956 ; P9LE-NEXT: blr
2957 ;
2958 ; P8BE-LABEL: spltCnstConvftoui:
2959 ; P8BE: # %bb.0: # %entry
2960 ; P8BE-NEXT: vspltisw v2, 4
2961 ; P8BE-NEXT: blr
2962 ;
2963 ; P8LE-LABEL: spltCnstConvftoui:
2964 ; P8LE: # %bb.0: # %entry
2965 ; P8LE-NEXT: vspltisw v2, 4
2966 ; P8LE-NEXT: blr
2967 entry:
2968 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4>
2969 }
2971 ; Function Attrs: norecurse nounwind readnone
2972 define <4 x i32> @fromRegsConvftoui(float %a, float %b, float %c, float %d) {
2973 ; P9BE-LABEL: fromRegsConvftoui:
2974 ; P9BE: # %bb.0: # %entry
2975 ; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4
2976 ; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
2977 ; P9BE-NEXT: xxmrghd vs0, vs2, vs4
2978 ; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3
2979 ; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
2980 ; P9BE-NEXT: xvcvdpuxws v2, vs0
2981 ; P9BE-NEXT: xxmrghd vs0, vs1, vs3
2982 ; P9BE-NEXT: xvcvdpuxws v3, vs0
2983 ; P9BE-NEXT: vmrgew v2, v3, v2
2984 ; P9BE-NEXT: blr
2985 ;
2986 ; P9LE-LABEL: fromRegsConvftoui:
2987 ; P9LE: # %bb.0: # %entry
2988 ; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3
2989 ; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
2990 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
2991 ; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4
2992 ; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
2993 ; P9LE-NEXT: xvcvdpuxws v2, vs0
2994 ; P9LE-NEXT: xxmrghd vs0, vs4, vs2
2995 ; P9LE-NEXT: xvcvdpuxws v3, vs0
2996 ; P9LE-NEXT: vmrgew v2, v3, v2
2997 ; P9LE-NEXT: blr
2998 ;
2999 ; P8BE-LABEL: fromRegsConvftoui:
3000 ; P8BE: # %bb.0: # %entry
3001 ; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
3002 ; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4
3003 ; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3
3004 ; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
3005 ; P8BE-NEXT: xxmrghd vs0, vs2, vs4
3006 ; P8BE-NEXT: xxmrghd vs1, vs1, vs3
3007 ; P8BE-NEXT: xvcvdpuxws v2, vs0
3008 ; P8BE-NEXT: xvcvdpuxws v3, vs1
3009 ; P8BE-NEXT: vmrgew v2, v3, v2
3010 ; P8BE-NEXT: blr
3011 ;
3012 ; P8LE-LABEL: fromRegsConvftoui:
3013 ; P8LE: # %bb.0: # %entry
3014 ; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
3015 ; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4
3016 ; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3
3017 ; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
3018 ; P8LE-NEXT: xxmrghd vs0, vs3, vs1
3019 ; P8LE-NEXT: xxmrghd vs1, vs4, vs2
3020 ; P8LE-NEXT: xvcvdpuxws v2, vs0
3021 ; P8LE-NEXT: xvcvdpuxws v3, vs1
3022 ; P8LE-NEXT: vmrgew v2, v3, v2
3023 ; P8LE-NEXT: blr
3024 entry:
3025 %conv = fptoui float %a to i32
3026 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
3027 %conv1 = fptoui float %b to i32
3028 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1
3029 %conv3 = fptoui float %c to i32
3030 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2
3031 %conv5 = fptoui float %d to i32
3032 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3
3033 ret <4 x i32> %vecinit6
3034 }
3036 ; Function Attrs: norecurse nounwind readnone
3037 define <4 x i32> @fromDiffConstsConvftoui() {
3038 ; P9BE-LABEL: fromDiffConstsConvftoui:
3039 ; P9BE: # %bb.0: # %entry
3040 ; P9BE-NEXT: addis r3, r2, .LCPI50_0@toc@ha
3041 ; P9BE-NEXT: addi r3, r3, .LCPI50_0@toc@l
3042 ; P9BE-NEXT: lxvx v2, 0, r3
3043 ; P9BE-NEXT: blr
3044 ;
3045 ; P9LE-LABEL: fromDiffConstsConvftoui:
3046 ; P9LE: # %bb.0: # %entry
3047 ; P9LE-NEXT: addis r3, r2, .LCPI50_0@toc@ha
3048 ; P9LE-NEXT: addi r3, r3, .LCPI50_0@toc@l
3049 ; P9LE-NEXT: lxvx v2, 0, r3
3050 ; P9LE-NEXT: blr
3051 ;
3052 ; P8BE-LABEL: fromDiffConstsConvftoui:
3053 ; P8BE: # %bb.0: # %entry
3054 ; P8BE-NEXT: addis r3, r2, .LCPI50_0@toc@ha
3055 ; P8BE-NEXT: addi r3, r3, .LCPI50_0@toc@l
3056 ; P8BE-NEXT: lxvw4x v2, 0, r3
3057 ; P8BE-NEXT: blr
3058 ;
3059 ; P8LE-LABEL: fromDiffConstsConvftoui:
3060 ; P8LE: # %bb.0: # %entry
3061 ; P8LE-NEXT: addis r3, r2, .LCPI50_0@toc@ha
3062 ; P8LE-NEXT: addi r3, r3, .LCPI50_0@toc@l
3063 ; P8LE-NEXT: lvx v2, 0, r3
3064 ; P8LE-NEXT: blr
3065 entry:
3066 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422>
3067 }
3069 ; Function Attrs: norecurse nounwind readonly
3070 define <4 x i32> @fromDiffMemConsAConvftoui(float* nocapture readonly %ptr) {
3071 ; P9BE-LABEL: fromDiffMemConsAConvftoui:
3072 ; P9BE: # %bb.0: # %entry
3073 ; P9BE-NEXT: lxv vs0, 0(r3)
3074 ; P9BE-NEXT: xvcvspuxws v2, vs0
3075 ; P9BE-NEXT: blr
3076 ;
3077 ; P9LE-LABEL: fromDiffMemConsAConvftoui:
3078 ; P9LE: # %bb.0: # %entry
3079 ; P9LE-NEXT: lxv vs0, 0(r3)
3080 ; P9LE-NEXT: xvcvspuxws v2, vs0
3081 ; P9LE-NEXT: blr
3082 ;
3083 ; P8BE-LABEL: fromDiffMemConsAConvftoui:
3084 ; P8BE: # %bb.0: # %entry
3085 ; P8BE-NEXT: lxvw4x vs0, 0, r3
3086 ; P8BE-NEXT: xvcvspuxws v2, vs0
3087 ; P8BE-NEXT: blr
3088 ;
3089 ; P8LE-LABEL: fromDiffMemConsAConvftoui:
3090 ; P8LE: # %bb.0: # %entry
3091 ; P8LE-NEXT: lxvd2x vs0, 0, r3
3092 ; P8LE-NEXT: xxswapd v2, vs0
3093 ; P8LE-NEXT: xvcvspuxws v2, v2
3094 ; P8LE-NEXT: blr
3095 entry:
3096 %0 = bitcast float* %ptr to <4 x float>*
3097 %1 = load <4 x float>, <4 x float>* %0, align 4
3098 %2 = fptoui <4 x float> %1 to <4 x i32>
3099 ret <4 x i32> %2
3100 }
3102 ; Function Attrs: norecurse nounwind readonly
3103 define <4 x i32> @fromDiffMemConsDConvftoui(float* nocapture readonly %ptr) {
3104 ; P9BE-LABEL: fromDiffMemConsDConvftoui:
3105 ; P9BE: # %bb.0: # %entry
3106 ; P9BE-NEXT: lxv v2, 0(r3)
3107 ; P9BE-NEXT: addis r3, r2, .LCPI52_0@toc@ha
3108 ; P9BE-NEXT: addi r3, r3, .LCPI52_0@toc@l
3109 ; P9BE-NEXT: lxvx v3, 0, r3
3110 ; P9BE-NEXT: vperm v2, v2, v2, v3
3111 ; P9BE-NEXT: xvcvspuxws v2, v2
3112 ; P9BE-NEXT: blr
3113 ;
3114 ; P9LE-LABEL: fromDiffMemConsDConvftoui:
3115 ; P9LE: # %bb.0: # %entry
3116 ; P9LE-NEXT: lxv v2, 0(r3)
3117 ; P9LE-NEXT: addis r3, r2, .LCPI52_0@toc@ha
3118 ; P9LE-NEXT: addi r3, r3, .LCPI52_0@toc@l
3119 ; P9LE-NEXT: lxvx v3, 0, r3
3120 ; P9LE-NEXT: vperm v2, v2, v2, v3
3121 ; P9LE-NEXT: xvcvspuxws v2, v2
3122 ; P9LE-NEXT: blr
3123 ;
3124 ; P8BE-LABEL: fromDiffMemConsDConvftoui:
3125 ; P8BE: # %bb.0: # %entry
3126 ; P8BE-NEXT: addis r4, r2, .LCPI52_0@toc@ha
3127 ; P8BE-NEXT: lxvw4x v2, 0, r3
3128 ; P8BE-NEXT: addi r4, r4, .LCPI52_0@toc@l
3129 ; P8BE-NEXT: lxvw4x v3, 0, r4
3130 ; P8BE-NEXT: vperm v2, v2, v2, v3
3131 ; P8BE-NEXT: xvcvspuxws v2, v2
3132 ; P8BE-NEXT: blr
3133 ;
3134 ; P8LE-LABEL: fromDiffMemConsDConvftoui:
3135 ; P8LE: # %bb.0: # %entry
3136 ; P8LE-NEXT: lxvd2x vs0, 0, r3
3137 ; P8LE-NEXT: addis r4, r2, .LCPI52_0@toc@ha
3138 ; P8LE-NEXT: addi r3, r4, .LCPI52_0@toc@l
3139 ; P8LE-NEXT: lvx v2, 0, r3
3140 ; P8LE-NEXT: xxswapd v3, vs0
3141 ; P8LE-NEXT: vperm v2, v3, v3, v2
3142 ; P8LE-NEXT: xvcvspuxws v2, v2
3143 ; P8LE-NEXT: blr
3144 entry:
3145 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3
3146 %0 = load float, float* %arrayidx, align 4
3147 %conv = fptoui float %0 to i32
3148 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
3149 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2
3150 %1 = load float, float* %arrayidx1, align 4
3151 %conv2 = fptoui float %1 to i32
3152 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
3153 %arrayidx4 = getelementptr inbounds float, float* %ptr, i64 1
3154 %2 = load float, float* %arrayidx4, align 4
3155 %conv5 = fptoui float %2 to i32
3156 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
3157 %3 = load float, float* %ptr, align 4
3158 %conv8 = fptoui float %3 to i32
3159 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
3160 ret <4 x i32> %vecinit9
3161 }
3163 ; Function Attrs: norecurse nounwind readonly
3164 define <4 x i32> @fromDiffMemVarAConvftoui(float* nocapture readonly %arr, i32 signext %elem) {
3165 ; P9BE-LABEL: fromDiffMemVarAConvftoui:
3166 ; P9BE: # %bb.0: # %entry
3167 ; P9BE-NEXT: sldi r4, r4, 2
3168 ; P9BE-NEXT: lfsux f0, r3, r4
3169 ; P9BE-NEXT: lfs f1, 12(r3)
3170 ; P9BE-NEXT: lfs f2, 4(r3)
3171 ; P9BE-NEXT: xxmrghd vs1, vs2, vs1
3172 ; P9BE-NEXT: xvcvdpsp v2, vs1
3173 ; P9BE-NEXT: lfs f1, 8(r3)
3174 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
3175 ; P9BE-NEXT: xvcvdpsp v3, vs0
3176 ; P9BE-NEXT: vmrgew v2, v3, v2
3177 ; P9BE-NEXT: xvcvspuxws v2, v2
3178 ; P9BE-NEXT: blr
3179 ;
3180 ; P9LE-LABEL: fromDiffMemVarAConvftoui:
3181 ; P9LE: # %bb.0: # %entry
3182 ; P9LE-NEXT: sldi r4, r4, 2
3183 ; P9LE-NEXT: lfsux f0, r3, r4
3184 ; P9LE-NEXT: lfs f1, 8(r3)
3185 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
3186 ; P9LE-NEXT: lfs f1, 12(r3)
3187 ; P9LE-NEXT: xvcvdpsp v2, vs0
3188 ; P9LE-NEXT: lfs f0, 4(r3)
3189 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
3190 ; P9LE-NEXT: xvcvdpsp v3, vs0
3191 ; P9LE-NEXT: vmrgew v2, v3, v2
3192 ; P9LE-NEXT: xvcvspuxws v2, v2
3193 ; P9LE-NEXT: blr
3194 ;
3195 ; P8BE-LABEL: fromDiffMemVarAConvftoui:
3196 ; P8BE: # %bb.0: # %entry
3197 ; P8BE-NEXT: sldi r4, r4, 2
3198 ; P8BE-NEXT: lfsux f0, r3, r4
3199 ; P8BE-NEXT: lfs f1, 12(r3)
3200 ; P8BE-NEXT: lfs f2, 4(r3)
3201 ; P8BE-NEXT: lfs f3, 8(r3)
3202 ; P8BE-NEXT: xxmrghd vs1, vs2, vs1
3203 ; P8BE-NEXT: xxmrghd vs0, vs0, vs3
3204 ; P8BE-NEXT: xvcvdpsp v2, vs1
3205 ; P8BE-NEXT: xvcvdpsp v3, vs0
3206 ; P8BE-NEXT: vmrgew v2, v3, v2
3207 ; P8BE-NEXT: xvcvspuxws v2, v2
3208 ; P8BE-NEXT: blr
3209 ;
3210 ; P8LE-LABEL: fromDiffMemVarAConvftoui:
3211 ; P8LE: # %bb.0: # %entry
3212 ; P8LE-NEXT: sldi r4, r4, 2
3213 ; P8LE-NEXT: lfsux f0, r3, r4
3214 ; P8LE-NEXT: lfs f1, 8(r3)
3215 ; P8LE-NEXT: lfs f2, 4(r3)
3216 ; P8LE-NEXT: lfs f3, 12(r3)
3217 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
3218 ; P8LE-NEXT: xxmrghd vs1, vs3, vs2
3219 ; P8LE-NEXT: xvcvdpsp v2, vs0
3220 ; P8LE-NEXT: xvcvdpsp v3, vs1
3221 ; P8LE-NEXT: vmrgew v2, v3, v2
3222 ; P8LE-NEXT: xvcvspuxws v2, v2
3223 ; P8LE-NEXT: blr
3224 entry:
3225 %idxprom = sext i32 %elem to i64
3226 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom
3227 %0 = load float, float* %arrayidx, align 4
3228 %conv = fptoui float %0 to i32
3229 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
3230 %add = add nsw i32 %elem, 1
3231 %idxprom1 = sext i32 %add to i64
3232 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1
3233 %1 = load float, float* %arrayidx2, align 4
3234 %conv3 = fptoui float %1 to i32
3235 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
3236 %add5 = add nsw i32 %elem, 2
3237 %idxprom6 = sext i32 %add5 to i64
3238 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6
3239 %2 = load float, float* %arrayidx7, align 4
3240 %conv8 = fptoui float %2 to i32
3241 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
3242 %add10 = add nsw i32 %elem, 3
3243 %idxprom11 = sext i32 %add10 to i64
3244 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11
3245 %3 = load float, float* %arrayidx12, align 4
3246 %conv13 = fptoui float %3 to i32
3247 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
3248 ret <4 x i32> %vecinit14
3249 ; FIXME: implement finding consecutive loads with pre-inc
3250 }
3252 ; Function Attrs: norecurse nounwind readonly
3253 define <4 x i32> @fromDiffMemVarDConvftoui(float* nocapture readonly %arr, i32 signext %elem) {
3254 ; P9BE-LABEL: fromDiffMemVarDConvftoui:
3255 ; P9BE: # %bb.0: # %entry
3256 ; P9BE-NEXT: sldi r4, r4, 2
3257 ; P9BE-NEXT: lfsux f0, r3, r4
3258 ; P9BE-NEXT: lfs f1, -12(r3)
3259 ; P9BE-NEXT: lfs f2, -4(r3)
3260 ; P9BE-NEXT: xxmrghd vs1, vs2, vs1
3261 ; P9BE-NEXT: xvcvdpsp v2, vs1
3262 ; P9BE-NEXT: lfs f1, -8(r3)
3263 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
3264 ; P9BE-NEXT: xvcvdpsp v3, vs0
3265 ; P9BE-NEXT: vmrgew v2, v3, v2
3266 ; P9BE-NEXT: xvcvspuxws v2, v2
3267 ; P9BE-NEXT: blr
3268 ;
3269 ; P9LE-LABEL: fromDiffMemVarDConvftoui:
3270 ; P9LE: # %bb.0: # %entry
3271 ; P9LE-NEXT: sldi r4, r4, 2
3272 ; P9LE-NEXT: lfsux f0, r3, r4
3273 ; P9LE-NEXT: lfs f1, -8(r3)
3274 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
3275 ; P9LE-NEXT: lfs f1, -12(r3)
3276 ; P9LE-NEXT: xvcvdpsp v2, vs0
3277 ; P9LE-NEXT: lfs f0, -4(r3)
3278 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
3279 ; P9LE-NEXT: xvcvdpsp v3, vs0
3280 ; P9LE-NEXT: vmrgew v2, v3, v2
3281 ; P9LE-NEXT: xvcvspuxws v2, v2
3282 ; P9LE-NEXT: blr
3283 ;
3284 ; P8BE-LABEL: fromDiffMemVarDConvftoui:
3285 ; P8BE: # %bb.0: # %entry
3286 ; P8BE-NEXT: sldi r4, r4, 2
3287 ; P8BE-NEXT: lfsux f0, r3, r4
3288 ; P8BE-NEXT: lfs f1, -12(r3)
3289 ; P8BE-NEXT: lfs f2, -4(r3)
3290 ; P8BE-NEXT: lfs f3, -8(r3)
3291 ; P8BE-NEXT: xxmrghd vs1, vs2, vs1
3292 ; P8BE-NEXT: xxmrghd vs0, vs0, vs3
3293 ; P8BE-NEXT: xvcvdpsp v2, vs1
3294 ; P8BE-NEXT: xvcvdpsp v3, vs0
3295 ; P8BE-NEXT: vmrgew v2, v3, v2
3296 ; P8BE-NEXT: xvcvspuxws v2, v2
3297 ; P8BE-NEXT: blr
3298 ;
3299 ; P8LE-LABEL: fromDiffMemVarDConvftoui:
3300 ; P8LE: # %bb.0: # %entry
3301 ; P8LE-NEXT: sldi r4, r4, 2
3302 ; P8LE-NEXT: lfsux f0, r3, r4
3303 ; P8LE-NEXT: lfs f1, -8(r3)
3304 ; P8LE-NEXT: lfs f2, -4(r3)
3305 ; P8LE-NEXT: lfs f3, -12(r3)
3306 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
3307 ; P8LE-NEXT: xxmrghd vs1, vs3, vs2
3308 ; P8LE-NEXT: xvcvdpsp v2, vs0
3309 ; P8LE-NEXT: xvcvdpsp v3, vs1
3310 ; P8LE-NEXT: vmrgew v2, v3, v2
3311 ; P8LE-NEXT: xvcvspuxws v2, v2
3312 ; P8LE-NEXT: blr
3313 entry:
3314 %idxprom = sext i32 %elem to i64
3315 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom
3316 %0 = load float, float* %arrayidx, align 4
3317 %conv = fptoui float %0 to i32
3318 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
3319 %sub = add nsw i32 %elem, -1
3320 %idxprom1 = sext i32 %sub to i64
3321 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1
3322 %1 = load float, float* %arrayidx2, align 4
3323 %conv3 = fptoui float %1 to i32
3324 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
3325 %sub5 = add nsw i32 %elem, -2
3326 %idxprom6 = sext i32 %sub5 to i64
3327 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6
3328 %2 = load float, float* %arrayidx7, align 4
3329 %conv8 = fptoui float %2 to i32
3330 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
3331 %sub10 = add nsw i32 %elem, -3
3332 %idxprom11 = sext i32 %sub10 to i64
3333 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11
3334 %3 = load float, float* %arrayidx12, align 4
3335 %conv13 = fptoui float %3 to i32
3336 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
3337 ret <4 x i32> %vecinit14
3338 ; FIXME: implement finding consecutive loads with pre-inc
3339 }
3341 ; Function Attrs: norecurse nounwind readnone
3342 define <4 x i32> @spltRegValConvftoui(float %val) {
3343 ; P9BE-LABEL: spltRegValConvftoui:
3344 ; P9BE: # %bb.0: # %entry
3345 ; P9BE-NEXT: xscvdpuxws f0, f1
3346 ; P9BE-NEXT: xxspltw v2, vs0, 1
3347 ; P9BE-NEXT: blr
3348 ;
3349 ; P9LE-LABEL: spltRegValConvftoui:
3350 ; P9LE: # %bb.0: # %entry
3351 ; P9LE-NEXT: xscvdpuxws f0, f1
3352 ; P9LE-NEXT: xxspltw v2, vs0, 1
3353 ; P9LE-NEXT: blr
3354 ;
3355 ; P8BE-LABEL: spltRegValConvftoui:
3356 ; P8BE: # %bb.0: # %entry
3357 ; P8BE-NEXT: xscvdpuxws f0, f1
3358 ; P8BE-NEXT: xxspltw v2, vs0, 1
3359 ; P8BE-NEXT: blr
3360 ;
3361 ; P8LE-LABEL: spltRegValConvftoui:
3362 ; P8LE: # %bb.0: # %entry
3363 ; P8LE-NEXT: xscvdpuxws f0, f1
3364 ; P8LE-NEXT: xxspltw v2, vs0, 1
3365 ; P8LE-NEXT: blr
3366 entry:
3367 %conv = fptoui float %val to i32
3368 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
3369 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
3370 ret <4 x i32> %splat.splat
3371 }
3373 ; Function Attrs: norecurse nounwind readonly
3374 define <4 x i32> @spltMemValConvftoui(float* nocapture readonly %ptr) {
3375 ; P9BE-LABEL: spltMemValConvftoui:
3376 ; P9BE: # %bb.0: # %entry
3377 ; P9BE-NEXT: lxvwsx vs0, 0, r3
3378 ; P9BE-NEXT: xvcvspuxws v2, vs0
3379 ; P9BE-NEXT: blr
3380 ;
3381 ; P9LE-LABEL: spltMemValConvftoui:
3382 ; P9LE: # %bb.0: # %entry
3383 ; P9LE-NEXT: lxvwsx vs0, 0, r3
3384 ; P9LE-NEXT: xvcvspuxws v2, vs0
3385 ; P9LE-NEXT: blr
3386 ;
3387 ; P8BE-LABEL: spltMemValConvftoui:
3388 ; P8BE: # %bb.0: # %entry
3389 ; P8BE-NEXT: lfsx f0, 0, r3
3390 ; P8BE-NEXT: xscvdpuxws f0, f0
3391 ; P8BE-NEXT: xxspltw v2, vs0, 1
3392 ; P8BE-NEXT: blr
3393 ;
3394 ; P8LE-LABEL: spltMemValConvftoui:
3395 ; P8LE: # %bb.0: # %entry
3396 ; P8LE-NEXT: lfsx f0, 0, r3
3397 ; P8LE-NEXT: xscvdpuxws f0, f0
3398 ; P8LE-NEXT: xxspltw v2, vs0, 1
3399 ; P8LE-NEXT: blr
3400 entry:
3401 %0 = load float, float* %ptr, align 4
3402 %conv = fptoui float %0 to i32
3403 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
3404 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
3405 ret <4 x i32> %splat.splat
3406 }
3408 ; Function Attrs: norecurse nounwind readnone
3409 define <4 x i32> @spltCnstConvdtoui() {
3410 ; P9BE-LABEL: spltCnstConvdtoui:
3411 ; P9BE: # %bb.0: # %entry
3412 ; P9BE-NEXT: vspltisw v2, 4
3413 ; P9BE-NEXT: blr
3414 ;
3415 ; P9LE-LABEL: spltCnstConvdtoui:
3416 ; P9LE: # %bb.0: # %entry
3417 ; P9LE-NEXT: vspltisw v2, 4
3418 ; P9LE-NEXT: blr
3419 ;
3420 ; P8BE-LABEL: spltCnstConvdtoui:
3421 ; P8BE: # %bb.0: # %entry
3422 ; P8BE-NEXT: vspltisw v2, 4
3423 ; P8BE-NEXT: blr
3424 ;
3425 ; P8LE-LABEL: spltCnstConvdtoui:
3426 ; P8LE: # %bb.0: # %entry
3427 ; P8LE-NEXT: vspltisw v2, 4
3428 ; P8LE-NEXT: blr
3429 entry:
3430 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4>
3431 }
3433 ; Function Attrs: norecurse nounwind readnone
3434 define <4 x i32> @fromRegsConvdtoui(double %a, double %b, double %c, double %d) {
3435 ; P9BE-LABEL: fromRegsConvdtoui:
3436 ; P9BE: # %bb.0: # %entry
3437 ; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4
3438 ; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
3439 ; P9BE-NEXT: xxmrghd vs0, vs2, vs4
3440 ; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3
3441 ; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
3442 ; P9BE-NEXT: xvcvdpuxws v2, vs0
3443 ; P9BE-NEXT: xxmrghd vs0, vs1, vs3
3444 ; P9BE-NEXT: xvcvdpuxws v3, vs0
3445 ; P9BE-NEXT: vmrgew v2, v3, v2
3446 ; P9BE-NEXT: blr
3447 ;
3448 ; P9LE-LABEL: fromRegsConvdtoui:
3449 ; P9LE: # %bb.0: # %entry
3450 ; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3
3451 ; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
3452 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
3453 ; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4
3454 ; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
3455 ; P9LE-NEXT: xvcvdpuxws v2, vs0
3456 ; P9LE-NEXT: xxmrghd vs0, vs4, vs2
3457 ; P9LE-NEXT: xvcvdpuxws v3, vs0
3458 ; P9LE-NEXT: vmrgew v2, v3, v2
3459 ; P9LE-NEXT: blr
3460 ;
3461 ; P8BE-LABEL: fromRegsConvdtoui:
3462 ; P8BE: # %bb.0: # %entry
3463 ; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
3464 ; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4
3465 ; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3
3466 ; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
3467 ; P8BE-NEXT: xxmrghd vs0, vs2, vs4
3468 ; P8BE-NEXT: xxmrghd vs1, vs1, vs3
3469 ; P8BE-NEXT: xvcvdpuxws v2, vs0
3470 ; P8BE-NEXT: xvcvdpuxws v3, vs1
3471 ; P8BE-NEXT: vmrgew v2, v3, v2
3472 ; P8BE-NEXT: blr
3473 ;
3474 ; P8LE-LABEL: fromRegsConvdtoui:
3475 ; P8LE: # %bb.0: # %entry
3476 ; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
3477 ; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4
3478 ; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3
3479 ; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
3480 ; P8LE-NEXT: xxmrghd vs0, vs3, vs1
3481 ; P8LE-NEXT: xxmrghd vs1, vs4, vs2
3482 ; P8LE-NEXT: xvcvdpuxws v2, vs0
3483 ; P8LE-NEXT: xvcvdpuxws v3, vs1
3484 ; P8LE-NEXT: vmrgew v2, v3, v2
3485 ; P8LE-NEXT: blr
3486 entry:
3487 %conv = fptoui double %a to i32
3488 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
3489 %conv1 = fptoui double %b to i32
3490 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1
3491 %conv3 = fptoui double %c to i32
3492 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2
3493 %conv5 = fptoui double %d to i32
3494 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3
3495 ret <4 x i32> %vecinit6
3496 }
3498 ; Function Attrs: norecurse nounwind readnone
3499 define <4 x i32> @fromDiffConstsConvdtoui() {
3500 ; P9BE-LABEL: fromDiffConstsConvdtoui:
3501 ; P9BE: # %bb.0: # %entry
3502 ; P9BE-NEXT: addis r3, r2, .LCPI59_0@toc@ha
3503 ; P9BE-NEXT: addi r3, r3, .LCPI59_0@toc@l
3504 ; P9BE-NEXT: lxvx v2, 0, r3
3505 ; P9BE-NEXT: blr
3506 ;
3507 ; P9LE-LABEL: fromDiffConstsConvdtoui:
3508 ; P9LE: # %bb.0: # %entry
3509 ; P9LE-NEXT: addis r3, r2, .LCPI59_0@toc@ha
3510 ; P9LE-NEXT: addi r3, r3, .LCPI59_0@toc@l
3511 ; P9LE-NEXT: lxvx v2, 0, r3
3512 ; P9LE-NEXT: blr
3513 ;
3514 ; P8BE-LABEL: fromDiffConstsConvdtoui:
3515 ; P8BE: # %bb.0: # %entry
3516 ; P8BE-NEXT: addis r3, r2, .LCPI59_0@toc@ha
3517 ; P8BE-NEXT: addi r3, r3, .LCPI59_0@toc@l
3518 ; P8BE-NEXT: lxvw4x v2, 0, r3
3519 ; P8BE-NEXT: blr
3520 ;
3521 ; P8LE-LABEL: fromDiffConstsConvdtoui:
3522 ; P8LE: # %bb.0: # %entry
3523 ; P8LE-NEXT: addis r3, r2, .LCPI59_0@toc@ha
3524 ; P8LE-NEXT: addi r3, r3, .LCPI59_0@toc@l
3525 ; P8LE-NEXT: lvx v2, 0, r3
3526 ; P8LE-NEXT: blr
3527 entry:
3528 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422>
3529 }
3531 ; Function Attrs: norecurse nounwind readonly
3532 define <4 x i32> @fromDiffMemConsAConvdtoui(double* nocapture readonly %ptr) {
3533 ; P9BE-LABEL: fromDiffMemConsAConvdtoui:
3534 ; P9BE: # %bb.0: # %entry
3535 ; P9BE-NEXT: lxv vs0, 0(r3)
3536 ; P9BE-NEXT: lxv vs1, 16(r3)
3537 ; P9BE-NEXT: xxmrgld vs2, vs0, vs1
3538 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
3539 ; P9BE-NEXT: xvcvdpuxws v2, vs2
3540 ; P9BE-NEXT: xvcvdpuxws v3, vs0
3541 ; P9BE-NEXT: vmrgew v2, v3, v2
3542 ; P9BE-NEXT: blr
3543 ;
3544 ; P9LE-LABEL: fromDiffMemConsAConvdtoui:
3545 ; P9LE: # %bb.0: # %entry
3546 ; P9LE-NEXT: lxv vs0, 0(r3)
3547 ; P9LE-NEXT: lxv vs1, 16(r3)
3548 ; P9LE-NEXT: xxmrgld vs2, vs1, vs0
3549 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
3550 ; P9LE-NEXT: xvcvdpuxws v2, vs2
3551 ; P9LE-NEXT: xvcvdpuxws v3, vs0
3552 ; P9LE-NEXT: vmrgew v2, v3, v2
3553 ; P9LE-NEXT: blr
3554 ;
3555 ; P8BE-LABEL: fromDiffMemConsAConvdtoui:
3556 ; P8BE: # %bb.0: # %entry
3557 ; P8BE-NEXT: li r4, 16
3558 ; P8BE-NEXT: lxvd2x vs0, 0, r3
3559 ; P8BE-NEXT: lxvd2x vs1, r3, r4
3560 ; P8BE-NEXT: xxmrgld vs2, vs0, vs1
3561 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
3562 ; P8BE-NEXT: xvcvdpuxws v2, vs2
3563 ; P8BE-NEXT: xvcvdpuxws v3, vs0
3564 ; P8BE-NEXT: vmrgew v2, v3, v2
3565 ; P8BE-NEXT: blr
3566 ;
3567 ; P8LE-LABEL: fromDiffMemConsAConvdtoui:
3568 ; P8LE: # %bb.0: # %entry
3569 ; P8LE-NEXT: li r4, 16
3570 ; P8LE-NEXT: lxvd2x vs0, 0, r3
3571 ; P8LE-NEXT: lxvd2x vs1, r3, r4
3572 ; P8LE-NEXT: xxswapd vs0, vs0
3573 ; P8LE-NEXT: xxswapd vs1, vs1
3574 ; P8LE-NEXT: xxmrgld vs2, vs1, vs0
3575 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
3576 ; P8LE-NEXT: xvcvdpuxws v2, vs2
3577 ; P8LE-NEXT: xvcvdpuxws v3, vs0
3578 ; P8LE-NEXT: vmrgew v2, v3, v2
3579 ; P8LE-NEXT: blr
3580 entry:
3581 %0 = bitcast double* %ptr to <2 x double>*
3582 %1 = load <2 x double>, <2 x double>* %0, align 8
3583 %2 = fptoui <2 x double> %1 to <2 x i32>
3584 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 2
3585 %3 = bitcast double* %arrayidx4 to <2 x double>*
3586 %4 = load <2 x double>, <2 x double>* %3, align 8
3587 %5 = fptoui <2 x double> %4 to <2 x i32>
3588 %vecinit9 = shufflevector <2 x i32> %2, <2 x i32> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
3589 ret <4 x i32> %vecinit9
3590 }
3592 ; Function Attrs: norecurse nounwind readonly
3593 define <4 x i32> @fromDiffMemConsDConvdtoui(double* nocapture readonly %ptr) {
3594 ; P9BE-LABEL: fromDiffMemConsDConvdtoui:
3595 ; P9BE: # %bb.0: # %entry
3596 ; P9BE-NEXT: lfd f0, 24(r3)
3597 ; P9BE-NEXT: lfd f1, 16(r3)
3598 ; P9BE-NEXT: lfd f2, 8(r3)
3599 ; P9BE-NEXT: xxmrghd vs0, vs0, vs2
3600 ; P9BE-NEXT: lfd f3, 0(r3)
3601 ; P9BE-NEXT: xxmrghd vs1, vs1, vs3
3602 ; P9BE-NEXT: xvcvdpuxws v2, vs1
3603 ; P9BE-NEXT: xvcvdpuxws v3, vs0
3604 ; P9BE-NEXT: vmrgew v2, v3, v2
3605 ; P9BE-NEXT: blr
3606 ;
3607 ; P9LE-LABEL: fromDiffMemConsDConvdtoui:
3608 ; P9LE: # %bb.0: # %entry
3609 ; P9LE-NEXT: lfd f0, 24(r3)
3610 ; P9LE-NEXT: lfd f2, 8(r3)
3611 ; P9LE-NEXT: xxmrghd vs0, vs2, vs0
3612 ; P9LE-NEXT: lfd f1, 16(r3)
3613 ; P9LE-NEXT: lfd f3, 0(r3)
3614 ; P9LE-NEXT: xvcvdpuxws v2, vs0
3615 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
3616 ; P9LE-NEXT: xvcvdpuxws v3, vs0
3617 ; P9LE-NEXT: vmrgew v2, v3, v2
3618 ; P9LE-NEXT: blr
3619 ;
3620 ; P8BE-LABEL: fromDiffMemConsDConvdtoui:
3621 ; P8BE: # %bb.0: # %entry
3622 ; P8BE-NEXT: lfdx f3, 0, r3
3623 ; P8BE-NEXT: lfd f0, 24(r3)
3624 ; P8BE-NEXT: lfd f1, 8(r3)
3625 ; P8BE-NEXT: lfd f2, 16(r3)
3626 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
3627 ; P8BE-NEXT: xxmrghd vs1, vs2, vs3
3628 ; P8BE-NEXT: xvcvdpuxws v2, vs0
3629 ; P8BE-NEXT: xvcvdpuxws v3, vs1
3630 ; P8BE-NEXT: vmrgew v2, v2, v3
3631 ; P8BE-NEXT: blr
3632 ;
3633 ; P8LE-LABEL: fromDiffMemConsDConvdtoui:
3634 ; P8LE: # %bb.0: # %entry
3635 ; P8LE-NEXT: lfdx f3, 0, r3
3636 ; P8LE-NEXT: lfd f0, 24(r3)
3637 ; P8LE-NEXT: lfd f1, 8(r3)
3638 ; P8LE-NEXT: lfd f2, 16(r3)
3639 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
3640 ; P8LE-NEXT: xxmrghd vs1, vs3, vs2
3641 ; P8LE-NEXT: xvcvdpuxws v2, vs0
3642 ; P8LE-NEXT: xvcvdpuxws v3, vs1
3643 ; P8LE-NEXT: vmrgew v2, v3, v2
3644 ; P8LE-NEXT: blr
3645 entry:
3646 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3
3647 %0 = load double, double* %arrayidx, align 8
3648 %conv = fptoui double %0 to i32
3649 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
3650 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2
3651 %1 = load double, double* %arrayidx1, align 8
3652 %conv2 = fptoui double %1 to i32
3653 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
3654 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 1
3655 %2 = load double, double* %arrayidx4, align 8
3656 %conv5 = fptoui double %2 to i32
3657 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
3658 %3 = load double, double* %ptr, align 8
3659 %conv8 = fptoui double %3 to i32
3660 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
3661 ret <4 x i32> %vecinit9
3662 }
3664 ; Function Attrs: norecurse nounwind readonly
3665 define <4 x i32> @fromDiffMemVarAConvdtoui(double* nocapture readonly %arr, i32 signext %elem) {
3666 ; P9BE-LABEL: fromDiffMemVarAConvdtoui:
3667 ; P9BE: # %bb.0: # %entry
3668 ; P9BE-NEXT: sldi r4, r4, 3
3669 ; P9BE-NEXT: lfdux f0, r3, r4
3670 ; P9BE-NEXT: lfd f1, 8(r3)
3671 ; P9BE-NEXT: lfd f2, 16(r3)
3672 ; P9BE-NEXT: lfd f3, 24(r3)
3673 ; P9BE-NEXT: xxmrghd vs1, vs1, vs3
3674 ; P9BE-NEXT: xxmrghd vs0, vs0, vs2
3675 ; P9BE-NEXT: xvcvdpuxws v2, vs1
3676 ; P9BE-NEXT: xvcvdpuxws v3, vs0
3677 ; P9BE-NEXT: vmrgew v2, v3, v2
3678 ; P9BE-NEXT: blr
3679 ;
3680 ; P9LE-LABEL: fromDiffMemVarAConvdtoui:
3681 ; P9LE: # %bb.0: # %entry
3682 ; P9LE-NEXT: sldi r4, r4, 3
3683 ; P9LE-NEXT: lfdux f0, r3, r4
3684 ; P9LE-NEXT: lfd f2, 16(r3)
3685 ; P9LE-NEXT: lfd f1, 8(r3)
3686 ; P9LE-NEXT: lfd f3, 24(r3)
3687 ; P9LE-NEXT: xxmrghd vs0, vs2, vs0
3688 ; P9LE-NEXT: xvcvdpuxws v2, vs0
3689 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
3690 ; P9LE-NEXT: xvcvdpuxws v3, vs0
3691 ; P9LE-NEXT: vmrgew v2, v3, v2
3692 ; P9LE-NEXT: blr
3693 ;
3694 ; P8BE-LABEL: fromDiffMemVarAConvdtoui:
3695 ; P8BE: # %bb.0: # %entry
3696 ; P8BE-NEXT: sldi r4, r4, 3
3697 ; P8BE-NEXT: lfdux f0, r3, r4
3698 ; P8BE-NEXT: lfd f1, 8(r3)
3699 ; P8BE-NEXT: lfd f2, 24(r3)
3700 ; P8BE-NEXT: lfd f3, 16(r3)
3701 ; P8BE-NEXT: xxmrghd vs1, vs1, vs2
3702 ; P8BE-NEXT: xxmrghd vs0, vs0, vs3
3703 ; P8BE-NEXT: xvcvdpuxws v2, vs1
3704 ; P8BE-NEXT: xvcvdpuxws v3, vs0
3705 ; P8BE-NEXT: vmrgew v2, v3, v2
3706 ; P8BE-NEXT: blr
3707 ;
3708 ; P8LE-LABEL: fromDiffMemVarAConvdtoui:
3709 ; P8LE: # %bb.0: # %entry
3710 ; P8LE-NEXT: sldi r4, r4, 3
3711 ; P8LE-NEXT: lfdux f0, r3, r4
3712 ; P8LE-NEXT: lfd f1, 16(r3)
3713 ; P8LE-NEXT: lfd f2, 8(r3)
3714 ; P8LE-NEXT: lfd f3, 24(r3)
3715 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
3716 ; P8LE-NEXT: xxmrghd vs1, vs3, vs2
3717 ; P8LE-NEXT: xvcvdpuxws v2, vs0
3718 ; P8LE-NEXT: xvcvdpuxws v3, vs1
3719 ; P8LE-NEXT: vmrgew v2, v3, v2
3720 ; P8LE-NEXT: blr
3721 entry:
3722 %idxprom = sext i32 %elem to i64
3723 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom
3724 %0 = load double, double* %arrayidx, align 8
3725 %conv = fptoui double %0 to i32
3726 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
3727 %add = add nsw i32 %elem, 1
3728 %idxprom1 = sext i32 %add to i64
3729 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1
3730 %1 = load double, double* %arrayidx2, align 8
3731 %conv3 = fptoui double %1 to i32
3732 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
3733 %add5 = add nsw i32 %elem, 2
3734 %idxprom6 = sext i32 %add5 to i64
3735 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6
3736 %2 = load double, double* %arrayidx7, align 8
3737 %conv8 = fptoui double %2 to i32
3738 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
3739 %add10 = add nsw i32 %elem, 3
3740 %idxprom11 = sext i32 %add10 to i64
3741 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11
3742 %3 = load double, double* %arrayidx12, align 8
3743 %conv13 = fptoui double %3 to i32
3744 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
3745 ret <4 x i32> %vecinit14
3746 }
3748 ; Function Attrs: norecurse nounwind readonly
3749 define <4 x i32> @fromDiffMemVarDConvdtoui(double* nocapture readonly %arr, i32 signext %elem) {
3750 ; P9BE-LABEL: fromDiffMemVarDConvdtoui:
3751 ; P9BE: # %bb.0: # %entry
3752 ; P9BE-NEXT: sldi r4, r4, 3
3753 ; P9BE-NEXT: lfdux f0, r3, r4
3754 ; P9BE-NEXT: lfd f1, -8(r3)
3755 ; P9BE-NEXT: lfd f2, -16(r3)
3756 ; P9BE-NEXT: lfd f3, -24(r3)
3757 ; P9BE-NEXT: xxmrghd vs1, vs1, vs3
3758 ; P9BE-NEXT: xxmrghd vs0, vs0, vs2
3759 ; P9BE-NEXT: xvcvdpuxws v2, vs1
3760 ; P9BE-NEXT: xvcvdpuxws v3, vs0
3761 ; P9BE-NEXT: vmrgew v2, v3, v2
3762 ; P9BE-NEXT: blr
3763 ;
3764 ; P9LE-LABEL: fromDiffMemVarDConvdtoui:
3765 ; P9LE: # %bb.0: # %entry
3766 ; P9LE-NEXT: sldi r4, r4, 3
3767 ; P9LE-NEXT: lfdux f0, r3, r4
3768 ; P9LE-NEXT: lfd f2, -16(r3)
3769 ; P9LE-NEXT: lfd f1, -8(r3)
3770 ; P9LE-NEXT: lfd f3, -24(r3)
3771 ; P9LE-NEXT: xxmrghd vs0, vs2, vs0
3772 ; P9LE-NEXT: xvcvdpuxws v2, vs0
3773 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
3774 ; P9LE-NEXT: xvcvdpuxws v3, vs0
3775 ; P9LE-NEXT: vmrgew v2, v3, v2
3776 ; P9LE-NEXT: blr
3777 ;
3778 ; P8BE-LABEL: fromDiffMemVarDConvdtoui:
3779 ; P8BE: # %bb.0: # %entry
3780 ; P8BE-NEXT: sldi r4, r4, 3
3781 ; P8BE-NEXT: lfdux f0, r3, r4
3782 ; P8BE-NEXT: lfd f1, -8(r3)
3783 ; P8BE-NEXT: lfd f2, -24(r3)
3784 ; P8BE-NEXT: lfd f3, -16(r3)
3785 ; P8BE-NEXT: xxmrghd vs1, vs1, vs2
3786 ; P8BE-NEXT: xxmrghd vs0, vs0, vs3
3787 ; P8BE-NEXT: xvcvdpuxws v2, vs1
3788 ; P8BE-NEXT: xvcvdpuxws v3, vs0
3789 ; P8BE-NEXT: vmrgew v2, v3, v2
3790 ; P8BE-NEXT: blr
3791 ;
3792 ; P8LE-LABEL: fromDiffMemVarDConvdtoui:
3793 ; P8LE: # %bb.0: # %entry
3794 ; P8LE-NEXT: sldi r4, r4, 3
3795 ; P8LE-NEXT: lfdux f0, r3, r4
3796 ; P8LE-NEXT: lfd f1, -16(r3)
3797 ; P8LE-NEXT: lfd f2, -8(r3)
3798 ; P8LE-NEXT: lfd f3, -24(r3)
3799 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
3800 ; P8LE-NEXT: xxmrghd vs1, vs3, vs2
3801 ; P8LE-NEXT: xvcvdpuxws v2, vs0
3802 ; P8LE-NEXT: xvcvdpuxws v3, vs1
3803 ; P8LE-NEXT: vmrgew v2, v3, v2
3804 ; P8LE-NEXT: blr
3805 entry:
3806 %idxprom = sext i32 %elem to i64
3807 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom
3808 %0 = load double, double* %arrayidx, align 8
3809 %conv = fptoui double %0 to i32
3810 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
3811 %sub = add nsw i32 %elem, -1
3812 %idxprom1 = sext i32 %sub to i64
3813 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1
3814 %1 = load double, double* %arrayidx2, align 8
3815 %conv3 = fptoui double %1 to i32
3816 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
3817 %sub5 = add nsw i32 %elem, -2
3818 %idxprom6 = sext i32 %sub5 to i64
3819 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6
3820 %2 = load double, double* %arrayidx7, align 8
3821 %conv8 = fptoui double %2 to i32
3822 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
3823 %sub10 = add nsw i32 %elem, -3
3824 %idxprom11 = sext i32 %sub10 to i64
3825 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11
3826 %3 = load double, double* %arrayidx12, align 8
3827 %conv13 = fptoui double %3 to i32
3828 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
3829 ret <4 x i32> %vecinit14
3830 }
3832 ; Function Attrs: norecurse nounwind readnone
3833 define <4 x i32> @spltRegValConvdtoui(double %val) {
3834 ; P9BE-LABEL: spltRegValConvdtoui:
3835 ; P9BE: # %bb.0: # %entry
3836 ; P9BE-NEXT: xscvdpuxws f0, f1
3837 ; P9BE-NEXT: xxspltw v2, vs0, 1
3838 ; P9BE-NEXT: blr
3839 ;
3840 ; P9LE-LABEL: spltRegValConvdtoui:
3841 ; P9LE: # %bb.0: # %entry
3842 ; P9LE-NEXT: xscvdpuxws f0, f1
3843 ; P9LE-NEXT: xxspltw v2, vs0, 1
3844 ; P9LE-NEXT: blr
3845 ;
3846 ; P8BE-LABEL: spltRegValConvdtoui:
3847 ; P8BE: # %bb.0: # %entry
3848 ; P8BE-NEXT: xscvdpuxws f0, f1
3849 ; P8BE-NEXT: xxspltw v2, vs0, 1
3850 ; P8BE-NEXT: blr
3851 ;
3852 ; P8LE-LABEL: spltRegValConvdtoui:
3853 ; P8LE: # %bb.0: # %entry
3854 ; P8LE-NEXT: xscvdpuxws f0, f1
3855 ; P8LE-NEXT: xxspltw v2, vs0, 1
3856 ; P8LE-NEXT: blr
3857 entry:
3858 %conv = fptoui double %val to i32
3859 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
3860 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
3861 ret <4 x i32> %splat.splat
3862 }
3864 ; Function Attrs: norecurse nounwind readonly
3865 define <4 x i32> @spltMemValConvdtoui(double* nocapture readonly %ptr) {
3866 ; P9BE-LABEL: spltMemValConvdtoui:
3867 ; P9BE: # %bb.0: # %entry
3868 ; P9BE-NEXT: lfd f0, 0(r3)
3869 ; P9BE-NEXT: xscvdpuxws f0, f0
3870 ; P9BE-NEXT: xxspltw v2, vs0, 1
3871 ; P9BE-NEXT: blr
3872 ;
3873 ; P9LE-LABEL: spltMemValConvdtoui:
3874 ; P9LE: # %bb.0: # %entry
3875 ; P9LE-NEXT: lfd f0, 0(r3)
3876 ; P9LE-NEXT: xscvdpuxws f0, f0
3877 ; P9LE-NEXT: xxspltw v2, vs0, 1
3878 ; P9LE-NEXT: blr
3879 ;
3880 ; P8BE-LABEL: spltMemValConvdtoui:
3881 ; P8BE: # %bb.0: # %entry
3882 ; P8BE-NEXT: lfdx f0, 0, r3
3883 ; P8BE-NEXT: xscvdpuxws f0, f0
3884 ; P8BE-NEXT: xxspltw v2, vs0, 1
3885 ; P8BE-NEXT: blr
3886 ;
3887 ; P8LE-LABEL: spltMemValConvdtoui:
3888 ; P8LE: # %bb.0: # %entry
3889 ; P8LE-NEXT: lfdx f0, 0, r3
3890 ; P8LE-NEXT: xscvdpuxws f0, f0
3891 ; P8LE-NEXT: xxspltw v2, vs0, 1
3892 ; P8LE-NEXT: blr
3893 entry:
3894 %0 = load double, double* %ptr, align 8
3895 %conv = fptoui double %0 to i32
3896 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
3897 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
3898 ret <4 x i32> %splat.splat
3899 }
3900 ; Function Attrs: norecurse nounwind readnone
3901 define <2 x i64> @allZeroll() {
3902 ; P9BE-LABEL: allZeroll:
3903 ; P9BE: # %bb.0: # %entry
3904 ; P9BE-NEXT: xxlxor v2, v2, v2
3905 ; P9BE-NEXT: blr
3906 ;
3907 ; P9LE-LABEL: allZeroll:
3908 ; P9LE: # %bb.0: # %entry
3909 ; P9LE-NEXT: xxlxor v2, v2, v2
3910 ; P9LE-NEXT: blr
3911 ;
3912 ; P8BE-LABEL: allZeroll:
3913 ; P8BE: # %bb.0: # %entry
3914 ; P8BE-NEXT: xxlxor v2, v2, v2
3915 ; P8BE-NEXT: blr
3916 ;
3917 ; P8LE-LABEL: allZeroll:
3918 ; P8LE: # %bb.0: # %entry
3919 ; P8LE-NEXT: xxlxor v2, v2, v2
3920 ; P8LE-NEXT: blr
3921 entry:
3922 ret <2 x i64> zeroinitializer
3923 }
3925 ; Function Attrs: norecurse nounwind readnone
3926 define <2 x i64> @allOnell() {
3927 ; P9BE-LABEL: allOnell:
3928 ; P9BE: # %bb.0: # %entry
3929 ; P9BE-NEXT: xxspltib v2, 255
3930 ; P9BE-NEXT: blr
3931 ;
3932 ; P9LE-LABEL: allOnell:
3933 ; P9LE: # %bb.0: # %entry
3934 ; P9LE-NEXT: xxspltib v2, 255
3935 ; P9LE-NEXT: blr
3936 ;
3937 ; P8BE-LABEL: allOnell:
3938 ; P8BE: # %bb.0: # %entry
3939 ; P8BE-NEXT: vspltisb v2, -1
3940 ; P8BE-NEXT: blr
3941 ;
3942 ; P8LE-LABEL: allOnell:
3943 ; P8LE: # %bb.0: # %entry
3944 ; P8LE-NEXT: vspltisb v2, -1
3945 ; P8LE-NEXT: blr
3946 entry:
3947 ret <2 x i64> <i64 -1, i64 -1>
3948 }
3950 ; Function Attrs: norecurse nounwind readnone
3951 define <2 x i64> @spltConst1ll() {
3952 ; P9BE-LABEL: spltConst1ll:
3953 ; P9BE: # %bb.0: # %entry
3954 ; P9BE-NEXT: addis r3, r2, .LCPI68_0@toc@ha
3955 ; P9BE-NEXT: addi r3, r3, .LCPI68_0@toc@l
3956 ; P9BE-NEXT: lxvx v2, 0, r3
3957 ; P9BE-NEXT: blr
3958 ;
3959 ; P9LE-LABEL: spltConst1ll:
3960 ; P9LE: # %bb.0: # %entry
3961 ; P9LE-NEXT: addis r3, r2, .LCPI68_0@toc@ha
3962 ; P9LE-NEXT: addi r3, r3, .LCPI68_0@toc@l
3963 ; P9LE-NEXT: lxvx v2, 0, r3
3964 ; P9LE-NEXT: blr
3965 ;
3966 ; P8BE-LABEL: spltConst1ll:
3967 ; P8BE: # %bb.0: # %entry
3968 ; P8BE-NEXT: addis r3, r2, .LCPI68_0@toc@ha
3969 ; P8BE-NEXT: addi r3, r3, .LCPI68_0@toc@l
3970 ; P8BE-NEXT: lxvd2x v2, 0, r3
3971 ; P8BE-NEXT: blr
3972 ;
3973 ; P8LE-LABEL: spltConst1ll:
3974 ; P8LE: # %bb.0: # %entry
3975 ; P8LE-NEXT: addis r3, r2, .LCPI68_0@toc@ha
3976 ; P8LE-NEXT: addi r3, r3, .LCPI68_0@toc@l
3977 ; P8LE-NEXT: lxvd2x vs0, 0, r3
3978 ; P8LE-NEXT: xxswapd v2, vs0
3979 ; P8LE-NEXT: blr
3980 entry:
3981 ret <2 x i64> <i64 1, i64 1>
3982 }
3984 ; Function Attrs: norecurse nounwind readnone
3985 define <2 x i64> @spltConst16kll() {
3986 ; P9BE-LABEL: spltConst16kll:
3987 ; P9BE: # %bb.0: # %entry
3988 ; P9BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha
3989 ; P9BE-NEXT: addi r3, r3, .LCPI69_0@toc@l
3990 ; P9BE-NEXT: lxvx v2, 0, r3
3991 ; P9BE-NEXT: blr
3992 ;
3993 ; P9LE-LABEL: spltConst16kll:
3994 ; P9LE: # %bb.0: # %entry
3995 ; P9LE-NEXT: addis r3, r2, .LCPI69_0@toc@ha
3996 ; P9LE-NEXT: addi r3, r3, .LCPI69_0@toc@l
3997 ; P9LE-NEXT: lxvx v2, 0, r3
3998 ; P9LE-NEXT: blr
3999 ;
4000 ; P8BE-LABEL: spltConst16kll:
4001 ; P8BE: # %bb.0: # %entry
4002 ; P8BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha
4003 ; P8BE-NEXT: addi r3, r3, .LCPI69_0@toc@l
4004 ; P8BE-NEXT: lxvd2x v2, 0, r3
4005 ; P8BE-NEXT: blr
4006 ;
4007 ; P8LE-LABEL: spltConst16kll:
4008 ; P8LE: # %bb.0: # %entry
4009 ; P8LE-NEXT: addis r3, r2, .LCPI69_0@toc@ha
4010 ; P8LE-NEXT: addi r3, r3, .LCPI69_0@toc@l
4011 ; P8LE-NEXT: lxvd2x vs0, 0, r3
4012 ; P8LE-NEXT: xxswapd v2, vs0
4013 ; P8LE-NEXT: blr
4014 entry:
4015 ret <2 x i64> <i64 32767, i64 32767>
4016 }
4018 ; Function Attrs: norecurse nounwind readnone
4019 define <2 x i64> @spltConst32kll() {
4020 ; P9BE-LABEL: spltConst32kll:
4021 ; P9BE: # %bb.0: # %entry
4022 ; P9BE-NEXT: addis r3, r2, .LCPI70_0@toc@ha
4023 ; P9BE-NEXT: addi r3, r3, .LCPI70_0@toc@l
4024 ; P9BE-NEXT: lxvx v2, 0, r3
4025 ; P9BE-NEXT: blr
4026 ;
4027 ; P9LE-LABEL: spltConst32kll:
4028 ; P9LE: # %bb.0: # %entry
4029 ; P9LE-NEXT: addis r3, r2, .LCPI70_0@toc@ha
4030 ; P9LE-NEXT: addi r3, r3, .LCPI70_0@toc@l
4031 ; P9LE-NEXT: lxvx v2, 0, r3
4032 ; P9LE-NEXT: blr
4033 ;
4034 ; P8BE-LABEL: spltConst32kll:
4035 ; P8BE: # %bb.0: # %entry
4036 ; P8BE-NEXT: addis r3, r2, .LCPI70_0@toc@ha
4037 ; P8BE-NEXT: addi r3, r3, .LCPI70_0@toc@l
4038 ; P8BE-NEXT: lxvd2x v2, 0, r3
4039 ; P8BE-NEXT: blr
4040 ;
4041 ; P8LE-LABEL: spltConst32kll:
4042 ; P8LE: # %bb.0: # %entry
4043 ; P8LE-NEXT: addis r3, r2, .LCPI70_0@toc@ha
4044 ; P8LE-NEXT: addi r3, r3, .LCPI70_0@toc@l
4045 ; P8LE-NEXT: lxvd2x vs0, 0, r3
4046 ; P8LE-NEXT: xxswapd v2, vs0
4047 ; P8LE-NEXT: blr
4048 entry:
4049 ret <2 x i64> <i64 65535, i64 65535>
4050 }
4052 ; Function Attrs: norecurse nounwind readnone
4053 define <2 x i64> @fromRegsll(i64 %a, i64 %b) {
4054 ; P9BE-LABEL: fromRegsll:
4055 ; P9BE: # %bb.0: # %entry
4056 ; P9BE-NEXT: mtvsrdd v2, r3, r4
4057 ; P9BE-NEXT: blr
4058 ;
4059 ; P9LE-LABEL: fromRegsll:
4060 ; P9LE: # %bb.0: # %entry
4061 ; P9LE-NEXT: mtvsrdd v2, r4, r3
4062 ; P9LE-NEXT: blr
4063 ;
4064 ; P8BE-LABEL: fromRegsll:
4065 ; P8BE: # %bb.0: # %entry
4066 ; P8BE-NEXT: mtvsrd f0, r4
4067 ; P8BE-NEXT: mtvsrd f1, r3
4068 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
4069 ; P8BE-NEXT: blr
4070 ;
4071 ; P8LE-LABEL: fromRegsll:
4072 ; P8LE: # %bb.0: # %entry
4073 ; P8LE-NEXT: mtvsrd f0, r3
4074 ; P8LE-NEXT: mtvsrd f1, r4
4075 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
4076 ; P8LE-NEXT: blr
4077 entry:
4078 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0
4079 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1
4080 ret <2 x i64> %vecinit1
4081 }
4083 ; Function Attrs: norecurse nounwind readnone
4084 define <2 x i64> @fromDiffConstsll() {
4085 ; P9BE-LABEL: fromDiffConstsll:
4086 ; P9BE: # %bb.0: # %entry
4087 ; P9BE-NEXT: addis r3, r2, .LCPI72_0@toc@ha
4088 ; P9BE-NEXT: addi r3, r3, .LCPI72_0@toc@l
4089 ; P9BE-NEXT: lxvx v2, 0, r3
4090 ; P9BE-NEXT: blr
4091 ;
4092 ; P9LE-LABEL: fromDiffConstsll:
4093 ; P9LE: # %bb.0: # %entry
4094 ; P9LE-NEXT: addis r3, r2, .LCPI72_0@toc@ha
4095 ; P9LE-NEXT: addi r3, r3, .LCPI72_0@toc@l
4096 ; P9LE-NEXT: lxvx v2, 0, r3
4097 ; P9LE-NEXT: blr
4098 ;
4099 ; P8BE-LABEL: fromDiffConstsll:
4100 ; P8BE: # %bb.0: # %entry
4101 ; P8BE-NEXT: addis r3, r2, .LCPI72_0@toc@ha
4102 ; P8BE-NEXT: addi r3, r3, .LCPI72_0@toc@l
4103 ; P8BE-NEXT: lxvd2x v2, 0, r3
4104 ; P8BE-NEXT: blr
4105 ;
4106 ; P8LE-LABEL: fromDiffConstsll:
4107 ; P8LE: # %bb.0: # %entry
4108 ; P8LE-NEXT: addis r3, r2, .LCPI72_0@toc@ha
4109 ; P8LE-NEXT: addi r3, r3, .LCPI72_0@toc@l
4110 ; P8LE-NEXT: lxvd2x vs0, 0, r3
4111 ; P8LE-NEXT: xxswapd v2, vs0
4112 ; P8LE-NEXT: blr
4113 entry:
4114 ret <2 x i64> <i64 242, i64 -113>
4115 }
4117 ; Function Attrs: norecurse nounwind readonly
4118 define <2 x i64> @fromDiffMemConsAll(i64* nocapture readonly %arr) {
4119 ; P9BE-LABEL: fromDiffMemConsAll:
4120 ; P9BE: # %bb.0: # %entry
4121 ; P9BE-NEXT: lxv v2, 0(r3)
4122 ; P9BE-NEXT: blr
4123 ;
4124 ; P9LE-LABEL: fromDiffMemConsAll:
4125 ; P9LE: # %bb.0: # %entry
4126 ; P9LE-NEXT: lxv v2, 0(r3)
4127 ; P9LE-NEXT: blr
4128 ;
4129 ; P8BE-LABEL: fromDiffMemConsAll:
4130 ; P8BE: # %bb.0: # %entry
4131 ; P8BE-NEXT: lxvd2x v2, 0, r3
4132 ; P8BE-NEXT: blr
4133 ;
4134 ; P8LE-LABEL: fromDiffMemConsAll:
4135 ; P8LE: # %bb.0: # %entry
4136 ; P8LE-NEXT: lxvd2x vs0, 0, r3
4137 ; P8LE-NEXT: xxswapd v2, vs0
4138 ; P8LE-NEXT: blr
4139 entry:
4140 %0 = load i64, i64* %arr, align 8
4141 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
4142 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 1
4143 %1 = load i64, i64* %arrayidx1, align 8
4144 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
4145 ret <2 x i64> %vecinit2
4146 }
4148 ; Function Attrs: norecurse nounwind readonly
4149 define <2 x i64> @fromDiffMemConsDll(i64* nocapture readonly %arr) {
4150 ; P9BE-LABEL: fromDiffMemConsDll:
4151 ; P9BE: # %bb.0: # %entry
4152 ; P9BE-NEXT: lxv v2, 16(r3)
4153 ; P9BE-NEXT: xxswapd v2, v2
4154 ; P9BE-NEXT: blr
4155 ;
4156 ; P9LE-LABEL: fromDiffMemConsDll:
4157 ; P9LE: # %bb.0: # %entry
4158 ; P9LE-NEXT: lxv v2, 16(r3)
4159 ; P9LE-NEXT: xxswapd v2, v2
4160 ; P9LE-NEXT: blr
4161 ;
4162 ; P8BE-LABEL: fromDiffMemConsDll:
4163 ; P8BE: # %bb.0: # %entry
4164 ; P8BE-NEXT: addi r3, r3, 16
4165 ; P8BE-NEXT: lxvd2x v2, 0, r3
4166 ; P8BE-NEXT: xxswapd v2, v2
4167 ; P8BE-NEXT: blr
4168 ;
4169 ; P8LE-LABEL: fromDiffMemConsDll:
4170 ; P8LE: # %bb.0: # %entry
4171 ; P8LE-NEXT: addi r3, r3, 16
4172 ; P8LE-NEXT: lxvd2x v2, 0, r3
4173 ; P8LE-NEXT: blr
4174 entry:
4175 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 3
4176 %0 = load i64, i64* %arrayidx, align 8
4177 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
4178 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 2
4179 %1 = load i64, i64* %arrayidx1, align 8
4180 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
4181 ret <2 x i64> %vecinit2
4182 }
4184 ; Function Attrs: norecurse nounwind readonly
4185 define <2 x i64> @fromDiffMemVarAll(i64* nocapture readonly %arr, i32 signext %elem) {
4186 ; P9BE-LABEL: fromDiffMemVarAll:
4187 ; P9BE: # %bb.0: # %entry
4188 ; P9BE-NEXT: sldi r4, r4, 3
4189 ; P9BE-NEXT: lxvx v2, r3, r4
4190 ; P9BE-NEXT: blr
4191 ;
4192 ; P9LE-LABEL: fromDiffMemVarAll:
4193 ; P9LE: # %bb.0: # %entry
4194 ; P9LE-NEXT: sldi r4, r4, 3
4195 ; P9LE-NEXT: lxvx v2, r3, r4
4196 ; P9LE-NEXT: blr
4197 ;
4198 ; P8BE-LABEL: fromDiffMemVarAll:
4199 ; P8BE: # %bb.0: # %entry
4200 ; P8BE-NEXT: sldi r4, r4, 3
4201 ; P8BE-NEXT: lxvd2x v2, r3, r4
4202 ; P8BE-NEXT: blr
4203 ;
4204 ; P8LE-LABEL: fromDiffMemVarAll:
4205 ; P8LE: # %bb.0: # %entry
4206 ; P8LE-NEXT: sldi r4, r4, 3
4207 ; P8LE-NEXT: lxvd2x vs0, r3, r4
4208 ; P8LE-NEXT: xxswapd v2, vs0
4209 ; P8LE-NEXT: blr
4210 entry:
4211 %idxprom = sext i32 %elem to i64
4212 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom
4213 %0 = load i64, i64* %arrayidx, align 8
4214 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
4215 %add = add nsw i32 %elem, 1
4216 %idxprom1 = sext i32 %add to i64
4217 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1
4218 %1 = load i64, i64* %arrayidx2, align 8
4219 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
4220 ret <2 x i64> %vecinit3
4221 }
4223 ; Function Attrs: norecurse nounwind readonly
4224 define <2 x i64> @fromDiffMemVarDll(i64* nocapture readonly %arr, i32 signext %elem) {
4225 ; P9BE-LABEL: fromDiffMemVarDll:
4226 ; P9BE: # %bb.0: # %entry
4227 ; P9BE-NEXT: sldi r4, r4, 3
4228 ; P9BE-NEXT: add r3, r3, r4
4229 ; P9BE-NEXT: li r4, -8
4230 ; P9BE-NEXT: lxvx v2, r3, r4
4231 ; P9BE-NEXT: xxswapd v2, v2
4232 ; P9BE-NEXT: blr
4233 ;
4234 ; P9LE-LABEL: fromDiffMemVarDll:
4235 ; P9LE: # %bb.0: # %entry
4236 ; P9LE-NEXT: sldi r4, r4, 3
4237 ; P9LE-NEXT: add r3, r3, r4
4238 ; P9LE-NEXT: li r4, -8
4239 ; P9LE-NEXT: lxvx v2, r3, r4
4240 ; P9LE-NEXT: xxswapd v2, v2
4241 ; P9LE-NEXT: blr
4242 ;
4243 ; P8BE-LABEL: fromDiffMemVarDll:
4244 ; P8BE: # %bb.0: # %entry
4245 ; P8BE-NEXT: sldi r4, r4, 3
4246 ; P8BE-NEXT: add r3, r3, r4
4247 ; P8BE-NEXT: addi r3, r3, -8
4248 ; P8BE-NEXT: lxvd2x v2, 0, r3
4249 ; P8BE-NEXT: xxswapd v2, v2
4250 ; P8BE-NEXT: blr
4251 ;
4252 ; P8LE-LABEL: fromDiffMemVarDll:
4253 ; P8LE: # %bb.0: # %entry
4254 ; P8LE-NEXT: sldi r4, r4, 3
4255 ; P8LE-NEXT: add r3, r3, r4
4256 ; P8LE-NEXT: addi r3, r3, -8
4257 ; P8LE-NEXT: lxvd2x v2, 0, r3
4258 ; P8LE-NEXT: blr
4259 entry:
4260 %idxprom = sext i32 %elem to i64
4261 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom
4262 %0 = load i64, i64* %arrayidx, align 8
4263 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
4264 %sub = add nsw i32 %elem, -1
4265 %idxprom1 = sext i32 %sub to i64
4266 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1
4267 %1 = load i64, i64* %arrayidx2, align 8
4268 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
4269 ret <2 x i64> %vecinit3
4270 }
4272 ; Function Attrs: norecurse nounwind readonly
4273 define <2 x i64> @fromRandMemConsll(i64* nocapture readonly %arr) {
4274 ; P9BE-LABEL: fromRandMemConsll:
4275 ; P9BE: # %bb.0: # %entry
4276 ; P9BE-NEXT: ld r4, 32(r3)
4277 ; P9BE-NEXT: ld r3, 144(r3)
4278 ; P9BE-NEXT: mtvsrdd v2, r4, r3
4279 ; P9BE-NEXT: blr
4280 ;
4281 ; P9LE-LABEL: fromRandMemConsll:
4282 ; P9LE: # %bb.0: # %entry
4283 ; P9LE-NEXT: ld r4, 32(r3)
4284 ; P9LE-NEXT: ld r3, 144(r3)
4285 ; P9LE-NEXT: mtvsrdd v2, r3, r4
4286 ; P9LE-NEXT: blr
4287 ;
4288 ; P8BE-LABEL: fromRandMemConsll:
4289 ; P8BE: # %bb.0: # %entry
4290 ; P8BE-NEXT: ld r4, 144(r3)
4291 ; P8BE-NEXT: ld r3, 32(r3)
4292 ; P8BE-NEXT: mtvsrd f0, r4
4293 ; P8BE-NEXT: mtvsrd f1, r3
4294 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
4295 ; P8BE-NEXT: blr
4296 ;
4297 ; P8LE-LABEL: fromRandMemConsll:
4298 ; P8LE: # %bb.0: # %entry
4299 ; P8LE-NEXT: ld r4, 32(r3)
4300 ; P8LE-NEXT: ld r3, 144(r3)
4301 ; P8LE-NEXT: mtvsrd f0, r4
4302 ; P8LE-NEXT: mtvsrd f1, r3
4303 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
4304 ; P8LE-NEXT: blr
4305 entry:
4306 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 4
4307 %0 = load i64, i64* %arrayidx, align 8
4308 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
4309 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 18
4310 %1 = load i64, i64* %arrayidx1, align 8
4311 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
4312 ret <2 x i64> %vecinit2
4313 }
4315 ; Function Attrs: norecurse nounwind readonly
4316 define <2 x i64> @fromRandMemVarll(i64* nocapture readonly %arr, i32 signext %elem) {
4317 ; P9BE-LABEL: fromRandMemVarll:
4318 ; P9BE: # %bb.0: # %entry
4319 ; P9BE-NEXT: sldi r4, r4, 3
4320 ; P9BE-NEXT: add r3, r3, r4
4321 ; P9BE-NEXT: ld r4, 32(r3)
4322 ; P9BE-NEXT: ld r3, 8(r3)
4323 ; P9BE-NEXT: mtvsrdd v2, r4, r3
4324 ; P9BE-NEXT: blr
4325 ;
4326 ; P9LE-LABEL: fromRandMemVarll:
4327 ; P9LE: # %bb.0: # %entry
4328 ; P9LE-NEXT: sldi r4, r4, 3
4329 ; P9LE-NEXT: add r3, r3, r4
4330 ; P9LE-NEXT: ld r4, 32(r3)
4331 ; P9LE-NEXT: ld r3, 8(r3)
4332 ; P9LE-NEXT: mtvsrdd v2, r3, r4
4333 ; P9LE-NEXT: blr
4334 ;
4335 ; P8BE-LABEL: fromRandMemVarll:
4336 ; P8BE: # %bb.0: # %entry
4337 ; P8BE-NEXT: sldi r4, r4, 3
4338 ; P8BE-NEXT: add r3, r3, r4
4339 ; P8BE-NEXT: ld r4, 8(r3)
4340 ; P8BE-NEXT: ld r3, 32(r3)
4341 ; P8BE-NEXT: mtvsrd f0, r4
4342 ; P8BE-NEXT: mtvsrd f1, r3
4343 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
4344 ; P8BE-NEXT: blr
4345 ;
4346 ; P8LE-LABEL: fromRandMemVarll:
4347 ; P8LE: # %bb.0: # %entry
4348 ; P8LE-NEXT: sldi r4, r4, 3
4349 ; P8LE-NEXT: add r3, r3, r4
4350 ; P8LE-NEXT: ld r4, 32(r3)
4351 ; P8LE-NEXT: ld r3, 8(r3)
4352 ; P8LE-NEXT: mtvsrd f0, r4
4353 ; P8LE-NEXT: mtvsrd f1, r3
4354 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
4355 ; P8LE-NEXT: blr
4356 entry:
4357 %add = add nsw i32 %elem, 4
4358 %idxprom = sext i32 %add to i64
4359 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom
4360 %0 = load i64, i64* %arrayidx, align 8
4361 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
4362 %add1 = add nsw i32 %elem, 1
4363 %idxprom2 = sext i32 %add1 to i64
4364 %arrayidx3 = getelementptr inbounds i64, i64* %arr, i64 %idxprom2
4365 %1 = load i64, i64* %arrayidx3, align 8
4366 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
4367 ret <2 x i64> %vecinit4
4368 }
4370 ; Function Attrs: norecurse nounwind readnone
4371 define <2 x i64> @spltRegValll(i64 %val) {
4372 ; P9BE-LABEL: spltRegValll:
4373 ; P9BE: # %bb.0: # %entry
4374 ; P9BE-NEXT: mtvsrdd v2, r3, r3
4375 ; P9BE-NEXT: blr
4376 ;
4377 ; P9LE-LABEL: spltRegValll:
4378 ; P9LE: # %bb.0: # %entry
4379 ; P9LE-NEXT: mtvsrdd v2, r3, r3
4380 ; P9LE-NEXT: blr
4381 ;
4382 ; P8BE-LABEL: spltRegValll:
4383 ; P8BE: # %bb.0: # %entry
4384 ; P8BE-NEXT: mtvsrd f0, r3
4385 ; P8BE-NEXT: xxspltd v2, vs0, 0
4386 ; P8BE-NEXT: blr
4387 ;
4388 ; P8LE-LABEL: spltRegValll:
4389 ; P8LE: # %bb.0: # %entry
4390 ; P8LE-NEXT: mtvsrd f0, r3
4391 ; P8LE-NEXT: xxspltd v2, vs0, 0
4392 ; P8LE-NEXT: blr
4393 entry:
4394 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0
4395 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
4396 ret <2 x i64> %splat.splat
4397 }
4399 ; Function Attrs: norecurse nounwind readonly
4400 define <2 x i64> @spltMemValll(i64* nocapture readonly %ptr) {
4401 ; P9BE-LABEL: spltMemValll:
4402 ; P9BE: # %bb.0: # %entry
4403 ; P9BE-NEXT: lxvdsx v2, 0, r3
4404 ; P9BE-NEXT: blr
4405 ;
4406 ; P9LE-LABEL: spltMemValll:
4407 ; P9LE: # %bb.0: # %entry
4408 ; P9LE-NEXT: lxvdsx v2, 0, r3
4409 ; P9LE-NEXT: blr
4410 ;
4411 ; P8BE-LABEL: spltMemValll:
4412 ; P8BE: # %bb.0: # %entry
4413 ; P8BE-NEXT: lxvdsx v2, 0, r3
4414 ; P8BE-NEXT: blr
4415 ;
4416 ; P8LE-LABEL: spltMemValll:
4417 ; P8LE: # %bb.0: # %entry
4418 ; P8LE-NEXT: lxvdsx v2, 0, r3
4419 ; P8LE-NEXT: blr
4420 entry:
4421 %0 = load i64, i64* %ptr, align 8
4422 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0
4423 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
4424 ret <2 x i64> %splat.splat
4425 }
4427 ; Function Attrs: norecurse nounwind readnone
4428 define <2 x i64> @spltCnstConvftoll() {
4429 ; P9BE-LABEL: spltCnstConvftoll:
4430 ; P9BE: # %bb.0: # %entry
4431 ; P9BE-NEXT: addis r3, r2, .LCPI81_0@toc@ha
4432 ; P9BE-NEXT: addi r3, r3, .LCPI81_0@toc@l
4433 ; P9BE-NEXT: lxvx v2, 0, r3
4434 ; P9BE-NEXT: blr
4435 ;
4436 ; P9LE-LABEL: spltCnstConvftoll:
4437 ; P9LE: # %bb.0: # %entry
4438 ; P9LE-NEXT: addis r3, r2, .LCPI81_0@toc@ha
4439 ; P9LE-NEXT: addi r3, r3, .LCPI81_0@toc@l
4440 ; P9LE-NEXT: lxvx v2, 0, r3
4441 ; P9LE-NEXT: blr
4442 ;
4443 ; P8BE-LABEL: spltCnstConvftoll:
4444 ; P8BE: # %bb.0: # %entry
4445 ; P8BE-NEXT: addis r3, r2, .LCPI81_0@toc@ha
4446 ; P8BE-NEXT: addi r3, r3, .LCPI81_0@toc@l
4447 ; P8BE-NEXT: lxvd2x v2, 0, r3
4448 ; P8BE-NEXT: blr
4449 ;
4450 ; P8LE-LABEL: spltCnstConvftoll:
4451 ; P8LE: # %bb.0: # %entry
4452 ; P8LE-NEXT: addis r3, r2, .LCPI81_0@toc@ha
4453 ; P8LE-NEXT: addi r3, r3, .LCPI81_0@toc@l
4454 ; P8LE-NEXT: lxvd2x vs0, 0, r3
4455 ; P8LE-NEXT: xxswapd v2, vs0
4456 ; P8LE-NEXT: blr
4457 entry:
4458 ret <2 x i64> <i64 4, i64 4>
4459 }
4461 ; Function Attrs: norecurse nounwind readnone
4462 define <2 x i64> @fromRegsConvftoll(float %a, float %b) {
4463 ; P9BE-LABEL: fromRegsConvftoll:
4464 ; P9BE: # %bb.0: # %entry
4465 ; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
4466 ; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
4467 ; P9BE-NEXT: xxmrghd vs0, vs1, vs2
4468 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4469 ; P9BE-NEXT: blr
4470 ;
4471 ; P9LE-LABEL: fromRegsConvftoll:
4472 ; P9LE: # %bb.0: # %entry
4473 ; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
4474 ; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
4475 ; P9LE-NEXT: xxmrghd vs0, vs2, vs1
4476 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4477 ; P9LE-NEXT: blr
4478 ;
4479 ; P8BE-LABEL: fromRegsConvftoll:
4480 ; P8BE: # %bb.0: # %entry
4481 ; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
4482 ; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
4483 ; P8BE-NEXT: xxmrghd vs0, vs1, vs2
4484 ; P8BE-NEXT: xvcvdpsxds v2, vs0
4485 ; P8BE-NEXT: blr
4486 ;
4487 ; P8LE-LABEL: fromRegsConvftoll:
4488 ; P8LE: # %bb.0: # %entry
4489 ; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
4490 ; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
4491 ; P8LE-NEXT: xxmrghd vs0, vs2, vs1
4492 ; P8LE-NEXT: xvcvdpsxds v2, vs0
4493 ; P8LE-NEXT: blr
4494 entry:
4495 %conv = fptosi float %a to i64
4496 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4497 %conv1 = fptosi float %b to i64
4498 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1
4499 ret <2 x i64> %vecinit2
4500 }
4502 ; Function Attrs: norecurse nounwind readnone
4503 define <2 x i64> @fromDiffConstsConvftoll() {
4504 ; P9BE-LABEL: fromDiffConstsConvftoll:
4505 ; P9BE: # %bb.0: # %entry
4506 ; P9BE-NEXT: addis r3, r2, .LCPI83_0@toc@ha
4507 ; P9BE-NEXT: addi r3, r3, .LCPI83_0@toc@l
4508 ; P9BE-NEXT: lxvx v2, 0, r3
4509 ; P9BE-NEXT: blr
4510 ;
4511 ; P9LE-LABEL: fromDiffConstsConvftoll:
4512 ; P9LE: # %bb.0: # %entry
4513 ; P9LE-NEXT: addis r3, r2, .LCPI83_0@toc@ha
4514 ; P9LE-NEXT: addi r3, r3, .LCPI83_0@toc@l
4515 ; P9LE-NEXT: lxvx v2, 0, r3
4516 ; P9LE-NEXT: blr
4517 ;
4518 ; P8BE-LABEL: fromDiffConstsConvftoll:
4519 ; P8BE: # %bb.0: # %entry
4520 ; P8BE-NEXT: addis r3, r2, .LCPI83_0@toc@ha
4521 ; P8BE-NEXT: addi r3, r3, .LCPI83_0@toc@l
4522 ; P8BE-NEXT: lxvd2x v2, 0, r3
4523 ; P8BE-NEXT: blr
4524 ;
4525 ; P8LE-LABEL: fromDiffConstsConvftoll:
4526 ; P8LE: # %bb.0: # %entry
4527 ; P8LE-NEXT: addis r3, r2, .LCPI83_0@toc@ha
4528 ; P8LE-NEXT: addi r3, r3, .LCPI83_0@toc@l
4529 ; P8LE-NEXT: lxvd2x vs0, 0, r3
4530 ; P8LE-NEXT: xxswapd v2, vs0
4531 ; P8LE-NEXT: blr
4532 entry:
4533 ret <2 x i64> <i64 24, i64 234>
4534 }
4536 ; Function Attrs: norecurse nounwind readonly
4537 define <2 x i64> @fromDiffMemConsAConvftoll(float* nocapture readonly %ptr) {
4538 ; P9BE-LABEL: fromDiffMemConsAConvftoll:
4539 ; P9BE: # %bb.0: # %entry
4540 ; P9BE-NEXT: lfs f0, 0(r3)
4541 ; P9BE-NEXT: lfs f1, 4(r3)
4542 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
4543 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4544 ; P9BE-NEXT: blr
4545 ;
4546 ; P9LE-LABEL: fromDiffMemConsAConvftoll:
4547 ; P9LE: # %bb.0: # %entry
4548 ; P9LE-NEXT: lfs f0, 0(r3)
4549 ; P9LE-NEXT: lfs f1, 4(r3)
4550 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
4551 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4552 ; P9LE-NEXT: blr
4553 ;
4554 ; P8BE-LABEL: fromDiffMemConsAConvftoll:
4555 ; P8BE: # %bb.0: # %entry
4556 ; P8BE-NEXT: lfsx f0, 0, r3
4557 ; P8BE-NEXT: lfs f1, 4(r3)
4558 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
4559 ; P8BE-NEXT: xvcvdpsxds v2, vs0
4560 ; P8BE-NEXT: blr
4561 ;
4562 ; P8LE-LABEL: fromDiffMemConsAConvftoll:
4563 ; P8LE: # %bb.0: # %entry
4564 ; P8LE-NEXT: lfsx f0, 0, r3
4565 ; P8LE-NEXT: lfs f1, 4(r3)
4566 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
4567 ; P8LE-NEXT: xvcvdpsxds v2, vs0
4568 ; P8LE-NEXT: blr
4569 entry:
4570 %0 = load float, float* %ptr, align 4
4571 %conv = fptosi float %0 to i64
4572 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4573 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 1
4574 %1 = load float, float* %arrayidx1, align 4
4575 %conv2 = fptosi float %1 to i64
4576 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
4577 ret <2 x i64> %vecinit3
4578 }
4580 ; Function Attrs: norecurse nounwind readonly
4581 define <2 x i64> @fromDiffMemConsDConvftoll(float* nocapture readonly %ptr) {
4582 ; P9BE-LABEL: fromDiffMemConsDConvftoll:
4583 ; P9BE: # %bb.0: # %entry
4584 ; P9BE-NEXT: lfs f0, 12(r3)
4585 ; P9BE-NEXT: lfs f1, 8(r3)
4586 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
4587 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4588 ; P9BE-NEXT: blr
4589 ;
4590 ; P9LE-LABEL: fromDiffMemConsDConvftoll:
4591 ; P9LE: # %bb.0: # %entry
4592 ; P9LE-NEXT: lfs f0, 12(r3)
4593 ; P9LE-NEXT: lfs f1, 8(r3)
4594 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
4595 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4596 ; P9LE-NEXT: blr
4597 ;
4598 ; P8BE-LABEL: fromDiffMemConsDConvftoll:
4599 ; P8BE: # %bb.0: # %entry
4600 ; P8BE-NEXT: lfs f0, 12(r3)
4601 ; P8BE-NEXT: lfs f1, 8(r3)
4602 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
4603 ; P8BE-NEXT: xvcvdpsxds v2, vs0
4604 ; P8BE-NEXT: blr
4605 ;
4606 ; P8LE-LABEL: fromDiffMemConsDConvftoll:
4607 ; P8LE: # %bb.0: # %entry
4608 ; P8LE-NEXT: lfs f0, 12(r3)
4609 ; P8LE-NEXT: lfs f1, 8(r3)
4610 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
4611 ; P8LE-NEXT: xvcvdpsxds v2, vs0
4612 ; P8LE-NEXT: blr
4613 entry:
4614 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3
4615 %0 = load float, float* %arrayidx, align 4
4616 %conv = fptosi float %0 to i64
4617 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4618 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2
4619 %1 = load float, float* %arrayidx1, align 4
4620 %conv2 = fptosi float %1 to i64
4621 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
4622 ret <2 x i64> %vecinit3
4623 }
4625 ; Function Attrs: norecurse nounwind readonly
4626 define <2 x i64> @fromDiffMemVarAConvftoll(float* nocapture readonly %arr, i32 signext %elem) {
4627 ; P9BE-LABEL: fromDiffMemVarAConvftoll:
4628 ; P9BE: # %bb.0: # %entry
4629 ; P9BE-NEXT: sldi r4, r4, 2
4630 ; P9BE-NEXT: lfsux f0, r3, r4
4631 ; P9BE-NEXT: lfs f1, 4(r3)
4632 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
4633 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4634 ; P9BE-NEXT: blr
4635 ;
4636 ; P9LE-LABEL: fromDiffMemVarAConvftoll:
4637 ; P9LE: # %bb.0: # %entry
4638 ; P9LE-NEXT: sldi r4, r4, 2
4639 ; P9LE-NEXT: lfsux f0, r3, r4
4640 ; P9LE-NEXT: lfs f1, 4(r3)
4641 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
4642 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4643 ; P9LE-NEXT: blr
4644 ;
4645 ; P8BE-LABEL: fromDiffMemVarAConvftoll:
4646 ; P8BE: # %bb.0: # %entry
4647 ; P8BE-NEXT: sldi r4, r4, 2
4648 ; P8BE-NEXT: lfsux f0, r3, r4
4649 ; P8BE-NEXT: lfs f1, 4(r3)
4650 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
4651 ; P8BE-NEXT: xvcvdpsxds v2, vs0
4652 ; P8BE-NEXT: blr
4653 ;
4654 ; P8LE-LABEL: fromDiffMemVarAConvftoll:
4655 ; P8LE: # %bb.0: # %entry
4656 ; P8LE-NEXT: sldi r4, r4, 2
4657 ; P8LE-NEXT: lfsux f0, r3, r4
4658 ; P8LE-NEXT: lfs f1, 4(r3)
4659 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
4660 ; P8LE-NEXT: xvcvdpsxds v2, vs0
4661 ; P8LE-NEXT: blr
4662 entry:
4663 %idxprom = sext i32 %elem to i64
4664 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom
4665 %0 = load float, float* %arrayidx, align 4
4666 %conv = fptosi float %0 to i64
4667 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4668 %add = add nsw i32 %elem, 1
4669 %idxprom1 = sext i32 %add to i64
4670 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1
4671 %1 = load float, float* %arrayidx2, align 4
4672 %conv3 = fptosi float %1 to i64
4673 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
4674 ret <2 x i64> %vecinit4
4675 }
4677 ; Function Attrs: norecurse nounwind readonly
4678 define <2 x i64> @fromDiffMemVarDConvftoll(float* nocapture readonly %arr, i32 signext %elem) {
4679 ; P9BE-LABEL: fromDiffMemVarDConvftoll:
4680 ; P9BE: # %bb.0: # %entry
4681 ; P9BE-NEXT: sldi r4, r4, 2
4682 ; P9BE-NEXT: lfsux f0, r3, r4
4683 ; P9BE-NEXT: lfs f1, -4(r3)
4684 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
4685 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4686 ; P9BE-NEXT: blr
4687 ;
4688 ; P9LE-LABEL: fromDiffMemVarDConvftoll:
4689 ; P9LE: # %bb.0: # %entry
4690 ; P9LE-NEXT: sldi r4, r4, 2
4691 ; P9LE-NEXT: lfsux f0, r3, r4
4692 ; P9LE-NEXT: lfs f1, -4(r3)
4693 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
4694 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4695 ; P9LE-NEXT: blr
4696 ;
4697 ; P8BE-LABEL: fromDiffMemVarDConvftoll:
4698 ; P8BE: # %bb.0: # %entry
4699 ; P8BE-NEXT: sldi r4, r4, 2
4700 ; P8BE-NEXT: lfsux f0, r3, r4
4701 ; P8BE-NEXT: lfs f1, -4(r3)
4702 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
4703 ; P8BE-NEXT: xvcvdpsxds v2, vs0
4704 ; P8BE-NEXT: blr
4705 ;
4706 ; P8LE-LABEL: fromDiffMemVarDConvftoll:
4707 ; P8LE: # %bb.0: # %entry
4708 ; P8LE-NEXT: sldi r4, r4, 2
4709 ; P8LE-NEXT: lfsux f0, r3, r4
4710 ; P8LE-NEXT: lfs f1, -4(r3)
4711 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
4712 ; P8LE-NEXT: xvcvdpsxds v2, vs0
4713 ; P8LE-NEXT: blr
4714 entry:
4715 %idxprom = sext i32 %elem to i64
4716 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom
4717 %0 = load float, float* %arrayidx, align 4
4718 %conv = fptosi float %0 to i64
4719 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4720 %sub = add nsw i32 %elem, -1
4721 %idxprom1 = sext i32 %sub to i64
4722 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1
4723 %1 = load float, float* %arrayidx2, align 4
4724 %conv3 = fptosi float %1 to i64
4725 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
4726 ret <2 x i64> %vecinit4
4727 }
4729 ; Function Attrs: norecurse nounwind readnone
4730 define <2 x i64> @spltRegValConvftoll(float %val) {
4731 ; P9BE-LABEL: spltRegValConvftoll:
4732 ; P9BE: # %bb.0: # %entry
4733 ; P9BE-NEXT: xscvdpsxds f0, f1
4734 ; P9BE-NEXT: xxspltd v2, f0, 0
4735 ; P9BE-NEXT: blr
4736 ;
4737 ; P9LE-LABEL: spltRegValConvftoll:
4738 ; P9LE: # %bb.0: # %entry
4739 ; P9LE-NEXT: xscvdpsxds f0, f1
4740 ; P9LE-NEXT: xxspltd v2, f0, 0
4741 ; P9LE-NEXT: blr
4742 ;
4743 ; P8BE-LABEL: spltRegValConvftoll:
4744 ; P8BE: # %bb.0: # %entry
4745 ; P8BE-NEXT: xscvdpsxds f0, f1
4746 ; P8BE-NEXT: xxspltd v2, f0, 0
4747 ; P8BE-NEXT: blr
4748 ;
4749 ; P8LE-LABEL: spltRegValConvftoll:
4750 ; P8LE: # %bb.0: # %entry
4751 ; P8LE-NEXT: xscvdpsxds f0, f1
4752 ; P8LE-NEXT: xxspltd v2, f0, 0
4753 ; P8LE-NEXT: blr
4754 entry:
4755 %conv = fptosi float %val to i64
4756 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
4757 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
4758 ret <2 x i64> %splat.splat
4759 }
4761 ; Function Attrs: norecurse nounwind readonly
4762 define <2 x i64> @spltMemValConvftoll(float* nocapture readonly %ptr) {
4763 ; P9BE-LABEL: spltMemValConvftoll:
4764 ; P9BE: # %bb.0: # %entry
4765 ; P9BE-NEXT: lfs f0, 0(r3)
4766 ; P9BE-NEXT: xscvdpsxds f0, f0
4767 ; P9BE-NEXT: xxspltd v2, f0, 0
4768 ; P9BE-NEXT: blr
4769 ;
4770 ; P9LE-LABEL: spltMemValConvftoll:
4771 ; P9LE: # %bb.0: # %entry
4772 ; P9LE-NEXT: lfs f0, 0(r3)
4773 ; P9LE-NEXT: xscvdpsxds f0, f0
4774 ; P9LE-NEXT: xxspltd v2, f0, 0
4775 ; P9LE-NEXT: blr
4776 ;
4777 ; P8BE-LABEL: spltMemValConvftoll:
4778 ; P8BE: # %bb.0: # %entry
4779 ; P8BE-NEXT: lfsx f0, 0, r3
4780 ; P8BE-NEXT: xscvdpsxds f0, f0
4781 ; P8BE-NEXT: xxspltd v2, f0, 0
4782 ; P8BE-NEXT: blr
4783 ;
4784 ; P8LE-LABEL: spltMemValConvftoll:
4785 ; P8LE: # %bb.0: # %entry
4786 ; P8LE-NEXT: lfsx f0, 0, r3
4787 ; P8LE-NEXT: xscvdpsxds f0, f0
4788 ; P8LE-NEXT: xxspltd v2, f0, 0
4789 ; P8LE-NEXT: blr
4790 entry:
4791 %0 = load float, float* %ptr, align 4
4792 %conv = fptosi float %0 to i64
4793 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
4794 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
4795 ret <2 x i64> %splat.splat
4796 }
4798 ; Function Attrs: norecurse nounwind readnone
4799 define <2 x i64> @spltCnstConvdtoll() {
4800 ; P9BE-LABEL: spltCnstConvdtoll:
4801 ; P9BE: # %bb.0: # %entry
4802 ; P9BE-NEXT: addis r3, r2, .LCPI90_0@toc@ha
4803 ; P9BE-NEXT: addi r3, r3, .LCPI90_0@toc@l
4804 ; P9BE-NEXT: lxvx v2, 0, r3
4805 ; P9BE-NEXT: blr
4806 ;
4807 ; P9LE-LABEL: spltCnstConvdtoll:
4808 ; P9LE: # %bb.0: # %entry
4809 ; P9LE-NEXT: addis r3, r2, .LCPI90_0@toc@ha
4810 ; P9LE-NEXT: addi r3, r3, .LCPI90_0@toc@l
4811 ; P9LE-NEXT: lxvx v2, 0, r3
4812 ; P9LE-NEXT: blr
4813 ;
4814 ; P8BE-LABEL: spltCnstConvdtoll:
4815 ; P8BE: # %bb.0: # %entry
4816 ; P8BE-NEXT: addis r3, r2, .LCPI90_0@toc@ha
4817 ; P8BE-NEXT: addi r3, r3, .LCPI90_0@toc@l
4818 ; P8BE-NEXT: lxvd2x v2, 0, r3
4819 ; P8BE-NEXT: blr
4820 ;
4821 ; P8LE-LABEL: spltCnstConvdtoll:
4822 ; P8LE: # %bb.0: # %entry
4823 ; P8LE-NEXT: addis r3, r2, .LCPI90_0@toc@ha
4824 ; P8LE-NEXT: addi r3, r3, .LCPI90_0@toc@l
4825 ; P8LE-NEXT: lxvd2x vs0, 0, r3
4826 ; P8LE-NEXT: xxswapd v2, vs0
4827 ; P8LE-NEXT: blr
4828 entry:
4829 ret <2 x i64> <i64 4, i64 4>
4830 }
4832 ; Function Attrs: norecurse nounwind readnone
4833 define <2 x i64> @fromRegsConvdtoll(double %a, double %b) {
4834 ; P9BE-LABEL: fromRegsConvdtoll:
4835 ; P9BE: # %bb.0: # %entry
4836 ; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
4837 ; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
4838 ; P9BE-NEXT: xxmrghd vs0, vs1, vs2
4839 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4840 ; P9BE-NEXT: blr
4841 ;
4842 ; P9LE-LABEL: fromRegsConvdtoll:
4843 ; P9LE: # %bb.0: # %entry
4844 ; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
4845 ; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
4846 ; P9LE-NEXT: xxmrghd vs0, vs2, vs1
4847 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4848 ; P9LE-NEXT: blr
4849 ;
4850 ; P8BE-LABEL: fromRegsConvdtoll:
4851 ; P8BE: # %bb.0: # %entry
4852 ; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
4853 ; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
4854 ; P8BE-NEXT: xxmrghd vs0, vs1, vs2
4855 ; P8BE-NEXT: xvcvdpsxds v2, vs0
4856 ; P8BE-NEXT: blr
4857 ;
4858 ; P8LE-LABEL: fromRegsConvdtoll:
4859 ; P8LE: # %bb.0: # %entry
4860 ; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
4861 ; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
4862 ; P8LE-NEXT: xxmrghd vs0, vs2, vs1
4863 ; P8LE-NEXT: xvcvdpsxds v2, vs0
4864 ; P8LE-NEXT: blr
4865 entry:
4866 %conv = fptosi double %a to i64
4867 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4868 %conv1 = fptosi double %b to i64
4869 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1
4870 ret <2 x i64> %vecinit2
4871 }
4873 ; Function Attrs: norecurse nounwind readnone
4874 define <2 x i64> @fromDiffConstsConvdtoll() {
4875 ; P9BE-LABEL: fromDiffConstsConvdtoll:
4876 ; P9BE: # %bb.0: # %entry
4877 ; P9BE-NEXT: addis r3, r2, .LCPI92_0@toc@ha
4878 ; P9BE-NEXT: addi r3, r3, .LCPI92_0@toc@l
4879 ; P9BE-NEXT: lxvx v2, 0, r3
4880 ; P9BE-NEXT: blr
4881 ;
4882 ; P9LE-LABEL: fromDiffConstsConvdtoll:
4883 ; P9LE: # %bb.0: # %entry
4884 ; P9LE-NEXT: addis r3, r2, .LCPI92_0@toc@ha
4885 ; P9LE-NEXT: addi r3, r3, .LCPI92_0@toc@l
4886 ; P9LE-NEXT: lxvx v2, 0, r3
4887 ; P9LE-NEXT: blr
4888 ;
4889 ; P8BE-LABEL: fromDiffConstsConvdtoll:
4890 ; P8BE: # %bb.0: # %entry
4891 ; P8BE-NEXT: addis r3, r2, .LCPI92_0@toc@ha
4892 ; P8BE-NEXT: addi r3, r3, .LCPI92_0@toc@l
4893 ; P8BE-NEXT: lxvd2x v2, 0, r3
4894 ; P8BE-NEXT: blr
4895 ;
4896 ; P8LE-LABEL: fromDiffConstsConvdtoll:
4897 ; P8LE: # %bb.0: # %entry
4898 ; P8LE-NEXT: addis r3, r2, .LCPI92_0@toc@ha
4899 ; P8LE-NEXT: addi r3, r3, .LCPI92_0@toc@l
4900 ; P8LE-NEXT: lxvd2x vs0, 0, r3
4901 ; P8LE-NEXT: xxswapd v2, vs0
4902 ; P8LE-NEXT: blr
4903 entry:
4904 ret <2 x i64> <i64 24, i64 234>
4905 }
4907 ; Function Attrs: norecurse nounwind readonly
4908 define <2 x i64> @fromDiffMemConsAConvdtoll(double* nocapture readonly %ptr) {
4909 ; P9BE-LABEL: fromDiffMemConsAConvdtoll:
4910 ; P9BE: # %bb.0: # %entry
4911 ; P9BE-NEXT: lxv vs0, 0(r3)
4912 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4913 ; P9BE-NEXT: blr
4914 ;
4915 ; P9LE-LABEL: fromDiffMemConsAConvdtoll:
4916 ; P9LE: # %bb.0: # %entry
4917 ; P9LE-NEXT: lxv vs0, 0(r3)
4918 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4919 ; P9LE-NEXT: blr
4920 ;
4921 ; P8BE-LABEL: fromDiffMemConsAConvdtoll:
4922 ; P8BE: # %bb.0: # %entry
4923 ; P8BE-NEXT: lxvd2x vs0, 0, r3
4924 ; P8BE-NEXT: xvcvdpsxds v2, vs0
4925 ; P8BE-NEXT: blr
4926 ;
4927 ; P8LE-LABEL: fromDiffMemConsAConvdtoll:
4928 ; P8LE: # %bb.0: # %entry
4929 ; P8LE-NEXT: lxvd2x vs0, 0, r3
4930 ; P8LE-NEXT: xxswapd vs0, vs0
4931 ; P8LE-NEXT: xvcvdpsxds v2, vs0
4932 ; P8LE-NEXT: blr
4933 entry:
4934 %0 = bitcast double* %ptr to <2 x double>*
4935 %1 = load <2 x double>, <2 x double>* %0, align 8
4936 %2 = fptosi <2 x double> %1 to <2 x i64>
4937 ret <2 x i64> %2
4938 }
4940 ; Function Attrs: norecurse nounwind readonly
4941 define <2 x i64> @fromDiffMemConsDConvdtoll(double* nocapture readonly %ptr) {
4942 ; P9BE-LABEL: fromDiffMemConsDConvdtoll:
4943 ; P9BE: # %bb.0: # %entry
4944 ; P9BE-NEXT: lxv vs0, 16(r3)
4945 ; P9BE-NEXT: xxswapd vs0, vs0
4946 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4947 ; P9BE-NEXT: blr
4948 ;
4949 ; P9LE-LABEL: fromDiffMemConsDConvdtoll:
4950 ; P9LE: # %bb.0: # %entry
4951 ; P9LE-NEXT: lxv vs0, 16(r3)
4952 ; P9LE-NEXT: xxswapd vs0, vs0
4953 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4954 ; P9LE-NEXT: blr
4955 ;
4956 ; P8BE-LABEL: fromDiffMemConsDConvdtoll:
4957 ; P8BE: # %bb.0: # %entry
4958 ; P8BE-NEXT: addi r3, r3, 16
4959 ; P8BE-NEXT: lxvd2x vs0, 0, r3
4960 ; P8BE-NEXT: xxswapd vs0, vs0
4961 ; P8BE-NEXT: xvcvdpsxds v2, vs0
4962 ; P8BE-NEXT: blr
4963 ;
4964 ; P8LE-LABEL: fromDiffMemConsDConvdtoll:
4965 ; P8LE: # %bb.0: # %entry
4966 ; P8LE-NEXT: addi r3, r3, 16
4967 ; P8LE-NEXT: lxvd2x vs0, 0, r3
4968 ; P8LE-NEXT: xvcvdpsxds v2, vs0
4969 ; P8LE-NEXT: blr
4970 entry:
4971 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3
4972 %0 = load double, double* %arrayidx, align 8
4973 %conv = fptosi double %0 to i64
4974 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4975 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2
4976 %1 = load double, double* %arrayidx1, align 8
4977 %conv2 = fptosi double %1 to i64
4978 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
4979 ret <2 x i64> %vecinit3
4980 }
4982 ; Function Attrs: norecurse nounwind readonly
4983 define <2 x i64> @fromDiffMemVarAConvdtoll(double* nocapture readonly %arr, i32 signext %elem) {
4984 ; P9BE-LABEL: fromDiffMemVarAConvdtoll:
4985 ; P9BE: # %bb.0: # %entry
4986 ; P9BE-NEXT: sldi r4, r4, 3
4987 ; P9BE-NEXT: lxvx vs0, r3, r4
4988 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4989 ; P9BE-NEXT: blr
4990 ;
4991 ; P9LE-LABEL: fromDiffMemVarAConvdtoll:
4992 ; P9LE: # %bb.0: # %entry
4993 ; P9LE-NEXT: sldi r4, r4, 3
4994 ; P9LE-NEXT: lxvx vs0, r3, r4
4995 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4996 ; P9LE-NEXT: blr
4997 ;
4998 ; P8BE-LABEL: fromDiffMemVarAConvdtoll:
4999 ; P8BE: # %bb.0: # %entry
5000 ; P8BE-NEXT: sldi r4, r4, 3
5001 ; P8BE-NEXT: lxvd2x vs0, r3, r4
5002 ; P8BE-NEXT: xvcvdpsxds v2, vs0
5003 ; P8BE-NEXT: blr
5004 ;
5005 ; P8LE-LABEL: fromDiffMemVarAConvdtoll:
5006 ; P8LE: # %bb.0: # %entry
5007 ; P8LE-NEXT: sldi r4, r4, 3
5008 ; P8LE-NEXT: lxvd2x vs0, r3, r4
5009 ; P8LE-NEXT: xxswapd vs0, vs0
5010 ; P8LE-NEXT: xvcvdpsxds v2, vs0
5011 ; P8LE-NEXT: blr
5012 entry:
5013 %idxprom = sext i32 %elem to i64
5014 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom
5015 %0 = load double, double* %arrayidx, align 8
5016 %conv = fptosi double %0 to i64
5017 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
5018 %add = add nsw i32 %elem, 1
5019 %idxprom1 = sext i32 %add to i64
5020 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1
5021 %1 = load double, double* %arrayidx2, align 8
5022 %conv3 = fptosi double %1 to i64
5023 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
5024 ret <2 x i64> %vecinit4
5025 }
5027 ; Function Attrs: norecurse nounwind readonly
5028 define <2 x i64> @fromDiffMemVarDConvdtoll(double* nocapture readonly %arr, i32 signext %elem) {
5029 ; P9BE-LABEL: fromDiffMemVarDConvdtoll:
5030 ; P9BE: # %bb.0: # %entry
5031 ; P9BE-NEXT: sldi r4, r4, 3
5032 ; P9BE-NEXT: add r3, r3, r4
5033 ; P9BE-NEXT: li r4, -8
5034 ; P9BE-NEXT: lxvx vs0, r3, r4
5035 ; P9BE-NEXT: xxswapd vs0, vs0
5036 ; P9BE-NEXT: xvcvdpsxds v2, vs0
5037 ; P9BE-NEXT: blr
5038 ;
5039 ; P9LE-LABEL: fromDiffMemVarDConvdtoll:
5040 ; P9LE: # %bb.0: # %entry
5041 ; P9LE-NEXT: sldi r4, r4, 3
5042 ; P9LE-NEXT: add r3, r3, r4
5043 ; P9LE-NEXT: li r4, -8
5044 ; P9LE-NEXT: lxvx vs0, r3, r4
5045 ; P9LE-NEXT: xxswapd vs0, vs0
5046 ; P9LE-NEXT: xvcvdpsxds v2, vs0
5047 ; P9LE-NEXT: blr
5048 ;
5049 ; P8BE-LABEL: fromDiffMemVarDConvdtoll:
5050 ; P8BE: # %bb.0: # %entry
5051 ; P8BE-NEXT: sldi r4, r4, 3
5052 ; P8BE-NEXT: add r3, r3, r4
5053 ; P8BE-NEXT: addi r3, r3, -8
5054 ; P8BE-NEXT: lxvd2x vs0, 0, r3
5055 ; P8BE-NEXT: xxswapd vs0, vs0
5056 ; P8BE-NEXT: xvcvdpsxds v2, vs0
5057 ; P8BE-NEXT: blr
5058 ;
5059 ; P8LE-LABEL: fromDiffMemVarDConvdtoll:
5060 ; P8LE: # %bb.0: # %entry
5061 ; P8LE-NEXT: sldi r4, r4, 3
5062 ; P8LE-NEXT: add r3, r3, r4
5063 ; P8LE-NEXT: addi r3, r3, -8
5064 ; P8LE-NEXT: lxvd2x vs0, 0, r3
5065 ; P8LE-NEXT: xvcvdpsxds v2, vs0
5066 ; P8LE-NEXT: blr
5067 entry:
5068 %idxprom = sext i32 %elem to i64
5069 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom
5070 %0 = load double, double* %arrayidx, align 8
5071 %conv = fptosi double %0 to i64
5072 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
5073 %sub = add nsw i32 %elem, -1
5074 %idxprom1 = sext i32 %sub to i64
5075 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1
5076 %1 = load double, double* %arrayidx2, align 8
5077 %conv3 = fptosi double %1 to i64
5078 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
5079 ret <2 x i64> %vecinit4
5080 }
5082 ; Function Attrs: norecurse nounwind readnone
5083 define <2 x i64> @spltRegValConvdtoll(double %val) {
5084 ; P9BE-LABEL: spltRegValConvdtoll:
5085 ; P9BE: # %bb.0: # %entry
5086 ; P9BE-NEXT: xscvdpsxds f0, f1
5087 ; P9BE-NEXT: xxspltd v2, vs0, 0
5088 ; P9BE-NEXT: blr
5089 ;
5090 ; P9LE-LABEL: spltRegValConvdtoll:
5091 ; P9LE: # %bb.0: # %entry
5092 ; P9LE-NEXT: xscvdpsxds f0, f1
5093 ; P9LE-NEXT: xxspltd v2, vs0, 0
5094 ; P9LE-NEXT: blr
5095 ;
5096 ; P8BE-LABEL: spltRegValConvdtoll:
5097 ; P8BE: # %bb.0: # %entry
5098 ; P8BE-NEXT: xscvdpsxds f0, f1
5099 ; P8BE-NEXT: xxspltd v2, vs0, 0
5100 ; P8BE-NEXT: blr
5101 ;
5102 ; P8LE-LABEL: spltRegValConvdtoll:
5103 ; P8LE: # %bb.0: # %entry
5104 ; P8LE-NEXT: xscvdpsxds f0, f1
5105 ; P8LE-NEXT: xxspltd v2, vs0, 0
5106 ; P8LE-NEXT: blr
5107 entry:
5108 %conv = fptosi double %val to i64
5109 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
5110 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
5111 ret <2 x i64> %splat.splat
5112 }
5114 ; Function Attrs: norecurse nounwind readonly
5115 define <2 x i64> @spltMemValConvdtoll(double* nocapture readonly %ptr) {
5116 ; P9BE-LABEL: spltMemValConvdtoll:
5117 ; P9BE: # %bb.0: # %entry
5118 ; P9BE-NEXT: lxvdsx vs0, 0, r3
5119 ; P9BE-NEXT: xvcvdpsxds v2, vs0
5120 ; P9BE-NEXT: blr
5121 ;
5122 ; P9LE-LABEL: spltMemValConvdtoll:
5123 ; P9LE: # %bb.0: # %entry
5124 ; P9LE-NEXT: lxvdsx vs0, 0, r3
5125 ; P9LE-NEXT: xvcvdpsxds v2, vs0
5126 ; P9LE-NEXT: blr
5127 ;
5128 ; P8BE-LABEL: spltMemValConvdtoll:
5129 ; P8BE: # %bb.0: # %entry
5130 ; P8BE-NEXT: lxvdsx vs0, 0, r3
5131 ; P8BE-NEXT: xvcvdpsxds v2, vs0
5132 ; P8BE-NEXT: blr
5133 ;
5134 ; P8LE-LABEL: spltMemValConvdtoll:
5135 ; P8LE: # %bb.0: # %entry
5136 ; P8LE-NEXT: lxvdsx vs0, 0, r3
5137 ; P8LE-NEXT: xvcvdpsxds v2, vs0
5138 ; P8LE-NEXT: blr
5139 entry:
5140 %0 = load double, double* %ptr, align 8
5141 %conv = fptosi double %0 to i64
5142 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
5143 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
5144 ret <2 x i64> %splat.splat
5145 }
5147 ; Function Attrs: norecurse nounwind readnone
5148 define <2 x i64> @allZeroull() {
5149 ; P9BE-LABEL: allZeroull:
5150 ; P9BE: # %bb.0: # %entry
5151 ; P9BE-NEXT: xxlxor v2, v2, v2
5152 ; P9BE-NEXT: blr
5153 ;
5154 ; P9LE-LABEL: allZeroull:
5155 ; P9LE: # %bb.0: # %entry
5156 ; P9LE-NEXT: xxlxor v2, v2, v2
5157 ; P9LE-NEXT: blr
5158 ;
5159 ; P8BE-LABEL: allZeroull:
5160 ; P8BE: # %bb.0: # %entry
5161 ; P8BE-NEXT: xxlxor v2, v2, v2
5162 ; P8BE-NEXT: blr
5163 ;
5164 ; P8LE-LABEL: allZeroull:
5165 ; P8LE: # %bb.0: # %entry
5166 ; P8LE-NEXT: xxlxor v2, v2, v2
5167 ; P8LE-NEXT: blr
5168 entry:
5169 ret <2 x i64> zeroinitializer
5170 }
5172 ; Function Attrs: norecurse nounwind readnone
5173 define <2 x i64> @allOneull() {
5174 ; P9BE-LABEL: allOneull:
5175 ; P9BE: # %bb.0: # %entry
5176 ; P9BE-NEXT: xxspltib v2, 255
5177 ; P9BE-NEXT: blr
5178 ;
5179 ; P9LE-LABEL: allOneull:
5180 ; P9LE: # %bb.0: # %entry
5181 ; P9LE-NEXT: xxspltib v2, 255
5182 ; P9LE-NEXT: blr
5183 ;
5184 ; P8BE-LABEL: allOneull:
5185 ; P8BE: # %bb.0: # %entry
5186 ; P8BE-NEXT: vspltisb v2, -1
5187 ; P8BE-NEXT: blr
5188 ;
5189 ; P8LE-LABEL: allOneull:
5190 ; P8LE: # %bb.0: # %entry
5191 ; P8LE-NEXT: vspltisb v2, -1
5192 ; P8LE-NEXT: blr
5193 entry:
5194 ret <2 x i64> <i64 -1, i64 -1>
5195 }
5197 ; Function Attrs: norecurse nounwind readnone
5198 define <2 x i64> @spltConst1ull() {
5199 ; P9BE-LABEL: spltConst1ull:
5200 ; P9BE: # %bb.0: # %entry
5201 ; P9BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha
5202 ; P9BE-NEXT: addi r3, r3, .LCPI101_0@toc@l
5203 ; P9BE-NEXT: lxvx v2, 0, r3
5204 ; P9BE-NEXT: blr
5205 ;
5206 ; P9LE-LABEL: spltConst1ull:
5207 ; P9LE: # %bb.0: # %entry
5208 ; P9LE-NEXT: addis r3, r2, .LCPI101_0@toc@ha
5209 ; P9LE-NEXT: addi r3, r3, .LCPI101_0@toc@l
5210 ; P9LE-NEXT: lxvx v2, 0, r3
5211 ; P9LE-NEXT: blr
5212 ;
5213 ; P8BE-LABEL: spltConst1ull:
5214 ; P8BE: # %bb.0: # %entry
5215 ; P8BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha
5216 ; P8BE-NEXT: addi r3, r3, .LCPI101_0@toc@l
5217 ; P8BE-NEXT: lxvd2x v2, 0, r3
5218 ; P8BE-NEXT: blr
5219 ;
5220 ; P8LE-LABEL: spltConst1ull:
5221 ; P8LE: # %bb.0: # %entry
5222 ; P8LE-NEXT: addis r3, r2, .LCPI101_0@toc@ha
5223 ; P8LE-NEXT: addi r3, r3, .LCPI101_0@toc@l
5224 ; P8LE-NEXT: lxvd2x vs0, 0, r3
5225 ; P8LE-NEXT: xxswapd v2, vs0
5226 ; P8LE-NEXT: blr
5227 entry:
5228 ret <2 x i64> <i64 1, i64 1>
5229 }
5231 ; Function Attrs: norecurse nounwind readnone
5232 define <2 x i64> @spltConst16kull() {
5233 ; P9BE-LABEL: spltConst16kull:
5234 ; P9BE: # %bb.0: # %entry
5235 ; P9BE-NEXT: addis r3, r2, .LCPI102_0@toc@ha
5236 ; P9BE-NEXT: addi r3, r3, .LCPI102_0@toc@l
5237 ; P9BE-NEXT: lxvx v2, 0, r3
5238 ; P9BE-NEXT: blr
5239 ;
5240 ; P9LE-LABEL: spltConst16kull:
5241 ; P9LE: # %bb.0: # %entry
5242 ; P9LE-NEXT: addis r3, r2, .LCPI102_0@toc@ha
5243 ; P9LE-NEXT: addi r3, r3, .LCPI102_0@toc@l
5244 ; P9LE-NEXT: lxvx v2, 0, r3
5245 ; P9LE-NEXT: blr
5246 ;
5247 ; P8BE-LABEL: spltConst16kull:
5248 ; P8BE: # %bb.0: # %entry
5249 ; P8BE-NEXT: addis r3, r2, .LCPI102_0@toc@ha
5250 ; P8BE-NEXT: addi r3, r3, .LCPI102_0@toc@l
5251 ; P8BE-NEXT: lxvd2x v2, 0, r3
5252 ; P8BE-NEXT: blr
5253 ;
5254 ; P8LE-LABEL: spltConst16kull:
5255 ; P8LE: # %bb.0: # %entry
5256 ; P8LE-NEXT: addis r3, r2, .LCPI102_0@toc@ha
5257 ; P8LE-NEXT: addi r3, r3, .LCPI102_0@toc@l
5258 ; P8LE-NEXT: lxvd2x vs0, 0, r3
5259 ; P8LE-NEXT: xxswapd v2, vs0
5260 ; P8LE-NEXT: blr
5261 entry:
5262 ret <2 x i64> <i64 32767, i64 32767>
5263 }
5265 ; Function Attrs: norecurse nounwind readnone
5266 define <2 x i64> @spltConst32kull() {
5267 ; P9BE-LABEL: spltConst32kull:
5268 ; P9BE: # %bb.0: # %entry
5269 ; P9BE-NEXT: addis r3, r2, .LCPI103_0@toc@ha
5270 ; P9BE-NEXT: addi r3, r3, .LCPI103_0@toc@l
5271 ; P9BE-NEXT: lxvx v2, 0, r3
5272 ; P9BE-NEXT: blr
5273 ;
5274 ; P9LE-LABEL: spltConst32kull:
5275 ; P9LE: # %bb.0: # %entry
5276 ; P9LE-NEXT: addis r3, r2, .LCPI103_0@toc@ha
5277 ; P9LE-NEXT: addi r3, r3, .LCPI103_0@toc@l
5278 ; P9LE-NEXT: lxvx v2, 0, r3
5279 ; P9LE-NEXT: blr
5280 ;
5281 ; P8BE-LABEL: spltConst32kull:
5282 ; P8BE: # %bb.0: # %entry
5283 ; P8BE-NEXT: addis r3, r2, .LCPI103_0@toc@ha
5284 ; P8BE-NEXT: addi r3, r3, .LCPI103_0@toc@l
5285 ; P8BE-NEXT: lxvd2x v2, 0, r3
5286 ; P8BE-NEXT: blr
5287 ;
5288 ; P8LE-LABEL: spltConst32kull:
5289 ; P8LE: # %bb.0: # %entry
5290 ; P8LE-NEXT: addis r3, r2, .LCPI103_0@toc@ha
5291 ; P8LE-NEXT: addi r3, r3, .LCPI103_0@toc@l
5292 ; P8LE-NEXT: lxvd2x vs0, 0, r3
5293 ; P8LE-NEXT: xxswapd v2, vs0
5294 ; P8LE-NEXT: blr
5295 entry:
5296 ret <2 x i64> <i64 65535, i64 65535>
5297 }
5299 ; Function Attrs: norecurse nounwind readnone
5300 define <2 x i64> @fromRegsull(i64 %a, i64 %b) {
5301 ; P9BE-LABEL: fromRegsull:
5302 ; P9BE: # %bb.0: # %entry
5303 ; P9BE-NEXT: mtvsrdd v2, r3, r4
5304 ; P9BE-NEXT: blr
5305 ;
5306 ; P9LE-LABEL: fromRegsull:
5307 ; P9LE: # %bb.0: # %entry
5308 ; P9LE-NEXT: mtvsrdd v2, r4, r3
5309 ; P9LE-NEXT: blr
5310 ;
5311 ; P8BE-LABEL: fromRegsull:
5312 ; P8BE: # %bb.0: # %entry
5313 ; P8BE-NEXT: mtvsrd f0, r4
5314 ; P8BE-NEXT: mtvsrd f1, r3
5315 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
5316 ; P8BE-NEXT: blr
5317 ;
5318 ; P8LE-LABEL: fromRegsull:
5319 ; P8LE: # %bb.0: # %entry
5320 ; P8LE-NEXT: mtvsrd f0, r3
5321 ; P8LE-NEXT: mtvsrd f1, r4
5322 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
5323 ; P8LE-NEXT: blr
5324 entry:
5325 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0
5326 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1
5327 ret <2 x i64> %vecinit1
5328 }
5330 ; Function Attrs: norecurse nounwind readnone
5331 define <2 x i64> @fromDiffConstsull() {
5332 ; P9BE-LABEL: fromDiffConstsull:
5333 ; P9BE: # %bb.0: # %entry
5334 ; P9BE-NEXT: addis r3, r2, .LCPI105_0@toc@ha
5335 ; P9BE-NEXT: addi r3, r3, .LCPI105_0@toc@l
5336 ; P9BE-NEXT: lxvx v2, 0, r3
5337 ; P9BE-NEXT: blr
5338 ;
5339 ; P9LE-LABEL: fromDiffConstsull:
5340 ; P9LE: # %bb.0: # %entry
5341 ; P9LE-NEXT: addis r3, r2, .LCPI105_0@toc@ha
5342 ; P9LE-NEXT: addi r3, r3, .LCPI105_0@toc@l
5343 ; P9LE-NEXT: lxvx v2, 0, r3
5344 ; P9LE-NEXT: blr
5345 ;
5346 ; P8BE-LABEL: fromDiffConstsull:
5347 ; P8BE: # %bb.0: # %entry
5348 ; P8BE-NEXT: addis r3, r2, .LCPI105_0@toc@ha
5349 ; P8BE-NEXT: addi r3, r3, .LCPI105_0@toc@l
5350 ; P8BE-NEXT: lxvd2x v2, 0, r3
5351 ; P8BE-NEXT: blr
5352 ;
5353 ; P8LE-LABEL: fromDiffConstsull:
5354 ; P8LE: # %bb.0: # %entry
5355 ; P8LE-NEXT: addis r3, r2, .LCPI105_0@toc@ha
5356 ; P8LE-NEXT: addi r3, r3, .LCPI105_0@toc@l
5357 ; P8LE-NEXT: lxvd2x vs0, 0, r3
5358 ; P8LE-NEXT: xxswapd v2, vs0
5359 ; P8LE-NEXT: blr
5360 entry:
5361 ret <2 x i64> <i64 242, i64 -113>
5362 }
5364 ; Function Attrs: norecurse nounwind readonly
5365 define <2 x i64> @fromDiffMemConsAull(i64* nocapture readonly %arr) {
5366 ; P9BE-LABEL: fromDiffMemConsAull:
5367 ; P9BE: # %bb.0: # %entry
5368 ; P9BE-NEXT: lxv v2, 0(r3)
5369 ; P9BE-NEXT: blr
5370 ;
5371 ; P9LE-LABEL: fromDiffMemConsAull:
5372 ; P9LE: # %bb.0: # %entry
5373 ; P9LE-NEXT: lxv v2, 0(r3)
5374 ; P9LE-NEXT: blr
5375 ;
5376 ; P8BE-LABEL: fromDiffMemConsAull:
5377 ; P8BE: # %bb.0: # %entry
5378 ; P8BE-NEXT: lxvd2x v2, 0, r3
5379 ; P8BE-NEXT: blr
5380 ;
5381 ; P8LE-LABEL: fromDiffMemConsAull:
5382 ; P8LE: # %bb.0: # %entry
5383 ; P8LE-NEXT: lxvd2x vs0, 0, r3
5384 ; P8LE-NEXT: xxswapd v2, vs0
5385 ; P8LE-NEXT: blr
5386 entry:
5387 %0 = load i64, i64* %arr, align 8
5388 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
5389 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 1
5390 %1 = load i64, i64* %arrayidx1, align 8
5391 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
5392 ret <2 x i64> %vecinit2
5393 }
5395 ; Function Attrs: norecurse nounwind readonly
5396 define <2 x i64> @fromDiffMemConsDull(i64* nocapture readonly %arr) {
5397 ; P9BE-LABEL: fromDiffMemConsDull:
5398 ; P9BE: # %bb.0: # %entry
5399 ; P9BE-NEXT: lxv v2, 16(r3)
5400 ; P9BE-NEXT: xxswapd v2, v2
5401 ; P9BE-NEXT: blr
5402 ;
5403 ; P9LE-LABEL: fromDiffMemConsDull:
5404 ; P9LE: # %bb.0: # %entry
5405 ; P9LE-NEXT: lxv v2, 16(r3)
5406 ; P9LE-NEXT: xxswapd v2, v2
5407 ; P9LE-NEXT: blr
5408 ;
5409 ; P8BE-LABEL: fromDiffMemConsDull:
5410 ; P8BE: # %bb.0: # %entry
5411 ; P8BE-NEXT: addi r3, r3, 16
5412 ; P8BE-NEXT: lxvd2x v2, 0, r3
5413 ; P8BE-NEXT: xxswapd v2, v2
5414 ; P8BE-NEXT: blr
5415 ;
5416 ; P8LE-LABEL: fromDiffMemConsDull:
5417 ; P8LE: # %bb.0: # %entry
5418 ; P8LE-NEXT: addi r3, r3, 16
5419 ; P8LE-NEXT: lxvd2x v2, 0, r3
5420 ; P8LE-NEXT: blr
5421 entry:
5422 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 3
5423 %0 = load i64, i64* %arrayidx, align 8
5424 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
5425 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 2
5426 %1 = load i64, i64* %arrayidx1, align 8
5427 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
5428 ret <2 x i64> %vecinit2
5429 }
5431 ; Function Attrs: norecurse nounwind readonly
5432 define <2 x i64> @fromDiffMemVarAull(i64* nocapture readonly %arr, i32 signext %elem) {
5433 ; P9BE-LABEL: fromDiffMemVarAull:
5434 ; P9BE: # %bb.0: # %entry
5435 ; P9BE-NEXT: sldi r4, r4, 3
5436 ; P9BE-NEXT: lxvx v2, r3, r4
5437 ; P9BE-NEXT: blr
5438 ;
5439 ; P9LE-LABEL: fromDiffMemVarAull:
5440 ; P9LE: # %bb.0: # %entry
5441 ; P9LE-NEXT: sldi r4, r4, 3
5442 ; P9LE-NEXT: lxvx v2, r3, r4
5443 ; P9LE-NEXT: blr
5444 ;
5445 ; P8BE-LABEL: fromDiffMemVarAull:
5446 ; P8BE: # %bb.0: # %entry
5447 ; P8BE-NEXT: sldi r4, r4, 3
5448 ; P8BE-NEXT: lxvd2x v2, r3, r4
5449 ; P8BE-NEXT: blr
5450 ;
5451 ; P8LE-LABEL: fromDiffMemVarAull:
5452 ; P8LE: # %bb.0: # %entry
5453 ; P8LE-NEXT: sldi r4, r4, 3
5454 ; P8LE-NEXT: lxvd2x vs0, r3, r4
5455 ; P8LE-NEXT: xxswapd v2, vs0
5456 ; P8LE-NEXT: blr
5457 entry:
5458 %idxprom = sext i32 %elem to i64
5459 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom
5460 %0 = load i64, i64* %arrayidx, align 8
5461 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
5462 %add = add nsw i32 %elem, 1
5463 %idxprom1 = sext i32 %add to i64
5464 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1
5465 %1 = load i64, i64* %arrayidx2, align 8
5466 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
5467 ret <2 x i64> %vecinit3
5468 }
5470 ; Function Attrs: norecurse nounwind readonly
5471 define <2 x i64> @fromDiffMemVarDull(i64* nocapture readonly %arr, i32 signext %elem) {
5472 ; P9BE-LABEL: fromDiffMemVarDull:
5473 ; P9BE: # %bb.0: # %entry
5474 ; P9BE-NEXT: sldi r4, r4, 3
5475 ; P9BE-NEXT: add r3, r3, r4
5476 ; P9BE-NEXT: li r4, -8
5477 ; P9BE-NEXT: lxvx v2, r3, r4
5478 ; P9BE-NEXT: xxswapd v2, v2
5479 ; P9BE-NEXT: blr
5480 ;
5481 ; P9LE-LABEL: fromDiffMemVarDull:
5482 ; P9LE: # %bb.0: # %entry
5483 ; P9LE-NEXT: sldi r4, r4, 3
5484 ; P9LE-NEXT: add r3, r3, r4
5485 ; P9LE-NEXT: li r4, -8
5486 ; P9LE-NEXT: lxvx v2, r3, r4
5487 ; P9LE-NEXT: xxswapd v2, v2
5488 ; P9LE-NEXT: blr
5489 ;
5490 ; P8BE-LABEL: fromDiffMemVarDull:
5491 ; P8BE: # %bb.0: # %entry
5492 ; P8BE-NEXT: sldi r4, r4, 3
5493 ; P8BE-NEXT: add r3, r3, r4
5494 ; P8BE-NEXT: addi r3, r3, -8
5495 ; P8BE-NEXT: lxvd2x v2, 0, r3
5496 ; P8BE-NEXT: xxswapd v2, v2
5497 ; P8BE-NEXT: blr
5498 ;
5499 ; P8LE-LABEL: fromDiffMemVarDull:
5500 ; P8LE: # %bb.0: # %entry
5501 ; P8LE-NEXT: sldi r4, r4, 3
5502 ; P8LE-NEXT: add r3, r3, r4
5503 ; P8LE-NEXT: addi r3, r3, -8
5504 ; P8LE-NEXT: lxvd2x v2, 0, r3
5505 ; P8LE-NEXT: blr
5506 entry:
5507 %idxprom = sext i32 %elem to i64
5508 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom
5509 %0 = load i64, i64* %arrayidx, align 8
5510 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
5511 %sub = add nsw i32 %elem, -1
5512 %idxprom1 = sext i32 %sub to i64
5513 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1
5514 %1 = load i64, i64* %arrayidx2, align 8
5515 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
5516 ret <2 x i64> %vecinit3
5517 }
5519 ; Function Attrs: norecurse nounwind readonly
5520 define <2 x i64> @fromRandMemConsull(i64* nocapture readonly %arr) {
5521 ; P9BE-LABEL: fromRandMemConsull:
5522 ; P9BE: # %bb.0: # %entry
5523 ; P9BE-NEXT: ld r4, 32(r3)
5524 ; P9BE-NEXT: ld r3, 144(r3)
5525 ; P9BE-NEXT: mtvsrdd v2, r4, r3
5526 ; P9BE-NEXT: blr
5527 ;
5528 ; P9LE-LABEL: fromRandMemConsull:
5529 ; P9LE: # %bb.0: # %entry
5530 ; P9LE-NEXT: ld r4, 32(r3)
5531 ; P9LE-NEXT: ld r3, 144(r3)
5532 ; P9LE-NEXT: mtvsrdd v2, r3, r4
5533 ; P9LE-NEXT: blr
5534 ;
5535 ; P8BE-LABEL: fromRandMemConsull:
5536 ; P8BE: # %bb.0: # %entry
5537 ; P8BE-NEXT: ld r4, 144(r3)
5538 ; P8BE-NEXT: ld r3, 32(r3)
5539 ; P8BE-NEXT: mtvsrd f0, r4
5540 ; P8BE-NEXT: mtvsrd f1, r3
5541 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
5542 ; P8BE-NEXT: blr
5543 ;
5544 ; P8LE-LABEL: fromRandMemConsull:
5545 ; P8LE: # %bb.0: # %entry
5546 ; P8LE-NEXT: ld r4, 32(r3)
5547 ; P8LE-NEXT: ld r3, 144(r3)
5548 ; P8LE-NEXT: mtvsrd f0, r4
5549 ; P8LE-NEXT: mtvsrd f1, r3
5550 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
5551 ; P8LE-NEXT: blr
5552 entry:
5553 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 4
5554 %0 = load i64, i64* %arrayidx, align 8
5555 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
5556 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 18
5557 %1 = load i64, i64* %arrayidx1, align 8
5558 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
5559 ret <2 x i64> %vecinit2
5560 }
5562 ; Function Attrs: norecurse nounwind readonly
5563 define <2 x i64> @fromRandMemVarull(i64* nocapture readonly %arr, i32 signext %elem) {
5564 ; P9BE-LABEL: fromRandMemVarull:
5565 ; P9BE: # %bb.0: # %entry
5566 ; P9BE-NEXT: sldi r4, r4, 3
5567 ; P9BE-NEXT: add r3, r3, r4
5568 ; P9BE-NEXT: ld r4, 32(r3)
5569 ; P9BE-NEXT: ld r3, 8(r3)
5570 ; P9BE-NEXT: mtvsrdd v2, r4, r3
5571 ; P9BE-NEXT: blr
5572 ;
5573 ; P9LE-LABEL: fromRandMemVarull:
5574 ; P9LE: # %bb.0: # %entry
5575 ; P9LE-NEXT: sldi r4, r4, 3
5576 ; P9LE-NEXT: add r3, r3, r4
5577 ; P9LE-NEXT: ld r4, 32(r3)
5578 ; P9LE-NEXT: ld r3, 8(r3)
5579 ; P9LE-NEXT: mtvsrdd v2, r3, r4
5580 ; P9LE-NEXT: blr
5581 ;
5582 ; P8BE-LABEL: fromRandMemVarull:
5583 ; P8BE: # %bb.0: # %entry
5584 ; P8BE-NEXT: sldi r4, r4, 3
5585 ; P8BE-NEXT: add r3, r3, r4
5586 ; P8BE-NEXT: ld r4, 8(r3)
5587 ; P8BE-NEXT: ld r3, 32(r3)
5588 ; P8BE-NEXT: mtvsrd f0, r4
5589 ; P8BE-NEXT: mtvsrd f1, r3
5590 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
5591 ; P8BE-NEXT: blr
5592 ;
5593 ; P8LE-LABEL: fromRandMemVarull:
5594 ; P8LE: # %bb.0: # %entry
5595 ; P8LE-NEXT: sldi r4, r4, 3
5596 ; P8LE-NEXT: add r3, r3, r4
5597 ; P8LE-NEXT: ld r4, 32(r3)
5598 ; P8LE-NEXT: ld r3, 8(r3)
5599 ; P8LE-NEXT: mtvsrd f0, r4
5600 ; P8LE-NEXT: mtvsrd f1, r3
5601 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
5602 ; P8LE-NEXT: blr
5603 entry:
5604 %add = add nsw i32 %elem, 4
5605 %idxprom = sext i32 %add to i64
5606 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom
5607 %0 = load i64, i64* %arrayidx, align 8
5608 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
5609 %add1 = add nsw i32 %elem, 1
5610 %idxprom2 = sext i32 %add1 to i64
5611 %arrayidx3 = getelementptr inbounds i64, i64* %arr, i64 %idxprom2
5612 %1 = load i64, i64* %arrayidx3, align 8
5613 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
5614 ret <2 x i64> %vecinit4
5615 }
5617 ; Function Attrs: norecurse nounwind readnone
5618 define <2 x i64> @spltRegValull(i64 %val) {
5619 ; P9BE-LABEL: spltRegValull:
5620 ; P9BE: # %bb.0: # %entry
5621 ; P9BE-NEXT: mtvsrdd v2, r3, r3
5622 ; P9BE-NEXT: blr
5623 ;
5624 ; P9LE-LABEL: spltRegValull:
5625 ; P9LE: # %bb.0: # %entry
5626 ; P9LE-NEXT: mtvsrdd v2, r3, r3
5627 ; P9LE-NEXT: blr
5628 ;
5629 ; P8BE-LABEL: spltRegValull:
5630 ; P8BE: # %bb.0: # %entry
5631 ; P8BE-NEXT: mtvsrd f0, r3
5632 ; P8BE-NEXT: xxspltd v2, vs0, 0
5633 ; P8BE-NEXT: blr
5634 ;
5635 ; P8LE-LABEL: spltRegValull:
5636 ; P8LE: # %bb.0: # %entry
5637 ; P8LE-NEXT: mtvsrd f0, r3
5638 ; P8LE-NEXT: xxspltd v2, vs0, 0
5639 ; P8LE-NEXT: blr
5640 entry:
5641 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0
5642 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
5643 ret <2 x i64> %splat.splat
5644 }
5646 ; Function Attrs: norecurse nounwind readonly
5647 define <2 x i64> @spltMemValull(i64* nocapture readonly %ptr) {
5648 ; P9BE-LABEL: spltMemValull:
5649 ; P9BE: # %bb.0: # %entry
5650 ; P9BE-NEXT: lxvdsx v2, 0, r3
5651 ; P9BE-NEXT: blr
5652 ;
5653 ; P9LE-LABEL: spltMemValull:
5654 ; P9LE: # %bb.0: # %entry
5655 ; P9LE-NEXT: lxvdsx v2, 0, r3
5656 ; P9LE-NEXT: blr
5657 ;
5658 ; P8BE-LABEL: spltMemValull:
5659 ; P8BE: # %bb.0: # %entry
5660 ; P8BE-NEXT: lxvdsx v2, 0, r3
5661 ; P8BE-NEXT: blr
5662 ;
5663 ; P8LE-LABEL: spltMemValull:
5664 ; P8LE: # %bb.0: # %entry
5665 ; P8LE-NEXT: lxvdsx v2, 0, r3
5666 ; P8LE-NEXT: blr
5667 entry:
5668 %0 = load i64, i64* %ptr, align 8
5669 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0
5670 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
5671 ret <2 x i64> %splat.splat
5672 }
5674 ; Function Attrs: norecurse nounwind readnone
5675 define <2 x i64> @spltCnstConvftoull() {
5676 ; P9BE-LABEL: spltCnstConvftoull:
5677 ; P9BE: # %bb.0: # %entry
5678 ; P9BE-NEXT: addis r3, r2, .LCPI114_0@toc@ha
5679 ; P9BE-NEXT: addi r3, r3, .LCPI114_0@toc@l
5680 ; P9BE-NEXT: lxvx v2, 0, r3
5681 ; P9BE-NEXT: blr
5682 ;
5683 ; P9LE-LABEL: spltCnstConvftoull:
5684 ; P9LE: # %bb.0: # %entry
5685 ; P9LE-NEXT: addis r3, r2, .LCPI114_0@toc@ha
5686 ; P9LE-NEXT: addi r3, r3, .LCPI114_0@toc@l
5687 ; P9LE-NEXT: lxvx v2, 0, r3
5688 ; P9LE-NEXT: blr
5689 ;
5690 ; P8BE-LABEL: spltCnstConvftoull:
5691 ; P8BE: # %bb.0: # %entry
5692 ; P8BE-NEXT: addis r3, r2, .LCPI114_0@toc@ha
5693 ; P8BE-NEXT: addi r3, r3, .LCPI114_0@toc@l
5694 ; P8BE-NEXT: lxvd2x v2, 0, r3
5695 ; P8BE-NEXT: blr
5696 ;
5697 ; P8LE-LABEL: spltCnstConvftoull:
5698 ; P8LE: # %bb.0: # %entry
5699 ; P8LE-NEXT: addis r3, r2, .LCPI114_0@toc@ha
5700 ; P8LE-NEXT: addi r3, r3, .LCPI114_0@toc@l
5701 ; P8LE-NEXT: lxvd2x vs0, 0, r3
5702 ; P8LE-NEXT: xxswapd v2, vs0
5703 ; P8LE-NEXT: blr
5704 entry:
5705 ret <2 x i64> <i64 4, i64 4>
5706 }
5708 ; Function Attrs: norecurse nounwind readnone
5709 define <2 x i64> @fromRegsConvftoull(float %a, float %b) {
5710 ; P9BE-LABEL: fromRegsConvftoull:
5711 ; P9BE: # %bb.0: # %entry
5712 ; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
5713 ; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
5714 ; P9BE-NEXT: xxmrghd vs0, vs1, vs2
5715 ; P9BE-NEXT: xvcvdpuxds v2, vs0
5716 ; P9BE-NEXT: blr
5717 ;
5718 ; P9LE-LABEL: fromRegsConvftoull:
5719 ; P9LE: # %bb.0: # %entry
5720 ; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
5721 ; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
5722 ; P9LE-NEXT: xxmrghd vs0, vs2, vs1
5723 ; P9LE-NEXT: xvcvdpuxds v2, vs0
5724 ; P9LE-NEXT: blr
5725 ;
5726 ; P8BE-LABEL: fromRegsConvftoull:
5727 ; P8BE: # %bb.0: # %entry
5728 ; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
5729 ; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
5730 ; P8BE-NEXT: xxmrghd vs0, vs1, vs2
5731 ; P8BE-NEXT: xvcvdpuxds v2, vs0
5732 ; P8BE-NEXT: blr
5733 ;
5734 ; P8LE-LABEL: fromRegsConvftoull:
5735 ; P8LE: # %bb.0: # %entry
5736 ; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
5737 ; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
5738 ; P8LE-NEXT: xxmrghd vs0, vs2, vs1
5739 ; P8LE-NEXT: xvcvdpuxds v2, vs0
5740 ; P8LE-NEXT: blr
5741 entry:
5742 %conv = fptoui float %a to i64
5743 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
5744 %conv1 = fptoui float %b to i64
5745 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1
5746 ret <2 x i64> %vecinit2
5747 }
5749 ; Function Attrs: norecurse nounwind readnone
5750 define <2 x i64> @fromDiffConstsConvftoull() {
5751 ; P9BE-LABEL: fromDiffConstsConvftoull:
5752 ; P9BE: # %bb.0: # %entry
5753 ; P9BE-NEXT: addis r3, r2, .LCPI116_0@toc@ha
5754 ; P9BE-NEXT: addi r3, r3, .LCPI116_0@toc@l
5755 ; P9BE-NEXT: lxvx v2, 0, r3
5756 ; P9BE-NEXT: blr
5757 ;
5758 ; P9LE-LABEL: fromDiffConstsConvftoull:
5759 ; P9LE: # %bb.0: # %entry
5760 ; P9LE-NEXT: addis r3, r2, .LCPI116_0@toc@ha
5761 ; P9LE-NEXT: addi r3, r3, .LCPI116_0@toc@l
5762 ; P9LE-NEXT: lxvx v2, 0, r3
5763 ; P9LE-NEXT: blr
5764 ;
5765 ; P8BE-LABEL: fromDiffConstsConvftoull:
5766 ; P8BE: # %bb.0: # %entry
5767 ; P8BE-NEXT: addis r3, r2, .LCPI116_0@toc@ha
5768 ; P8BE-NEXT: addi r3, r3, .LCPI116_0@toc@l
5769 ; P8BE-NEXT: lxvd2x v2, 0, r3
5770 ; P8BE-NEXT: blr
5771 ;
5772 ; P8LE-LABEL: fromDiffConstsConvftoull:
5773 ; P8LE: # %bb.0: # %entry
5774 ; P8LE-NEXT: addis r3, r2, .LCPI116_0@toc@ha
5775 ; P8LE-NEXT: addi r3, r3, .LCPI116_0@toc@l
5776 ; P8LE-NEXT: lxvd2x vs0, 0, r3
5777 ; P8LE-NEXT: xxswapd v2, vs0
5778 ; P8LE-NEXT: blr
5779 entry:
5780 ret <2 x i64> <i64 24, i64 234>
5781 }
5783 ; Function Attrs: norecurse nounwind readonly
5784 define <2 x i64> @fromDiffMemConsAConvftoull(float* nocapture readonly %ptr) {
5785 ; P9BE-LABEL: fromDiffMemConsAConvftoull:
5786 ; P9BE: # %bb.0: # %entry
5787 ; P9BE-NEXT: lfs f0, 0(r3)
5788 ; P9BE-NEXT: lfs f1, 4(r3)
5789 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
5790 ; P9BE-NEXT: xvcvdpuxds v2, vs0
5791 ; P9BE-NEXT: blr
5792 ;
5793 ; P9LE-LABEL: fromDiffMemConsAConvftoull:
5794 ; P9LE: # %bb.0: # %entry
5795 ; P9LE-NEXT: lfs f0, 0(r3)
5796 ; P9LE-NEXT: lfs f1, 4(r3)
5797 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
5798 ; P9LE-NEXT: xvcvdpuxds v2, vs0
5799 ; P9LE-NEXT: blr
5800 ;
5801 ; P8BE-LABEL: fromDiffMemConsAConvftoull:
5802 ; P8BE: # %bb.0: # %entry
5803 ; P8BE-NEXT: lfsx f0, 0, r3
5804 ; P8BE-NEXT: lfs f1, 4(r3)
5805 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
5806 ; P8BE-NEXT: xvcvdpuxds v2, vs0
5807 ; P8BE-NEXT: blr
5808 ;
5809 ; P8LE-LABEL: fromDiffMemConsAConvftoull:
5810 ; P8LE: # %bb.0: # %entry
5811 ; P8LE-NEXT: lfsx f0, 0, r3
5812 ; P8LE-NEXT: lfs f1, 4(r3)
5813 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
5814 ; P8LE-NEXT: xvcvdpuxds v2, vs0
5815 ; P8LE-NEXT: blr
5816 entry:
5817 %0 = load float, float* %ptr, align 4
5818 %conv = fptoui float %0 to i64
5819 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
5820 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 1
5821 %1 = load float, float* %arrayidx1, align 4
5822 %conv2 = fptoui float %1 to i64
5823 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
5824 ret <2 x i64> %vecinit3
5825 }
5827 ; Function Attrs: norecurse nounwind readonly
5828 define <2 x i64> @fromDiffMemConsDConvftoull(float* nocapture readonly %ptr) {
5829 ; P9BE-LABEL: fromDiffMemConsDConvftoull:
5830 ; P9BE: # %bb.0: # %entry
5831 ; P9BE-NEXT: lfs f0, 12(r3)
5832 ; P9BE-NEXT: lfs f1, 8(r3)
5833 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
5834 ; P9BE-NEXT: xvcvdpuxds v2, vs0
5835 ; P9BE-NEXT: blr
5836 ;
5837 ; P9LE-LABEL: fromDiffMemConsDConvftoull:
5838 ; P9LE: # %bb.0: # %entry
5839 ; P9LE-NEXT: lfs f0, 12(r3)
5840 ; P9LE-NEXT: lfs f1, 8(r3)
5841 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
5842 ; P9LE-NEXT: xvcvdpuxds v2, vs0
5843 ; P9LE-NEXT: blr
5844 ;
5845 ; P8BE-LABEL: fromDiffMemConsDConvftoull:
5846 ; P8BE: # %bb.0: # %entry
5847 ; P8BE-NEXT: lfs f0, 12(r3)
5848 ; P8BE-NEXT: lfs f1, 8(r3)
5849 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
5850 ; P8BE-NEXT: xvcvdpuxds v2, vs0
5851 ; P8BE-NEXT: blr
5852 ;
5853 ; P8LE-LABEL: fromDiffMemConsDConvftoull:
5854 ; P8LE: # %bb.0: # %entry
5855 ; P8LE-NEXT: lfs f0, 12(r3)
5856 ; P8LE-NEXT: lfs f1, 8(r3)
5857 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
5858 ; P8LE-NEXT: xvcvdpuxds v2, vs0
5859 ; P8LE-NEXT: blr
5860 entry:
5861 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3
5862 %0 = load float, float* %arrayidx, align 4
5863 %conv = fptoui float %0 to i64
5864 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
5865 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2
5866 %1 = load float, float* %arrayidx1, align 4
5867 %conv2 = fptoui float %1 to i64
5868 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
5869 ret <2 x i64> %vecinit3
5870 }
5872 ; Function Attrs: norecurse nounwind readonly
5873 define <2 x i64> @fromDiffMemVarAConvftoull(float* nocapture readonly %arr, i32 signext %elem) {
5874 ; P9BE-LABEL: fromDiffMemVarAConvftoull:
5875 ; P9BE: # %bb.0: # %entry
5876 ; P9BE-NEXT: sldi r4, r4, 2
5877 ; P9BE-NEXT: lfsux f0, r3, r4
5878 ; P9BE-NEXT: lfs f1, 4(r3)
5879 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
5880 ; P9BE-NEXT: xvcvdpuxds v2, vs0
5881 ; P9BE-NEXT: blr
5882 ;
5883 ; P9LE-LABEL: fromDiffMemVarAConvftoull:
5884 ; P9LE: # %bb.0: # %entry
5885 ; P9LE-NEXT: sldi r4, r4, 2
5886 ; P9LE-NEXT: lfsux f0, r3, r4
5887 ; P9LE-NEXT: lfs f1, 4(r3)
5888 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
5889 ; P9LE-NEXT: xvcvdpuxds v2, vs0
5890 ; P9LE-NEXT: blr
5891 ;
5892 ; P8BE-LABEL: fromDiffMemVarAConvftoull:
5893 ; P8BE: # %bb.0: # %entry
5894 ; P8BE-NEXT: sldi r4, r4, 2
5895 ; P8BE-NEXT: lfsux f0, r3, r4
5896 ; P8BE-NEXT: lfs f1, 4(r3)
5897 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
5898 ; P8BE-NEXT: xvcvdpuxds v2, vs0
5899 ; P8BE-NEXT: blr
5900 ;
5901 ; P8LE-LABEL: fromDiffMemVarAConvftoull:
5902 ; P8LE: # %bb.0: # %entry
5903 ; P8LE-NEXT: sldi r4, r4, 2
5904 ; P8LE-NEXT: lfsux f0, r3, r4
5905 ; P8LE-NEXT: lfs f1, 4(r3)
5906 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
5907 ; P8LE-NEXT: xvcvdpuxds v2, vs0
5908 ; P8LE-NEXT: blr
5909 entry:
5910 %idxprom = sext i32 %elem to i64
5911 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom
5912 %0 = load float, float* %arrayidx, align 4
5913 %conv = fptoui float %0 to i64
5914 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
5915 %add = add nsw i32 %elem, 1
5916 %idxprom1 = sext i32 %add to i64
5917 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1
5918 %1 = load float, float* %arrayidx2, align 4
5919 %conv3 = fptoui float %1 to i64
5920 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
5921 ret <2 x i64> %vecinit4
5922 }
5924 ; Function Attrs: norecurse nounwind readonly
5925 define <2 x i64> @fromDiffMemVarDConvftoull(float* nocapture readonly %arr, i32 signext %elem) {
5926 ; P9BE-LABEL: fromDiffMemVarDConvftoull:
5927 ; P9BE: # %bb.0: # %entry
5928 ; P9BE-NEXT: sldi r4, r4, 2
5929 ; P9BE-NEXT: lfsux f0, r3, r4
5930 ; P9BE-NEXT: lfs f1, -4(r3)
5931 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
5932 ; P9BE-NEXT: xvcvdpuxds v2, vs0
5933 ; P9BE-NEXT: blr
5934 ;
5935 ; P9LE-LABEL: fromDiffMemVarDConvftoull:
5936 ; P9LE: # %bb.0: # %entry
5937 ; P9LE-NEXT: sldi r4, r4, 2
5938 ; P9LE-NEXT: lfsux f0, r3, r4
5939 ; P9LE-NEXT: lfs f1, -4(r3)
5940 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
5941 ; P9LE-NEXT: xvcvdpuxds v2, vs0
5942 ; P9LE-NEXT: blr
5943 ;
5944 ; P8BE-LABEL: fromDiffMemVarDConvftoull:
5945 ; P8BE: # %bb.0: # %entry
5946 ; P8BE-NEXT: sldi r4, r4, 2
5947 ; P8BE-NEXT: lfsux f0, r3, r4
5948 ; P8BE-NEXT: lfs f1, -4(r3)
5949 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
5950 ; P8BE-NEXT: xvcvdpuxds v2, vs0
5951 ; P8BE-NEXT: blr
5952 ;
5953 ; P8LE-LABEL: fromDiffMemVarDConvftoull:
5954 ; P8LE: # %bb.0: # %entry
5955 ; P8LE-NEXT: sldi r4, r4, 2
5956 ; P8LE-NEXT: lfsux f0, r3, r4
5957 ; P8LE-NEXT: lfs f1, -4(r3)
5958 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
5959 ; P8LE-NEXT: xvcvdpuxds v2, vs0
5960 ; P8LE-NEXT: blr
5961 entry:
5962 %idxprom = sext i32 %elem to i64
5963 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom
5964 %0 = load float, float* %arrayidx, align 4
5965 %conv = fptoui float %0 to i64
5966 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
5967 %sub = add nsw i32 %elem, -1
5968 %idxprom1 = sext i32 %sub to i64
5969 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1
5970 %1 = load float, float* %arrayidx2, align 4
5971 %conv3 = fptoui float %1 to i64
5972 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
5973 ret <2 x i64> %vecinit4
5974 }
5976 ; Function Attrs: norecurse nounwind readnone
5977 define <2 x i64> @spltRegValConvftoull(float %val) {
5978 ; P9BE-LABEL: spltRegValConvftoull:
5979 ; P9BE: # %bb.0: # %entry
5980 ; P9BE-NEXT: xscvdpuxds f0, f1
5981 ; P9BE-NEXT: xxspltd v2, f0, 0
5982 ; P9BE-NEXT: blr
5983 ;
5984 ; P9LE-LABEL: spltRegValConvftoull:
5985 ; P9LE: # %bb.0: # %entry
5986 ; P9LE-NEXT: xscvdpuxds f0, f1
5987 ; P9LE-NEXT: xxspltd v2, f0, 0
5988 ; P9LE-NEXT: blr
5989 ;
5990 ; P8BE-LABEL: spltRegValConvftoull:
5991 ; P8BE: # %bb.0: # %entry
5992 ; P8BE-NEXT: xscvdpuxds f0, f1
5993 ; P8BE-NEXT: xxspltd v2, f0, 0
5994 ; P8BE-NEXT: blr
5995 ;
5996 ; P8LE-LABEL: spltRegValConvftoull:
5997 ; P8LE: # %bb.0: # %entry
5998 ; P8LE-NEXT: xscvdpuxds f0, f1
5999 ; P8LE-NEXT: xxspltd v2, f0, 0
6000 ; P8LE-NEXT: blr
6001 entry:
6002 %conv = fptoui float %val to i64
6003 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
6004 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
6005 ret <2 x i64> %splat.splat
6006 }
6008 ; Function Attrs: norecurse nounwind readonly
6009 define <2 x i64> @spltMemValConvftoull(float* nocapture readonly %ptr) {
6010 ; P9BE-LABEL: spltMemValConvftoull:
6011 ; P9BE: # %bb.0: # %entry
6012 ; P9BE-NEXT: lfs f0, 0(r3)
6013 ; P9BE-NEXT: xscvdpuxds f0, f0
6014 ; P9BE-NEXT: xxspltd v2, f0, 0
6015 ; P9BE-NEXT: blr
6016 ;
6017 ; P9LE-LABEL: spltMemValConvftoull:
6018 ; P9LE: # %bb.0: # %entry
6019 ; P9LE-NEXT: lfs f0, 0(r3)
6020 ; P9LE-NEXT: xscvdpuxds f0, f0
6021 ; P9LE-NEXT: xxspltd v2, f0, 0
6022 ; P9LE-NEXT: blr
6023 ;
6024 ; P8BE-LABEL: spltMemValConvftoull:
6025 ; P8BE: # %bb.0: # %entry
6026 ; P8BE-NEXT: lfsx f0, 0, r3
6027 ; P8BE-NEXT: xscvdpuxds f0, f0
6028 ; P8BE-NEXT: xxspltd v2, f0, 0
6029 ; P8BE-NEXT: blr
6030 ;
6031 ; P8LE-LABEL: spltMemValConvftoull:
6032 ; P8LE: # %bb.0: # %entry
6033 ; P8LE-NEXT: lfsx f0, 0, r3
6034 ; P8LE-NEXT: xscvdpuxds f0, f0
6035 ; P8LE-NEXT: xxspltd v2, f0, 0
6036 ; P8LE-NEXT: blr
6037 entry:
6038 %0 = load float, float* %ptr, align 4
6039 %conv = fptoui float %0 to i64
6040 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
6041 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
6042 ret <2 x i64> %splat.splat
6043 }
6045 ; Function Attrs: norecurse nounwind readnone
6046 define <2 x i64> @spltCnstConvdtoull() {
6047 ; P9BE-LABEL: spltCnstConvdtoull:
6048 ; P9BE: # %bb.0: # %entry
6049 ; P9BE-NEXT: addis r3, r2, .LCPI123_0@toc@ha
6050 ; P9BE-NEXT: addi r3, r3, .LCPI123_0@toc@l
6051 ; P9BE-NEXT: lxvx v2, 0, r3
6052 ; P9BE-NEXT: blr
6053 ;
6054 ; P9LE-LABEL: spltCnstConvdtoull:
6055 ; P9LE: # %bb.0: # %entry
6056 ; P9LE-NEXT: addis r3, r2, .LCPI123_0@toc@ha
6057 ; P9LE-NEXT: addi r3, r3, .LCPI123_0@toc@l
6058 ; P9LE-NEXT: lxvx v2, 0, r3
6059 ; P9LE-NEXT: blr
6060 ;
6061 ; P8BE-LABEL: spltCnstConvdtoull:
6062 ; P8BE: # %bb.0: # %entry
6063 ; P8BE-NEXT: addis r3, r2, .LCPI123_0@toc@ha
6064 ; P8BE-NEXT: addi r3, r3, .LCPI123_0@toc@l
6065 ; P8BE-NEXT: lxvd2x v2, 0, r3
6066 ; P8BE-NEXT: blr
6067 ;
6068 ; P8LE-LABEL: spltCnstConvdtoull:
6069 ; P8LE: # %bb.0: # %entry
6070 ; P8LE-NEXT: addis r3, r2, .LCPI123_0@toc@ha
6071 ; P8LE-NEXT: addi r3, r3, .LCPI123_0@toc@l
6072 ; P8LE-NEXT: lxvd2x vs0, 0, r3
6073 ; P8LE-NEXT: xxswapd v2, vs0
6074 ; P8LE-NEXT: blr
6075 entry:
6076 ret <2 x i64> <i64 4, i64 4>
6077 }
6079 ; Function Attrs: norecurse nounwind readnone
6080 define <2 x i64> @fromRegsConvdtoull(double %a, double %b) {
6081 ; P9BE-LABEL: fromRegsConvdtoull:
6082 ; P9BE: # %bb.0: # %entry
6083 ; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
6084 ; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
6085 ; P9BE-NEXT: xxmrghd vs0, vs1, vs2
6086 ; P9BE-NEXT: xvcvdpuxds v2, vs0
6087 ; P9BE-NEXT: blr
6088 ;
6089 ; P9LE-LABEL: fromRegsConvdtoull:
6090 ; P9LE: # %bb.0: # %entry
6091 ; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
6092 ; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
6093 ; P9LE-NEXT: xxmrghd vs0, vs2, vs1
6094 ; P9LE-NEXT: xvcvdpuxds v2, vs0
6095 ; P9LE-NEXT: blr
6096 ;
6097 ; P8BE-LABEL: fromRegsConvdtoull:
6098 ; P8BE: # %bb.0: # %entry
6099 ; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
6100 ; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
6101 ; P8BE-NEXT: xxmrghd vs0, vs1, vs2
6102 ; P8BE-NEXT: xvcvdpuxds v2, vs0
6103 ; P8BE-NEXT: blr
6104 ;
6105 ; P8LE-LABEL: fromRegsConvdtoull:
6106 ; P8LE: # %bb.0: # %entry
6107 ; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
6108 ; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
6109 ; P8LE-NEXT: xxmrghd vs0, vs2, vs1
6110 ; P8LE-NEXT: xvcvdpuxds v2, vs0
6111 ; P8LE-NEXT: blr
6112 entry:
6113 %conv = fptoui double %a to i64
6114 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
6115 %conv1 = fptoui double %b to i64
6116 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1
6117 ret <2 x i64> %vecinit2
6118 }
6120 ; Function Attrs: norecurse nounwind readnone
6121 define <2 x i64> @fromDiffConstsConvdtoull() {
6122 ; P9BE-LABEL: fromDiffConstsConvdtoull:
6123 ; P9BE: # %bb.0: # %entry
6124 ; P9BE-NEXT: addis r3, r2, .LCPI125_0@toc@ha
6125 ; P9BE-NEXT: addi r3, r3, .LCPI125_0@toc@l
6126 ; P9BE-NEXT: lxvx v2, 0, r3
6127 ; P9BE-NEXT: blr
6128 ;
6129 ; P9LE-LABEL: fromDiffConstsConvdtoull:
6130 ; P9LE: # %bb.0: # %entry
6131 ; P9LE-NEXT: addis r3, r2, .LCPI125_0@toc@ha
6132 ; P9LE-NEXT: addi r3, r3, .LCPI125_0@toc@l
6133 ; P9LE-NEXT: lxvx v2, 0, r3
6134 ; P9LE-NEXT: blr
6135 ;
6136 ; P8BE-LABEL: fromDiffConstsConvdtoull:
6137 ; P8BE: # %bb.0: # %entry
6138 ; P8BE-NEXT: addis r3, r2, .LCPI125_0@toc@ha
6139 ; P8BE-NEXT: addi r3, r3, .LCPI125_0@toc@l
6140 ; P8BE-NEXT: lxvd2x v2, 0, r3
6141 ; P8BE-NEXT: blr
6142 ;
6143 ; P8LE-LABEL: fromDiffConstsConvdtoull:
6144 ; P8LE: # %bb.0: # %entry
6145 ; P8LE-NEXT: addis r3, r2, .LCPI125_0@toc@ha
6146 ; P8LE-NEXT: addi r3, r3, .LCPI125_0@toc@l
6147 ; P8LE-NEXT: lxvd2x vs0, 0, r3
6148 ; P8LE-NEXT: xxswapd v2, vs0
6149 ; P8LE-NEXT: blr
6150 entry:
6151 ret <2 x i64> <i64 24, i64 234>
6152 }
6154 ; Function Attrs: norecurse nounwind readonly
6155 define <2 x i64> @fromDiffMemConsAConvdtoull(double* nocapture readonly %ptr) {
6156 ; P9BE-LABEL: fromDiffMemConsAConvdtoull:
6157 ; P9BE: # %bb.0: # %entry
6158 ; P9BE-NEXT: lxv vs0, 0(r3)
6159 ; P9BE-NEXT: xvcvdpuxds v2, vs0
6160 ; P9BE-NEXT: blr
6161 ;
6162 ; P9LE-LABEL: fromDiffMemConsAConvdtoull:
6163 ; P9LE: # %bb.0: # %entry
6164 ; P9LE-NEXT: lxv vs0, 0(r3)
6165 ; P9LE-NEXT: xvcvdpuxds v2, vs0
6166 ; P9LE-NEXT: blr
6167 ;
6168 ; P8BE-LABEL: fromDiffMemConsAConvdtoull:
6169 ; P8BE: # %bb.0: # %entry
6170 ; P8BE-NEXT: lxvd2x vs0, 0, r3
6171 ; P8BE-NEXT: xvcvdpuxds v2, vs0
6172 ; P8BE-NEXT: blr
6173 ;
6174 ; P8LE-LABEL: fromDiffMemConsAConvdtoull:
6175 ; P8LE: # %bb.0: # %entry
6176 ; P8LE-NEXT: lxvd2x vs0, 0, r3
6177 ; P8LE-NEXT: xxswapd vs0, vs0
6178 ; P8LE-NEXT: xvcvdpuxds v2, vs0
6179 ; P8LE-NEXT: blr
6180 entry:
6181 %0 = bitcast double* %ptr to <2 x double>*
6182 %1 = load <2 x double>, <2 x double>* %0, align 8
6183 %2 = fptoui <2 x double> %1 to <2 x i64>
6184 ret <2 x i64> %2
6185 }
6187 ; Function Attrs: norecurse nounwind readonly
6188 define <2 x i64> @fromDiffMemConsDConvdtoull(double* nocapture readonly %ptr) {
6189 ; P9BE-LABEL: fromDiffMemConsDConvdtoull:
6190 ; P9BE: # %bb.0: # %entry
6191 ; P9BE-NEXT: lxv vs0, 16(r3)
6192 ; P9BE-NEXT: xxswapd vs0, vs0
6193 ; P9BE-NEXT: xvcvdpuxds v2, vs0
6194 ; P9BE-NEXT: blr
6195 ;
6196 ; P9LE-LABEL: fromDiffMemConsDConvdtoull:
6197 ; P9LE: # %bb.0: # %entry
6198 ; P9LE-NEXT: lxv vs0, 16(r3)
6199 ; P9LE-NEXT: xxswapd vs0, vs0
6200 ; P9LE-NEXT: xvcvdpuxds v2, vs0
6201 ; P9LE-NEXT: blr
6202 ;
6203 ; P8BE-LABEL: fromDiffMemConsDConvdtoull:
6204 ; P8BE: # %bb.0: # %entry
6205 ; P8BE-NEXT: addi r3, r3, 16
6206 ; P8BE-NEXT: lxvd2x vs0, 0, r3
6207 ; P8BE-NEXT: xxswapd vs0, vs0
6208 ; P8BE-NEXT: xvcvdpuxds v2, vs0
6209 ; P8BE-NEXT: blr
6210 ;
6211 ; P8LE-LABEL: fromDiffMemConsDConvdtoull:
6212 ; P8LE: # %bb.0: # %entry
6213 ; P8LE-NEXT: addi r3, r3, 16
6214 ; P8LE-NEXT: lxvd2x vs0, 0, r3
6215 ; P8LE-NEXT: xvcvdpuxds v2, vs0
6216 ; P8LE-NEXT: blr
6217 entry:
6218 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3
6219 %0 = load double, double* %arrayidx, align 8
6220 %conv = fptoui double %0 to i64
6221 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
6222 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2
6223 %1 = load double, double* %arrayidx1, align 8
6224 %conv2 = fptoui double %1 to i64
6225 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
6226 ret <2 x i64> %vecinit3
6227 }
6229 ; Function Attrs: norecurse nounwind readonly
6230 define <2 x i64> @fromDiffMemVarAConvdtoull(double* nocapture readonly %arr, i32 signext %elem) {
6231 ; P9BE-LABEL: fromDiffMemVarAConvdtoull:
6232 ; P9BE: # %bb.0: # %entry
6233 ; P9BE-NEXT: sldi r4, r4, 3
6234 ; P9BE-NEXT: lxvx vs0, r3, r4
6235 ; P9BE-NEXT: xvcvdpuxds v2, vs0
6236 ; P9BE-NEXT: blr
6237 ;
6238 ; P9LE-LABEL: fromDiffMemVarAConvdtoull:
6239 ; P9LE: # %bb.0: # %entry
6240 ; P9LE-NEXT: sldi r4, r4, 3
6241 ; P9LE-NEXT: lxvx vs0, r3, r4
6242 ; P9LE-NEXT: xvcvdpuxds v2, vs0
6243 ; P9LE-NEXT: blr
6244 ;
6245 ; P8BE-LABEL: fromDiffMemVarAConvdtoull:
6246 ; P8BE: # %bb.0: # %entry
6247 ; P8BE-NEXT: sldi r4, r4, 3
6248 ; P8BE-NEXT: lxvd2x vs0, r3, r4
6249 ; P8BE-NEXT: xvcvdpuxds v2, vs0
6250 ; P8BE-NEXT: blr
6251 ;
6252 ; P8LE-LABEL: fromDiffMemVarAConvdtoull:
6253 ; P8LE: # %bb.0: # %entry
6254 ; P8LE-NEXT: sldi r4, r4, 3
6255 ; P8LE-NEXT: lxvd2x vs0, r3, r4
6256 ; P8LE-NEXT: xxswapd vs0, vs0
6257 ; P8LE-NEXT: xvcvdpuxds v2, vs0
6258 ; P8LE-NEXT: blr
6259 entry:
6260 %idxprom = sext i32 %elem to i64
6261 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom
6262 %0 = load double, double* %arrayidx, align 8
6263 %conv = fptoui double %0 to i64
6264 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
6265 %add = add nsw i32 %elem, 1
6266 %idxprom1 = sext i32 %add to i64
6267 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1
6268 %1 = load double, double* %arrayidx2, align 8
6269 %conv3 = fptoui double %1 to i64
6270 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
6271 ret <2 x i64> %vecinit4
6272 }
6274 ; Function Attrs: norecurse nounwind readonly
6275 define <2 x i64> @fromDiffMemVarDConvdtoull(double* nocapture readonly %arr, i32 signext %elem) {
6276 ; P9BE-LABEL: fromDiffMemVarDConvdtoull:
6277 ; P9BE: # %bb.0: # %entry
6278 ; P9BE-NEXT: sldi r4, r4, 3
6279 ; P9BE-NEXT: add r3, r3, r4
6280 ; P9BE-NEXT: li r4, -8
6281 ; P9BE-NEXT: lxvx vs0, r3, r4
6282 ; P9BE-NEXT: xxswapd vs0, vs0
6283 ; P9BE-NEXT: xvcvdpuxds v2, vs0
6284 ; P9BE-NEXT: blr
6285 ;
6286 ; P9LE-LABEL: fromDiffMemVarDConvdtoull:
6287 ; P9LE: # %bb.0: # %entry
6288 ; P9LE-NEXT: sldi r4, r4, 3
6289 ; P9LE-NEXT: add r3, r3, r4
6290 ; P9LE-NEXT: li r4, -8
6291 ; P9LE-NEXT: lxvx vs0, r3, r4
6292 ; P9LE-NEXT: xxswapd vs0, vs0
6293 ; P9LE-NEXT: xvcvdpuxds v2, vs0
6294 ; P9LE-NEXT: blr
6295 ;
6296 ; P8BE-LABEL: fromDiffMemVarDConvdtoull:
6297 ; P8BE: # %bb.0: # %entry
6298 ; P8BE-NEXT: sldi r4, r4, 3
6299 ; P8BE-NEXT: add r3, r3, r4
6300 ; P8BE-NEXT: addi r3, r3, -8
6301 ; P8BE-NEXT: lxvd2x vs0, 0, r3
6302 ; P8BE-NEXT: xxswapd vs0, vs0
6303 ; P8BE-NEXT: xvcvdpuxds v2, vs0
6304 ; P8BE-NEXT: blr
6305 ;
6306 ; P8LE-LABEL: fromDiffMemVarDConvdtoull:
6307 ; P8LE: # %bb.0: # %entry
6308 ; P8LE-NEXT: sldi r4, r4, 3
6309 ; P8LE-NEXT: add r3, r3, r4
6310 ; P8LE-NEXT: addi r3, r3, -8
6311 ; P8LE-NEXT: lxvd2x vs0, 0, r3
6312 ; P8LE-NEXT: xvcvdpuxds v2, vs0
6313 ; P8LE-NEXT: blr
6314 entry:
6315 %idxprom = sext i32 %elem to i64
6316 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom
6317 %0 = load double, double* %arrayidx, align 8
6318 %conv = fptoui double %0 to i64
6319 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
6320 %sub = add nsw i32 %elem, -1
6321 %idxprom1 = sext i32 %sub to i64
6322 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1
6323 %1 = load double, double* %arrayidx2, align 8
6324 %conv3 = fptoui double %1 to i64
6325 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
6326 ret <2 x i64> %vecinit4
6327 }
6329 ; Function Attrs: norecurse nounwind readnone
6330 define <2 x i64> @spltRegValConvdtoull(double %val) {
6331 ; P9BE-LABEL: spltRegValConvdtoull:
6332 ; P9BE: # %bb.0: # %entry
6333 ; P9BE-NEXT: xscvdpuxds f0, f1
6334 ; P9BE-NEXT: xxspltd v2, vs0, 0
6335 ; P9BE-NEXT: blr
6336 ;
6337 ; P9LE-LABEL: spltRegValConvdtoull:
6338 ; P9LE: # %bb.0: # %entry
6339 ; P9LE-NEXT: xscvdpuxds f0, f1
6340 ; P9LE-NEXT: xxspltd v2, vs0, 0
6341 ; P9LE-NEXT: blr
6342 ;
6343 ; P8BE-LABEL: spltRegValConvdtoull:
6344 ; P8BE: # %bb.0: # %entry
6345 ; P8BE-NEXT: xscvdpuxds f0, f1
6346 ; P8BE-NEXT: xxspltd v2, vs0, 0
6347 ; P8BE-NEXT: blr
6348 ;
6349 ; P8LE-LABEL: spltRegValConvdtoull:
6350 ; P8LE: # %bb.0: # %entry
6351 ; P8LE-NEXT: xscvdpuxds f0, f1
6352 ; P8LE-NEXT: xxspltd v2, vs0, 0
6353 ; P8LE-NEXT: blr
6354 entry:
6355 %conv = fptoui double %val to i64
6356 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
6357 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
6358 ret <2 x i64> %splat.splat
6359 }
6361 ; Function Attrs: norecurse nounwind readonly
6362 define <2 x i64> @spltMemValConvdtoull(double* nocapture readonly %ptr) {
6363 ; P9BE-LABEL: spltMemValConvdtoull:
6364 ; P9BE: # %bb.0: # %entry
6365 ; P9BE-NEXT: lxvdsx vs0, 0, r3
6366 ; P9BE-NEXT: xvcvdpuxds v2, vs0
6367 ; P9BE-NEXT: blr
6368 ;
6369 ; P9LE-LABEL: spltMemValConvdtoull:
6370 ; P9LE: # %bb.0: # %entry
6371 ; P9LE-NEXT: lxvdsx vs0, 0, r3
6372 ; P9LE-NEXT: xvcvdpuxds v2, vs0
6373 ; P9LE-NEXT: blr
6374 ;
6375 ; P8BE-LABEL: spltMemValConvdtoull:
6376 ; P8BE: # %bb.0: # %entry
6377 ; P8BE-NEXT: lxvdsx vs0, 0, r3
6378 ; P8BE-NEXT: xvcvdpuxds v2, vs0
6379 ; P8BE-NEXT: blr
6380 ;
6381 ; P8LE-LABEL: spltMemValConvdtoull:
6382 ; P8LE: # %bb.0: # %entry
6383 ; P8LE-NEXT: lxvdsx vs0, 0, r3
6384 ; P8LE-NEXT: xvcvdpuxds v2, vs0
6385 ; P8LE-NEXT: blr
6386 entry:
6387 %0 = load double, double* %ptr, align 8
6388 %conv = fptoui double %0 to i64
6389 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
6390 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
6391 ret <2 x i64> %splat.splat
6392 }