1 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \
2 ; RUN: -verify-machineinstrs < %s | FileCheck %s
3 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu \
4 ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-BE
6 define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
8 ; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_
10 ; CHECK: xxinsertw 34, 0, 12
11 ; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_
12 ; CHECK-BE: xxsldwi 0, 35, 35, 3
13 ; CHECK-BE: xxinsertw 34, 0, 0
14 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
15 ret <4 x float> %vecins
18 define <4 x float> @_Z7testInsILj0ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
20 ; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_
21 ; CHECK: xxsldwi 0, 35, 35, 1
22 ; CHECK: xxinsertw 34, 0, 12
23 ; CHECK-BE-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_
24 ; CHECK-BE-NOT: xxsldwi
25 ; CHECK-BE: xxinsertw 34, 35, 0
26 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 5, i32 1, i32 2, i32 3>
27 ret <4 x float> %vecins
30 define <4 x float> @_Z7testInsILj0ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
32 ; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_
34 ; CHECK: xxinsertw 34, 35, 12
35 ; CHECK-BE-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_
36 ; CHECK-BE: xxsldwi 0, 35, 35, 1
37 ; CHECK-BE: xxinsertw 34, 0, 0
38 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 6, i32 1, i32 2, i32 3>
39 ret <4 x float> %vecins
42 define <4 x float> @_Z7testInsILj0ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
44 ; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_
45 ; CHECK: xxsldwi 0, 35, 35, 3
46 ; CHECK: xxinsertw 34, 0, 12
47 ; CHECK-BE-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_
48 ; CHECK-BE: xxswapd 0, 35
49 ; CHECK-BE: xxinsertw 34, 0, 0
50 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 7, i32 1, i32 2, i32 3>
51 ret <4 x float> %vecins
54 define <4 x float> @_Z7testInsILj1ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
56 ; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_
57 ; CHECK: xxswapd 0, 35
58 ; CHECK: xxinsertw 34, 0, 8
59 ; CHECK-BE-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_
60 ; CHECK-BE: xxsldwi 0, 35, 35, 3
61 ; CHECK-BE: xxinsertw 34, 0, 4
62 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 3>
63 ret <4 x float> %vecins
66 define <4 x float> @_Z7testInsILj1ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
68 ; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_
69 ; CHECK: xxsldwi 0, 35, 35, 1
70 ; CHECK: xxinsertw 34, 0, 8
71 ; CHECK-BE-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_
72 ; CHECK-BE-NOT: xxsldwi
73 ; CHECK-BE: xxinsertw 34, 35, 4
74 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
75 ret <4 x float> %vecins
78 define <4 x float> @_Z7testInsILj1ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
80 ; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_
82 ; CHECK: xxinsertw 34, 35, 8
83 ; CHECK-BE-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_
84 ; CHECK-BE: xxsldwi 0, 35, 35, 1
85 ; CHECK-BE: xxinsertw 34, 0, 4
86 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
87 ret <4 x float> %vecins
90 define <4 x float> @_Z7testInsILj1ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
92 ; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_
93 ; CHECK: xxsldwi 0, 35, 35, 3
94 ; CHECK: xxinsertw 34, 0, 8
95 ; CHECK-BE-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_
96 ; CHECK-BE: xxswapd 0, 35
97 ; CHECK-BE: xxinsertw 34, 0, 4
98 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 3>
99 ret <4 x float> %vecins
102 define <4 x float> @_Z7testInsILj2ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
104 ; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_
105 ; CHECK: xxswapd 0, 35
106 ; CHECK: xxinsertw 34, 0, 4
107 ; CHECK-BE-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_
108 ; CHECK-BE: xxsldwi 0, 35, 35, 3
109 ; CHECK-BE: xxinsertw 34, 0, 8
110 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 3>
111 ret <4 x float> %vecins
114 define <4 x float> @_Z7testInsILj2ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
116 ; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_
117 ; CHECK: xxsldwi 0, 35, 35, 1
118 ; CHECK: xxinsertw 34, 0, 4
119 ; CHECK-BE-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_
120 ; CHECK-BE-NOT: xxsldwi
121 ; CHECK-BE: xxinsertw 34, 35, 8
122 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 5, i32 3>
123 ret <4 x float> %vecins
126 define <4 x float> @_Z7testInsILj2ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
128 ; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_
130 ; CHECK: xxinsertw 34, 35, 4
131 ; CHECK-BE-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_
132 ; CHECK-BE: xxsldwi 0, 35, 35, 1
133 ; CHECK-BE: xxinsertw 34, 0, 8
134 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
135 ret <4 x float> %vecins
138 define <4 x float> @_Z7testInsILj2ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
140 ; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_
141 ; CHECK: xxsldwi 0, 35, 35, 3
142 ; CHECK: xxinsertw 34, 0, 4
143 ; CHECK-BE-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_
144 ; CHECK-BE: xxswapd 0, 35
145 ; CHECK-BE: xxinsertw 34, 0, 8
146 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 7, i32 3>
147 ret <4 x float> %vecins
150 define <4 x float> @_Z7testInsILj3ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
152 ; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_
153 ; CHECK: xxswapd 0, 35
154 ; CHECK: xxinsertw 34, 0, 0
155 ; CHECK-BE-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_
156 ; CHECK-BE: xxsldwi 0, 35, 35, 3
157 ; CHECK-BE: xxinsertw 34, 0, 12
158 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
159 ret <4 x float> %vecins
162 define <4 x float> @_Z7testInsILj3ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
164 ; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_
165 ; CHECK: xxsldwi 0, 35, 35, 1
166 ; CHECK: xxinsertw 34, 0, 0
167 ; CHECK-BE-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_
168 ; CHECK-BE-NOT: xxsldwi
169 ; CHECK-BE: xxinsertw 34, 35, 12
170 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
171 ret <4 x float> %vecins
174 define <4 x float> @_Z7testInsILj3ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
176 ; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_
178 ; CHECK: xxinsertw 34, 35, 0
179 ; CHECK-BE-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_
180 ; CHECK-BE: xxsldwi 0, 35, 35, 1
181 ; CHECK-BE: xxinsertw 34, 0, 12
182 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
183 ret <4 x float> %vecins
186 define <4 x float> @_Z7testInsILj3ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
188 ; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_
189 ; CHECK: xxsldwi 0, 35, 35, 3
190 ; CHECK: xxinsertw 34, 0, 0
191 ; CHECK-BE-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_
192 ; CHECK-BE: xxswapd 0, 35
193 ; CHECK-BE: xxinsertw 34, 0, 12
194 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
195 ret <4 x float> %vecins
198 define <4 x i32> @_Z7testInsILj0ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
200 ; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_
201 ; CHECK: xxswapd 0, 35
202 ; CHECK: xxinsertw 34, 0, 12
203 ; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_
204 ; CHECK-BE: xxsldwi 0, 35, 35, 3
205 ; CHECK-BE: xxinsertw 34, 0, 0
206 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
207 ret <4 x i32> %vecins
210 define <4 x i32> @_Z7testInsILj0ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
212 ; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_
213 ; CHECK: xxsldwi 0, 35, 35, 1
214 ; CHECK: xxinsertw 34, 0, 12
215 ; CHECK-BE-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_
216 ; CHECK-BE-NOT: xxsldwi
217 ; CHECK-BE: xxinsertw 34, 35, 0
218 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 5, i32 1, i32 2, i32 3>
219 ret <4 x i32> %vecins
222 define <4 x i32> @_Z7testInsILj0ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
224 ; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_
226 ; CHECK: xxinsertw 34, 35, 12
227 ; CHECK-BE-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_
228 ; CHECK-BE: xxsldwi 0, 35, 35, 1
229 ; CHECK-BE: xxinsertw 34, 0, 0
230 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 6, i32 1, i32 2, i32 3>
231 ret <4 x i32> %vecins
234 define <4 x i32> @_Z7testInsILj0ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
236 ; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_
237 ; CHECK: xxsldwi 0, 35, 35, 3
238 ; CHECK: xxinsertw 34, 0, 12
239 ; CHECK-BE-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_
240 ; CHECK-BE: xxswapd 0, 35
241 ; CHECK-BE: xxinsertw 34, 0, 0
242 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 7, i32 1, i32 2, i32 3>
243 ret <4 x i32> %vecins
246 define <4 x i32> @_Z7testInsILj1ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
248 ; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_
249 ; CHECK: xxswapd 0, 35
250 ; CHECK: xxinsertw 34, 0, 8
251 ; CHECK-BE-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_
252 ; CHECK-BE: xxsldwi 0, 35, 35, 3
253 ; CHECK-BE: xxinsertw 34, 0, 4
254 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 3>
255 ret <4 x i32> %vecins
258 define <4 x i32> @_Z7testInsILj1ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
260 ; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_
261 ; CHECK: xxsldwi 0, 35, 35, 1
262 ; CHECK: xxinsertw 34, 0, 8
263 ; CHECK-BE-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_
264 ; CHECK-BE-NOT: xxsldwi
265 ; CHECK-BE: xxinsertw 34, 35, 4
266 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
267 ret <4 x i32> %vecins
270 define <4 x i32> @_Z7testInsILj1ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
272 ; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_
274 ; CHECK: xxinsertw 34, 35, 8
275 ; CHECK-BE-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_
276 ; CHECK-BE: xxsldwi 0, 35, 35, 1
277 ; CHECK-BE: xxinsertw 34, 0, 4
278 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
279 ret <4 x i32> %vecins
282 define <4 x i32> @_Z7testInsILj1ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
284 ; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_
285 ; CHECK: xxsldwi 0, 35, 35, 3
286 ; CHECK: xxinsertw 34, 0, 8
287 ; CHECK-BE-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_
288 ; CHECK-BE: xxswapd 0, 35
289 ; CHECK-BE: xxinsertw 34, 0, 4
290 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 3>
291 ret <4 x i32> %vecins
294 define <4 x i32> @_Z7testInsILj2ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
296 ; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_
297 ; CHECK: xxswapd 0, 35
298 ; CHECK: xxinsertw 34, 0, 4
299 ; CHECK-BE-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_
300 ; CHECK-BE: xxsldwi 0, 35, 35, 3
301 ; CHECK-BE: xxinsertw 34, 0, 8
302 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 3>
303 ret <4 x i32> %vecins
306 define <4 x i32> @_Z7testInsILj2ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
308 ; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_
309 ; CHECK: xxsldwi 0, 35, 35, 1
310 ; CHECK: xxinsertw 34, 0, 4
311 ; CHECK-BE-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_
312 ; CHECK-BE-NOT: xxsldwi
313 ; CHECK-BE: xxinsertw 34, 35, 8
314 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 5, i32 3>
315 ret <4 x i32> %vecins
318 define <4 x i32> @_Z7testInsILj2ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
320 ; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_
322 ; CHECK: xxinsertw 34, 35, 4
323 ; CHECK-BE-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_
324 ; CHECK-BE: xxsldwi 0, 35, 35, 1
325 ; CHECK-BE: xxinsertw 34, 0, 8
326 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
327 ret <4 x i32> %vecins
330 define <4 x i32> @_Z7testInsILj2ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
332 ; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_
333 ; CHECK: xxsldwi 0, 35, 35, 3
334 ; CHECK: xxinsertw 34, 0, 4
335 ; CHECK-BE-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_
336 ; CHECK-BE: xxswapd 0, 35
337 ; CHECK-BE: xxinsertw 34, 0, 8
338 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 7, i32 3>
339 ret <4 x i32> %vecins
342 define <4 x i32> @_Z7testInsILj3ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
344 ; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_
345 ; CHECK: xxswapd 0, 35
346 ; CHECK: xxinsertw 34, 0, 0
347 ; CHECK-BE-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_
348 ; CHECK-BE: xxsldwi 0, 35, 35, 3
349 ; CHECK-BE: xxinsertw 34, 0, 12
350 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
351 ret <4 x i32> %vecins
354 define <4 x i32> @_Z7testInsILj3ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
356 ; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_
357 ; CHECK: xxsldwi 0, 35, 35, 1
358 ; CHECK: xxinsertw 34, 0, 0
359 ; CHECK-BE-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_
360 ; CHECK-BE-NOT: xxsldwi
361 ; CHECK-BE: xxinsertw 34, 35, 12
362 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
363 ret <4 x i32> %vecins
366 define <4 x i32> @_Z7testInsILj3ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
368 ; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_
370 ; CHECK: xxinsertw 34, 35, 0
371 ; CHECK-BE-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_
372 ; CHECK-BE: xxsldwi 0, 35, 35, 1
373 ; CHECK-BE: xxinsertw 34, 0, 12
374 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
375 ret <4 x i32> %vecins
378 define <4 x i32> @_Z7testInsILj3ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
380 ; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_
381 ; CHECK: xxsldwi 0, 35, 35, 3
382 ; CHECK: xxinsertw 34, 0, 0
383 ; CHECK-BE-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_
384 ; CHECK-BE: xxswapd 0, 35
385 ; CHECK-BE: xxinsertw 34, 0, 12
386 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
387 ret <4 x i32> %vecins
390 define float @_Z13testUiToFpExtILj0EEfDv4_j(<4 x i32> %a) {
392 ; CHECK-LABEL: _Z13testUiToFpExtILj0EEfDv4_j
393 ; CHECK: xxextractuw 0, 34, 12
394 ; CHECK: xscvuxdsp 1, 0
395 ; CHECK-BE-LABEL: _Z13testUiToFpExtILj0EEfDv4_j
396 ; CHECK-BE: xxextractuw 0, 34, 0
397 ; CHECK-BE: xscvuxdsp 1, 0
398 %vecext = extractelement <4 x i32> %a, i32 0
399 %conv = uitofp i32 %vecext to float
403 define float @_Z13testUiToFpExtILj1EEfDv4_j(<4 x i32> %a) {
405 ; CHECK-LABEL: _Z13testUiToFpExtILj1EEfDv4_j
406 ; CHECK: xxextractuw 0, 34, 8
407 ; CHECK: xscvuxdsp 1, 0
408 ; CHECK-BE-LABEL: _Z13testUiToFpExtILj1EEfDv4_j
409 ; CHECK-BE: xxextractuw 0, 34, 4
410 ; CHECK-BE: xscvuxdsp 1, 0
411 %vecext = extractelement <4 x i32> %a, i32 1
412 %conv = uitofp i32 %vecext to float
416 define float @_Z13testUiToFpExtILj2EEfDv4_j(<4 x i32> %a) {
418 ; CHECK-LABEL: _Z13testUiToFpExtILj2EEfDv4_j
419 ; CHECK: xxextractuw 0, 34, 4
420 ; CHECK: xscvuxdsp 1, 0
421 ; CHECK-BE-LABEL: _Z13testUiToFpExtILj2EEfDv4_j
422 ; CHECK-BE: xxextractuw 0, 34, 8
423 ; CHECK-BE: xscvuxdsp 1, 0
424 %vecext = extractelement <4 x i32> %a, i32 2
425 %conv = uitofp i32 %vecext to float
429 define float @_Z13testUiToFpExtILj3EEfDv4_j(<4 x i32> %a) {
431 ; CHECK-LABEL: _Z13testUiToFpExtILj3EEfDv4_j
432 ; CHECK: xxextractuw 0, 34, 0
433 ; CHECK: xscvuxdsp 1, 0
434 ; CHECK-BE-LABEL: _Z13testUiToFpExtILj3EEfDv4_j
435 ; CHECK-BE: xxextractuw 0, 34, 12
436 ; CHECK-BE: xscvuxdsp 1, 0
437 %vecext = extractelement <4 x i32> %a, i32 3
438 %conv = uitofp i32 %vecext to float
442 ; Verify we generate optimal code for unsigned vector int elem extract followed
443 ; by conversion to double
445 define double @conv2dlbTestui0(<4 x i32> %a) {
447 ; CHECK-LABEL: conv2dlbTestui0
448 ; CHECK: xxextractuw [[SW:[0-9]+]], 34, 12
449 ; CHECK: xscvuxddp 1, [[SW]]
450 ; CHECK-BE-LABEL: conv2dlbTestui0
451 ; CHECK-BE: xxextractuw [[CP:[0-9]+]], 34, 0
452 ; CHECK-BE: xscvuxddp 1, [[CP]]
453 %0 = extractelement <4 x i32> %a, i32 0
454 %1 = uitofp i32 %0 to double
458 define double @conv2dlbTestui1(<4 x i32> %a) {
460 ; CHECK-LABEL: conv2dlbTestui1
461 ; CHECK: xxextractuw [[SW:[0-9]+]], 34, 8
462 ; CHECK: xscvuxddp 1, [[SW]]
463 ; CHECK-BE-LABEL: conv2dlbTestui1
464 ; CHECK-BE: xxextractuw [[CP:[0-9]+]], 34, 4
465 ; CHECK-BE: xscvuxddp 1, [[CP]]
466 %0 = extractelement <4 x i32> %a, i32 1
467 %1 = uitofp i32 %0 to double
471 define double @conv2dlbTestui2(<4 x i32> %a) {
473 ; CHECK-LABEL: conv2dlbTestui2
474 ; CHECK: xxextractuw [[SW:[0-9]+]], 34, 4
475 ; CHECK: xscvuxddp 1, [[SW]]
476 ; CHECK-BE-LABEL: conv2dlbTestui2
477 ; CHECK-BE: xxextractuw [[CP:[0-9]+]], 34, 8
478 ; CHECK-BE: xscvuxddp 1, [[CP]]
479 %0 = extractelement <4 x i32> %a, i32 2
480 %1 = uitofp i32 %0 to double
484 define double @conv2dlbTestui3(<4 x i32> %a) {
486 ; CHECK-LABEL: conv2dlbTestui3
487 ; CHECK: xxextractuw [[SW:[0-9]+]], 34, 0
488 ; CHECK: xscvuxddp 1, [[SW]]
489 ; CHECK-BE-LABEL: conv2dlbTestui3
490 ; CHECK-BE: xxextractuw [[CP:[0-9]+]], 34, 12
491 ; CHECK-BE: xscvuxddp 1, [[CP]]
492 %0 = extractelement <4 x i32> %a, i32 3
493 %1 = uitofp i32 %0 to double
497 ; verify we don't crash for variable elem extract
498 define double @conv2dlbTestuiVar(<4 x i32> %a, i32 zeroext %elem) {
500 %vecext = extractelement <4 x i32> %a, i32 %elem
501 %conv = uitofp i32 %vecext to double
505 define <4 x float> @_Z10testInsEltILj0EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {
507 ; CHECK-LABEL: _Z10testInsEltILj0EDv4_ffET0_S1_T1_
508 ; CHECK: xscvdpspn 0, 1
509 ; CHECK: xxsldwi 0, 0, 0, 3
510 ; CHECK: xxinsertw 34, 0, 12
511 ; CHECK-BE-LABEL: _Z10testInsEltILj0EDv4_ffET0_S1_T1_
512 ; CHECK-BE: xscvdpspn 0, 1
513 ; CHECK-BE: xxsldwi 0, 0, 0, 3
514 ; CHECK-BE: xxinsertw 34, 0, 0
515 %vecins = insertelement <4 x float> %a, float %b, i32 0
516 ret <4 x float> %vecins
519 define <4 x float> @_Z10testInsEltILj1EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {
521 ; CHECK-LABEL: _Z10testInsEltILj1EDv4_ffET0_S1_T1_
522 ; CHECK: xscvdpspn 0, 1
523 ; CHECK: xxsldwi 0, 0, 0, 3
524 ; CHECK: xxinsertw 34, 0, 8
525 ; CHECK-BE-LABEL: _Z10testInsEltILj1EDv4_ffET0_S1_T1_
526 ; CHECK-BE: xscvdpspn 0, 1
527 ; CHECK-BE: xxsldwi 0, 0, 0, 3
528 ; CHECK-BE: xxinsertw 34, 0, 4
529 %vecins = insertelement <4 x float> %a, float %b, i32 1
530 ret <4 x float> %vecins
533 define <4 x float> @_Z10testInsEltILj2EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {
535 ; CHECK-LABEL: _Z10testInsEltILj2EDv4_ffET0_S1_T1_
536 ; CHECK: xscvdpspn 0, 1
537 ; CHECK: xxsldwi 0, 0, 0, 3
538 ; CHECK: xxinsertw 34, 0, 4
539 ; CHECK-BE-LABEL: _Z10testInsEltILj2EDv4_ffET0_S1_T1_
540 ; CHECK-BE: xscvdpspn 0, 1
541 ; CHECK-BE: xxsldwi 0, 0, 0, 3
542 ; CHECK-BE: xxinsertw 34, 0, 8
543 %vecins = insertelement <4 x float> %a, float %b, i32 2
544 ret <4 x float> %vecins
547 define <4 x float> @_Z10testInsEltILj3EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {
549 ; CHECK-LABEL: _Z10testInsEltILj3EDv4_ffET0_S1_T1_
550 ; CHECK: xscvdpspn 0, 1
551 ; CHECK: xxsldwi 0, 0, 0, 3
552 ; CHECK: xxinsertw 34, 0, 0
553 ; CHECK-BE-LABEL: _Z10testInsEltILj3EDv4_ffET0_S1_T1_
554 ; CHECK-BE: xscvdpspn 0, 1
555 ; CHECK-BE: xxsldwi 0, 0, 0, 3
556 ; CHECK-BE: xxinsertw 34, 0, 12
557 %vecins = insertelement <4 x float> %a, float %b, i32 3
558 ret <4 x float> %vecins
561 define <4 x i32> @_Z10testInsEltILj0EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
563 ; CHECK-LABEL: _Z10testInsEltILj0EDv4_jjET0_S1_T1_
564 ; CHECK: mtvsrwz 0, 5
565 ; CHECK: xxinsertw 34, 0, 12
566 ; CHECK-BE-LABEL: _Z10testInsEltILj0EDv4_jjET0_S1_T1_
567 ; CHECK-BE: mtvsrwz 0, 5
568 ; CHECK-BE: xxinsertw 34, 0, 0
569 %vecins = insertelement <4 x i32> %a, i32 %b, i32 0
570 ret <4 x i32> %vecins
573 define <4 x i32> @_Z10testInsEltILj1EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
575 ; CHECK-LABEL: _Z10testInsEltILj1EDv4_jjET0_S1_T1_
576 ; CHECK: mtvsrwz 0, 5
577 ; CHECK: xxinsertw 34, 0, 8
578 ; CHECK-BE-LABEL: _Z10testInsEltILj1EDv4_jjET0_S1_T1_
579 ; CHECK-BE: mtvsrwz 0, 5
580 ; CHECK-BE: xxinsertw 34, 0, 4
581 %vecins = insertelement <4 x i32> %a, i32 %b, i32 1
582 ret <4 x i32> %vecins
585 define <4 x i32> @_Z10testInsEltILj2EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
587 ; CHECK-LABEL: _Z10testInsEltILj2EDv4_jjET0_S1_T1_
588 ; CHECK: mtvsrwz 0, 5
589 ; CHECK: xxinsertw 34, 0, 4
590 ; CHECK-BE-LABEL: _Z10testInsEltILj2EDv4_jjET0_S1_T1_
591 ; CHECK-BE: mtvsrwz 0, 5
592 ; CHECK-BE: xxinsertw 34, 0, 8
593 %vecins = insertelement <4 x i32> %a, i32 %b, i32 2
594 ret <4 x i32> %vecins
597 define <4 x i32> @_Z10testInsEltILj3EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
599 ; CHECK-LABEL: _Z10testInsEltILj3EDv4_jjET0_S1_T1_
600 ; CHECK: mtvsrwz 0, 5
601 ; CHECK: xxinsertw 34, 0, 0
602 ; CHECK-BE-LABEL: _Z10testInsEltILj3EDv4_jjET0_S1_T1_
603 ; CHECK-BE: mtvsrwz 0, 5
604 ; CHECK-BE: xxinsertw 34, 0, 12
605 %vecins = insertelement <4 x i32> %a, i32 %b, i32 3
606 ret <4 x i32> %vecins
609 define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
611 ; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_
612 ; CHECK: xxswapd 0, 35
613 ; CHECK: xxinsertw 34, 0, 12
614 ; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_
615 ; CHECK-BE: xxsldwi 0, 35, 35, 3
616 ; CHECK-BE: xxinsertw 34, 0, 0
617 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
618 ret <4 x float> %vecins
621 define <4 x float> @_Z7testInsILj0ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
623 ; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_
624 ; CHECK: xxsldwi 0, 35, 35, 1
625 ; CHECK: xxinsertw 34, 0, 12
626 ; CHECK-BE-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_
627 ; CHECK-BE-NOT: xxsldwi
628 ; CHECK-BE: xxinsertw 34, 35, 0
629 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 1, i32 5, i32 6, i32 7>
630 ret <4 x float> %vecins
633 define <4 x float> @_Z7testInsILj0ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
635 ; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_
637 ; CHECK: xxinsertw 34, 35, 12
638 ; CHECK-BE-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_
639 ; CHECK-BE: xxsldwi 0, 35, 35, 1
640 ; CHECK-BE: xxinsertw 34, 0, 0
641 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 2, i32 5, i32 6, i32 7>
642 ret <4 x float> %vecins
645 define <4 x float> @_Z7testInsILj0ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
647 ; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_
648 ; CHECK: xxsldwi 0, 35, 35, 3
649 ; CHECK: xxinsertw 34, 0, 12
650 ; CHECK-BE-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_
651 ; CHECK-BE: xxswapd 0, 35
652 ; CHECK-BE: xxinsertw 34, 0, 0
653 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 3, i32 5, i32 6, i32 7>
654 ret <4 x float> %vecins
657 define <4 x float> @_Z7testInsILj1ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
659 ; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_
660 ; CHECK: xxswapd 0, 35
661 ; CHECK: xxinsertw 34, 0, 8
662 ; CHECK-BE-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_
663 ; CHECK-BE: xxsldwi 0, 35, 35, 3
664 ; CHECK-BE: xxinsertw 34, 0, 4
665 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 0, i32 6, i32 7>
666 ret <4 x float> %vecins
669 define <4 x float> @_Z7testInsILj1ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
671 ; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_
672 ; CHECK: xxsldwi 0, 35, 35, 1
673 ; CHECK: xxinsertw 34, 0, 8
674 ; CHECK-BE-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_
675 ; CHECK-BE-NOT: xxsldwi
676 ; CHECK-BE: xxinsertw 34, 35, 4
677 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
678 ret <4 x float> %vecins
681 define <4 x float> @_Z7testInsILj1ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
683 ; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_
685 ; CHECK: xxinsertw 34, 35, 8
686 ; CHECK-BE-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_
687 ; CHECK-BE: xxsldwi 0, 35, 35, 1
688 ; CHECK-BE: xxinsertw 34, 0, 4
689 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 2, i32 6, i32 7>
690 ret <4 x float> %vecins
693 define <4 x float> @_Z7testInsILj1ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
695 ; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_
696 ; CHECK: xxsldwi 0, 35, 35, 3
697 ; CHECK: xxinsertw 34, 0, 8
698 ; CHECK-BE-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_
699 ; CHECK-BE: xxswapd 0, 35
700 ; CHECK-BE: xxinsertw 34, 0, 4
701 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 3, i32 6, i32 7>
702 ret <4 x float> %vecins
705 define <4 x float> @_Z7testInsILj2ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
707 ; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_
708 ; CHECK: xxswapd 0, 35
709 ; CHECK: xxinsertw 34, 0, 4
710 ; CHECK-BE-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_
711 ; CHECK-BE: xxsldwi 0, 35, 35, 3
712 ; CHECK-BE: xxinsertw 34, 0, 8
713 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 0, i32 7>
714 ret <4 x float> %vecins
717 define <4 x float> @_Z7testInsILj2ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
719 ; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_
720 ; CHECK: xxsldwi 0, 35, 35, 1
721 ; CHECK: xxinsertw 34, 0, 4
722 ; CHECK-BE-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_
723 ; CHECK-BE-NOT: xxsldwi
724 ; CHECK-BE: xxinsertw 34, 35, 8
725 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 7>
726 ret <4 x float> %vecins
729 define <4 x float> @_Z7testInsILj2ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
731 ; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_
733 ; CHECK: xxinsertw 34, 35, 4
734 ; CHECK-BE-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_
735 ; CHECK-BE: xxsldwi 0, 35, 35, 1
736 ; CHECK-BE: xxinsertw 34, 0, 8
737 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
738 ret <4 x float> %vecins
741 define <4 x float> @_Z7testInsILj2ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
743 ; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_
744 ; CHECK: xxsldwi 0, 35, 35, 3
745 ; CHECK: xxinsertw 34, 0, 4
746 ; CHECK-BE-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_
747 ; CHECK-BE: xxswapd 0, 35
748 ; CHECK-BE: xxinsertw 34, 0, 8
749 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 3, i32 7>
750 ret <4 x float> %vecins
753 define <4 x float> @_Z7testInsILj3ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
755 ; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_
756 ; CHECK: xxswapd 0, 35
757 ; CHECK: xxinsertw 34, 0, 0
758 ; CHECK-BE-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_
759 ; CHECK-BE: xxsldwi 0, 35, 35, 3
760 ; CHECK-BE: xxinsertw 34, 0, 12
761 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 0>
762 ret <4 x float> %vecins
765 define <4 x float> @_Z7testInsILj3ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
767 ; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_
768 ; CHECK: xxsldwi 0, 35, 35, 1
769 ; CHECK: xxinsertw 34, 0, 0
770 ; CHECK-BE-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_
771 ; CHECK-BE-NOT: xxsldwi
772 ; CHECK-BE: xxinsertw 34, 35, 12
773 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 1>
774 ret <4 x float> %vecins
777 define <4 x float> @_Z7testInsILj3ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
779 ; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_
781 ; CHECK: xxinsertw 34, 35, 0
782 ; CHECK-BE-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_
783 ; CHECK-BE: xxsldwi 0, 35, 35, 1
784 ; CHECK-BE: xxinsertw 34, 0, 12
785 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 2>
786 ret <4 x float> %vecins
789 define <4 x float> @_Z7testInsILj3ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
791 ; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_
792 ; CHECK: xxsldwi 0, 35, 35, 3
793 ; CHECK: xxinsertw 34, 0, 0
794 ; CHECK-BE-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_
795 ; CHECK-BE: xxswapd 0, 35
796 ; CHECK-BE: xxinsertw 34, 0, 12
797 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 3>
798 ret <4 x float> %vecins
801 define <4 x i32> @_Z7testInsILj0ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
803 ; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_
804 ; CHECK: xxswapd 0, 35
805 ; CHECK: xxinsertw 34, 0, 12
806 ; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_
807 ; CHECK-BE: xxsldwi 0, 35, 35, 3
808 ; CHECK-BE: xxinsertw 34, 0, 0
809 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
810 ret <4 x i32> %vecins
813 define <4 x i32> @_Z7testInsILj0ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
815 ; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_
816 ; CHECK: xxsldwi 0, 35, 35, 1
817 ; CHECK: xxinsertw 34, 0, 12
818 ; CHECK-BE-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_
819 ; CHECK-BE-NOT: xxsldwi
820 ; CHECK-BE: xxinsertw 34, 35, 0
821 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 1, i32 5, i32 6, i32 7>
822 ret <4 x i32> %vecins
825 define <4 x i32> @_Z7testInsILj0ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
827 ; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_
829 ; CHECK: xxinsertw 34, 35, 12
830 ; CHECK-BE-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_
831 ; CHECK-BE: xxsldwi 0, 35, 35, 1
832 ; CHECK-BE: xxinsertw 34, 0, 0
833 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 2, i32 5, i32 6, i32 7>
834 ret <4 x i32> %vecins
837 define <4 x i32> @_Z7testInsILj0ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
839 ; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_
840 ; CHECK: xxsldwi 0, 35, 35, 3
841 ; CHECK: xxinsertw 34, 0, 12
842 ; CHECK-BE-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_
843 ; CHECK-BE: xxswapd 0, 35
844 ; CHECK-BE: xxinsertw 34, 0, 0
845 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 3, i32 5, i32 6, i32 7>
846 ret <4 x i32> %vecins
849 define <4 x i32> @_Z7testInsILj1ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
851 ; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_
852 ; CHECK: xxswapd 0, 35
853 ; CHECK: xxinsertw 34, 0, 8
854 ; CHECK-BE-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_
855 ; CHECK-BE: xxsldwi 0, 35, 35, 3
856 ; CHECK-BE: xxinsertw 34, 0, 4
857 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 0, i32 6, i32 7>
858 ret <4 x i32> %vecins
861 define <4 x i32> @_Z7testInsILj1ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
863 ; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_
864 ; CHECK: xxsldwi 0, 35, 35, 1
865 ; CHECK: xxinsertw 34, 0, 8
866 ; CHECK-BE-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_
867 ; CHECK-BE-NOT: xxsldwi
868 ; CHECK-BE: xxinsertw 34, 35, 4
869 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
870 ret <4 x i32> %vecins
873 define <4 x i32> @_Z7testInsILj1ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
875 ; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_
877 ; CHECK: xxinsertw 34, 35, 8
878 ; CHECK-BE-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_
879 ; CHECK-BE: xxsldwi 0, 35, 35, 1
880 ; CHECK-BE: xxinsertw 34, 0, 4
881 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 2, i32 6, i32 7>
882 ret <4 x i32> %vecins
885 define <4 x i32> @_Z7testInsILj1ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
887 ; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_
888 ; CHECK: xxsldwi 0, 35, 35, 3
889 ; CHECK: xxinsertw 34, 0, 8
890 ; CHECK-BE-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_
891 ; CHECK-BE: xxswapd 0, 35
892 ; CHECK-BE: xxinsertw 34, 0, 4
893 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 3, i32 6, i32 7>
894 ret <4 x i32> %vecins
897 define <4 x i32> @_Z7testInsILj2ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
899 ; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_
900 ; CHECK: xxswapd 0, 35
901 ; CHECK: xxinsertw 34, 0, 4
902 ; CHECK-BE-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_
903 ; CHECK-BE: xxsldwi 0, 35, 35, 3
904 ; CHECK-BE: xxinsertw 34, 0, 8
905 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 0, i32 7>
906 ret <4 x i32> %vecins
909 define <4 x i32> @_Z7testInsILj2ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
911 ; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_
912 ; CHECK: xxsldwi 0, 35, 35, 1
913 ; CHECK: xxinsertw 34, 0, 4
914 ; CHECK-BE-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_
915 ; CHECK-BE-NOT: xxsldwi
916 ; CHECK-BE: xxinsertw 34, 35, 8
917 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 7>
918 ret <4 x i32> %vecins
921 define <4 x i32> @_Z7testInsILj2ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
923 ; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_
925 ; CHECK: xxinsertw 34, 35, 4
926 ; CHECK-BE-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_
927 ; CHECK-BE: xxsldwi 0, 35, 35, 1
928 ; CHECK-BE: xxinsertw 34, 0, 8
929 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
930 ret <4 x i32> %vecins
933 define <4 x i32> @_Z7testInsILj2ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
935 ; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_
936 ; CHECK: xxsldwi 0, 35, 35, 3
937 ; CHECK: xxinsertw 34, 0, 4
938 ; CHECK-BE-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_
939 ; CHECK-BE: xxswapd 0, 35
940 ; CHECK-BE: xxinsertw 34, 0, 8
941 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 3, i32 7>
942 ret <4 x i32> %vecins
945 define <4 x i32> @_Z7testInsILj3ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
947 ; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_
948 ; CHECK: xxswapd 0, 35
949 ; CHECK: xxinsertw 34, 0, 0
950 ; CHECK-BE-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_
951 ; CHECK-BE: xxsldwi 0, 35, 35, 3
952 ; CHECK-BE: xxinsertw 34, 0, 12
953 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 0>
954 ret <4 x i32> %vecins
957 define <4 x i32> @_Z7testInsILj3ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
959 ; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_
960 ; CHECK: xxsldwi 0, 35, 35, 1
961 ; CHECK: xxinsertw 34, 0, 0
962 ; CHECK-BE-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_
963 ; CHECK-BE-NOT: xxsldwi
964 ; CHECK-BE: xxinsertw 34, 35, 12
965 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 1>
966 ret <4 x i32> %vecins
969 define <4 x i32> @_Z7testInsILj3ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
971 ; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_
973 ; CHECK: xxinsertw 34, 35, 0
974 ; CHECK-BE-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_
975 ; CHECK-BE: xxsldwi 0, 35, 35, 1
976 ; CHECK-BE: xxinsertw 34, 0, 12
977 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 2>
978 ret <4 x i32> %vecins
981 define <4 x i32> @_Z7testInsILj3ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
983 ; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_
984 ; CHECK: xxsldwi 0, 35, 35, 3
985 ; CHECK: xxinsertw 34, 0, 0
986 ; CHECK-BE-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_
987 ; CHECK-BE: xxswapd 0, 35
988 ; CHECK-BE: xxinsertw 34, 0, 12
989 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 3>
990 ret <4 x i32> %vecins
992 define <4 x float> @testSameVecEl0BE(<4 x float> %a) {
994 ; CHECK-BE-LABEL: testSameVecEl0BE
995 ; CHECK-BE: xxinsertw 34, 34, 0
996 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 5, i32 1, i32 2, i32 3>
997 ret <4 x float> %vecins
999 define <4 x float> @testSameVecEl2BE(<4 x float> %a) {
1001 ; CHECK-BE-LABEL: testSameVecEl2BE
1002 ; CHECK-BE: xxinsertw 34, 34, 8
1003 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 5, i32 3>
1004 ret <4 x float> %vecins
1006 define <4 x float> @testSameVecEl3BE(<4 x float> %a) {
1008 ; CHECK-BE-LABEL: testSameVecEl3BE
1009 ; CHECK-BE: xxinsertw 34, 34, 12
1010 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
1011 ret <4 x float> %vecins
1013 define <4 x float> @testSameVecEl0LE(<4 x float> %a) {
1015 ; CHECK-LABEL: testSameVecEl0LE
1016 ; CHECK: xxinsertw 34, 34, 12
1017 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 6, i32 1, i32 2, i32 3>
1018 ret <4 x float> %vecins
1020 define <4 x float> @testSameVecEl1LE(<4 x float> %a) {
1022 ; CHECK-LABEL: testSameVecEl1LE
1023 ; CHECK: xxinsertw 34, 34, 8
1024 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
1025 ret <4 x float> %vecins
1027 define <4 x float> @testSameVecEl3LE(<4 x float> %a) {
1029 ; CHECK-LABEL: testSameVecEl3LE
1030 ; CHECK: xxinsertw 34, 34, 0
1031 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
1032 ret <4 x float> %vecins
1034 define <4 x float> @insertVarF(<4 x float> %a, float %f, i32 %el) {
1036 ; CHECK-LABEL: insertVarF
1039 ; CHECK-BE-LABEL: insertVarF
1040 ; CHECK-BE: stfsx 1,
1042 %vecins = insertelement <4 x float> %a, float %f, i32 %el
1043 ret <4 x float> %vecins
1045 define <4 x i32> @insertVarI(<4 x i32> %a, i32 %i, i32 %el) {
1047 ; CHECK-LABEL: insertVarI
1050 ; CHECK-BE-LABEL: insertVarI
1053 %vecins = insertelement <4 x i32> %a, i32 %i, i32 %el
1054 ret <4 x i32> %vecins
1056 define <4 x i32> @intrinsicInsertTest(<4 x i32> %a, <2 x i64> %b) {
1058 ; CHECK-LABEL:intrinsicInsertTest
1059 ; CHECK: xxinsertw 34, 35, 3
1061 %ans = tail call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32> %a, <2 x i64> %b, i32 3)
1064 declare <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32>, <2 x i64>, i32)
1065 define <2 x i64> @intrinsicExtractTest(<2 x i64> %a) {
1067 ; CHECK-LABEL: intrinsicExtractTest
1068 ; CHECK: xxextractuw 0, 34, 5
1070 %ans = tail call <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64> %a, i32 5)
1073 declare <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64>, i32)