| blob | 6b945d4688062d5a49be9fe98561e92b37b3d14c |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3 ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
4 ; RUN: FileCheck %s --check-prefix=CHECK-P8
5 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
6 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
7 ; RUN: FileCheck %s --check-prefix=CHECK-P9
8 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
9 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
10 ; RUN: FileCheck %s --check-prefix=CHECK-BE
12 define <2 x i64> @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
13 ; CHECK-P8-LABEL: test2elt:
14 ; CHECK-P8: # %bb.0: # %entry
15 ; CHECK-P8-NEXT: mtvsrd f0, r3
16 ; CHECK-P8-NEXT: xxswapd v2, vs0
17 ; CHECK-P8-NEXT: xscvspdpn f0, vs0
18 ; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 3
19 ; CHECK-P8-NEXT: xscvspdpn f1, vs1
20 ; CHECK-P8-NEXT: xxmrghd vs0, vs0, vs1
21 ; CHECK-P8-NEXT: xvcvdpuxds v2, vs0
22 ; CHECK-P8-NEXT: blr
23 ;
24 ; CHECK-P9-LABEL: test2elt:
25 ; CHECK-P9: # %bb.0: # %entry
26 ; CHECK-P9-NEXT: mtvsrd f0, r3
27 ; CHECK-P9-NEXT: xxswapd v2, vs0
28 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
29 ; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3
30 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
31 ; CHECK-P9-NEXT: xxmrghd vs0, vs0, vs1
32 ; CHECK-P9-NEXT: xvcvdpuxds v2, vs0
33 ; CHECK-P9-NEXT: blr
34 ;
35 ; CHECK-BE-LABEL: test2elt:
36 ; CHECK-BE: # %bb.0: # %entry
37 ; CHECK-BE-NEXT: mtvsrd f0, r3
38 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
39 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
40 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
41 ; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0
42 ; CHECK-BE-NEXT: xvcvdpuxds v2, vs0
43 ; CHECK-BE-NEXT: blr
44 entry:
45 %0 = bitcast i64 %a.coerce to <2 x float>
46 %1 = fptoui <2 x float> %0 to <2 x i64>
47 ret <2 x i64> %1
48 }
50 define void @test4elt(<4 x i64>* noalias nocapture sret %agg.result, <4 x float> %a) local_unnamed_addr #1 {
51 ; CHECK-P8-LABEL: test4elt:
52 ; CHECK-P8: # %bb.0: # %entry
53 ; CHECK-P8-NEXT: xxsldwi vs0, v2, v2, 3
54 ; CHECK-P8-NEXT: xxswapd vs1, v2
55 ; CHECK-P8-NEXT: li r4, 16
56 ; CHECK-P8-NEXT: xxsldwi vs3, v2, v2, 1
57 ; CHECK-P8-NEXT: xscvspdpn f2, v2
58 ; CHECK-P8-NEXT: xscvspdpn f0, vs0
59 ; CHECK-P8-NEXT: xscvspdpn f1, vs1
60 ; CHECK-P8-NEXT: xscvspdpn f3, vs3
61 ; CHECK-P8-NEXT: xxmrghd vs0, vs1, vs0
62 ; CHECK-P8-NEXT: xxmrghd vs1, vs2, vs3
63 ; CHECK-P8-NEXT: xvcvdpuxds v2, vs0
64 ; CHECK-P8-NEXT: xvcvdpuxds v3, vs1
65 ; CHECK-P8-NEXT: xxswapd vs1, v2
66 ; CHECK-P8-NEXT: xxswapd vs0, v3
67 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r4
68 ; CHECK-P8-NEXT: stxvd2x vs1, 0, r3
69 ; CHECK-P8-NEXT: blr
70 ;
71 ; CHECK-P9-LABEL: test4elt:
72 ; CHECK-P9: # %bb.0: # %entry
73 ; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 3
74 ; CHECK-P9-NEXT: xxswapd vs1, v2
75 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
76 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
77 ; CHECK-P9-NEXT: xxsldwi vs2, v2, v2, 1
78 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
79 ; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0
80 ; CHECK-P9-NEXT: xscvspdpn f1, v2
81 ; CHECK-P9-NEXT: xxmrghd vs1, vs1, vs2
82 ; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0
83 ; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1
84 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
85 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
86 ; CHECK-P9-NEXT: blr
87 ;
88 ; CHECK-BE-LABEL: test4elt:
89 ; CHECK-BE: # %bb.0: # %entry
90 ; CHECK-BE-NEXT: xxsldwi vs1, v2, v2, 1
91 ; CHECK-BE-NEXT: xscvspdpn f0, v2
92 ; CHECK-BE-NEXT: xxswapd vs2, v2
93 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
94 ; CHECK-BE-NEXT: xxmrghd vs0, vs0, vs1
95 ; CHECK-BE-NEXT: xxsldwi vs1, v2, v2, 3
96 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
97 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
98 ; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0
99 ; CHECK-BE-NEXT: xxmrghd vs1, vs2, vs1
100 ; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1
101 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
102 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
103 ; CHECK-BE-NEXT: blr
104 entry:
105 %0 = fptoui <4 x float> %a to <4 x i64>
106 store <4 x i64> %0, <4 x i64>* %agg.result, align 32
107 ret void
108 }
110 define void @test8elt(<8 x i64>* noalias nocapture sret %agg.result, <8 x float>* nocapture readonly) local_unnamed_addr #2 {
111 ; CHECK-P8-LABEL: test8elt:
112 ; CHECK-P8: # %bb.0: # %entry
113 ; CHECK-P8-NEXT: li r5, 16
114 ; CHECK-P8-NEXT: lvx v3, 0, r4
115 ; CHECK-P8-NEXT: li r6, 32
116 ; CHECK-P8-NEXT: lvx v2, r4, r5
117 ; CHECK-P8-NEXT: li r4, 48
118 ; CHECK-P8-NEXT: xxsldwi vs5, v3, v3, 3
119 ; CHECK-P8-NEXT: xxswapd vs6, v3
120 ; CHECK-P8-NEXT: xxsldwi vs0, v2, v2, 3
121 ; CHECK-P8-NEXT: xxswapd vs1, v2
122 ; CHECK-P8-NEXT: xxsldwi vs3, v2, v2, 1
123 ; CHECK-P8-NEXT: xxsldwi vs7, v3, v3, 1
124 ; CHECK-P8-NEXT: xscvspdpn f2, v2
125 ; CHECK-P8-NEXT: xscvspdpn f4, v3
126 ; CHECK-P8-NEXT: xscvspdpn f0, vs0
127 ; CHECK-P8-NEXT: xscvspdpn f1, vs1
128 ; CHECK-P8-NEXT: xscvspdpn f3, vs3
129 ; CHECK-P8-NEXT: xscvspdpn f5, vs5
130 ; CHECK-P8-NEXT: xscvspdpn f6, vs6
131 ; CHECK-P8-NEXT: xscvspdpn f7, vs7
132 ; CHECK-P8-NEXT: xxmrghd vs0, vs1, vs0
133 ; CHECK-P8-NEXT: xxmrghd vs1, vs2, vs3
134 ; CHECK-P8-NEXT: xxmrghd vs2, vs6, vs5
135 ; CHECK-P8-NEXT: xvcvdpuxds v2, vs0
136 ; CHECK-P8-NEXT: xxmrghd vs3, vs4, vs7
137 ; CHECK-P8-NEXT: xvcvdpuxds v3, vs1
138 ; CHECK-P8-NEXT: xvcvdpuxds v4, vs2
139 ; CHECK-P8-NEXT: xvcvdpuxds v5, vs3
140 ; CHECK-P8-NEXT: xxswapd vs1, v2
141 ; CHECK-P8-NEXT: xxswapd vs0, v3
142 ; CHECK-P8-NEXT: xxswapd vs3, v4
143 ; CHECK-P8-NEXT: xxswapd vs2, v5
144 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r4
145 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r6
146 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r5
147 ; CHECK-P8-NEXT: stxvd2x vs3, 0, r3
148 ; CHECK-P8-NEXT: blr
149 ;
150 ; CHECK-P9-LABEL: test8elt:
151 ; CHECK-P9: # %bb.0: # %entry
152 ; CHECK-P9-NEXT: lxv vs0, 0(r4)
153 ; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3
154 ; CHECK-P9-NEXT: xxswapd vs2, vs0
155 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
156 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
157 ; CHECK-P9-NEXT: xscvspdpn f3, vs0
158 ; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
159 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
160 ; CHECK-P9-NEXT: xxmrghd vs1, vs2, vs1
161 ; CHECK-P9-NEXT: lxv vs2, 16(r4)
162 ; CHECK-P9-NEXT: xxmrghd vs0, vs3, vs0
163 ; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1
164 ; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0
165 ; CHECK-P9-NEXT: xxsldwi vs3, vs2, vs2, 3
166 ; CHECK-P9-NEXT: xxswapd vs4, vs2
167 ; CHECK-P9-NEXT: xscvspdpn f3, vs3
168 ; CHECK-P9-NEXT: xscvspdpn f4, vs4
169 ; CHECK-P9-NEXT: stxv vs0, 16(r3)
170 ; CHECK-P9-NEXT: xxmrghd vs3, vs4, vs3
171 ; CHECK-P9-NEXT: xscvspdpn f4, vs2
172 ; CHECK-P9-NEXT: xxsldwi vs2, vs2, vs2, 1
173 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
174 ; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3
175 ; CHECK-P9-NEXT: xxmrghd vs2, vs4, vs2
176 ; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2
177 ; CHECK-P9-NEXT: stxv vs3, 32(r3)
178 ; CHECK-P9-NEXT: stxv vs2, 48(r3)
179 ; CHECK-P9-NEXT: stxv vs1, 0(r3)
180 ; CHECK-P9-NEXT: blr
181 ;
182 ; CHECK-BE-LABEL: test8elt:
183 ; CHECK-BE: # %bb.0: # %entry
184 ; CHECK-BE-NEXT: lxv vs1, 0(r4)
185 ; CHECK-BE-NEXT: xxsldwi vs3, vs1, vs1, 1
186 ; CHECK-BE-NEXT: xscvspdpn f2, vs1
187 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
188 ; CHECK-BE-NEXT: lxv vs0, 16(r4)
189 ; CHECK-BE-NEXT: xxsldwi vs4, vs0, vs0, 1
190 ; CHECK-BE-NEXT: xscvspdpn f4, vs4
191 ; CHECK-BE-NEXT: xxmrghd vs2, vs2, vs3
192 ; CHECK-BE-NEXT: xxsldwi vs3, vs1, vs1, 3
193 ; CHECK-BE-NEXT: xxswapd vs1, vs1
194 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
195 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
196 ; CHECK-BE-NEXT: xxmrghd vs1, vs1, vs3
197 ; CHECK-BE-NEXT: xscvspdpn f3, vs0
198 ; CHECK-BE-NEXT: xxmrghd vs3, vs3, vs4
199 ; CHECK-BE-NEXT: xxsldwi vs4, vs0, vs0, 3
200 ; CHECK-BE-NEXT: xxswapd vs0, vs0
201 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
202 ; CHECK-BE-NEXT: xscvspdpn f4, vs4
203 ; CHECK-BE-NEXT: xxmrghd vs0, vs0, vs4
204 ; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2
205 ; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1
206 ; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3
207 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
208 ; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0
209 ; CHECK-BE-NEXT: stxv vs3, 32(r3)
210 ; CHECK-BE-NEXT: stxv vs0, 48(r3)
211 ; CHECK-BE-NEXT: stxv vs2, 0(r3)
212 ; CHECK-BE-NEXT: blr
213 entry:
214 %a = load <8 x float>, <8 x float>* %0, align 32
215 %1 = fptoui <8 x float> %a to <8 x i64>
216 store <8 x i64> %1, <8 x i64>* %agg.result, align 64
217 ret void
218 }
220 define void @test16elt(<16 x i64>* noalias nocapture sret %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #2 {
221 ; CHECK-P8-LABEL: test16elt:
222 ; CHECK-P8: # %bb.0: # %entry
223 ; CHECK-P8-NEXT: li r5, 16
224 ; CHECK-P8-NEXT: li r7, 48
225 ; CHECK-P8-NEXT: li r6, 32
226 ; CHECK-P8-NEXT: lvx v4, 0, r4
227 ; CHECK-P8-NEXT: li r8, 64
228 ; CHECK-P8-NEXT: lvx v5, r4, r5
229 ; CHECK-P8-NEXT: lvx v3, r4, r7
230 ; CHECK-P8-NEXT: lvx v2, r4, r6
231 ; CHECK-P8-NEXT: li r4, 112
232 ; CHECK-P8-NEXT: xxsldwi vs13, v4, v4, 3
233 ; CHECK-P8-NEXT: xscvspdpn f6, v4
234 ; CHECK-P8-NEXT: xxsldwi vs1, v5, v5, 3
235 ; CHECK-P8-NEXT: xxswapd vs3, v5
236 ; CHECK-P8-NEXT: xxsldwi vs9, v3, v3, 1
237 ; CHECK-P8-NEXT: xscvspdpn f4, v3
238 ; CHECK-P8-NEXT: xxsldwi vs5, v5, v5, 1
239 ; CHECK-P8-NEXT: xxsldwi vs10, v3, v3, 3
240 ; CHECK-P8-NEXT: xscvspdpn f1, vs1
241 ; CHECK-P8-NEXT: xxswapd vs11, v3
242 ; CHECK-P8-NEXT: xscvspdpn f3, vs3
243 ; CHECK-P8-NEXT: xxsldwi vs7, v2, v2, 3
244 ; CHECK-P8-NEXT: xscvspdpn f9, vs9
245 ; CHECK-P8-NEXT: xxswapd vs8, v2
246 ; CHECK-P8-NEXT: xscvspdpn f0, v5
247 ; CHECK-P8-NEXT: xxsldwi vs12, v2, v2, 1
248 ; CHECK-P8-NEXT: xscvspdpn f2, v2
249 ; CHECK-P8-NEXT: xxswapd v2, v4
250 ; CHECK-P8-NEXT: xscvspdpn f5, vs5
251 ; CHECK-P8-NEXT: xxsldwi v3, v4, v4, 1
252 ; CHECK-P8-NEXT: xscvspdpn f10, vs10
253 ; CHECK-P8-NEXT: xscvspdpn f11, vs11
254 ; CHECK-P8-NEXT: xxmrghd vs1, vs3, vs1
255 ; CHECK-P8-NEXT: xscvspdpn f7, vs7
256 ; CHECK-P8-NEXT: xxmrghd vs4, vs4, vs9
257 ; CHECK-P8-NEXT: xscvspdpn f8, vs8
258 ; CHECK-P8-NEXT: xscvspdpn f12, vs12
259 ; CHECK-P8-NEXT: xscvspdpn f13, vs13
260 ; CHECK-P8-NEXT: xxmrghd vs0, vs0, vs5
261 ; CHECK-P8-NEXT: xscvspdpn f3, v2
262 ; CHECK-P8-NEXT: xscvspdpn f9, v3
263 ; CHECK-P8-NEXT: xxmrghd vs5, vs11, vs10
264 ; CHECK-P8-NEXT: xvcvdpuxds v3, vs4
265 ; CHECK-P8-NEXT: xvcvdpuxds v2, vs1
266 ; CHECK-P8-NEXT: xxmrghd vs1, vs2, vs12
267 ; CHECK-P8-NEXT: xxmrghd vs2, vs8, vs7
268 ; CHECK-P8-NEXT: xvcvdpuxds v4, vs0
269 ; CHECK-P8-NEXT: xxmrghd vs0, vs3, vs13
270 ; CHECK-P8-NEXT: xvcvdpuxds v5, vs5
271 ; CHECK-P8-NEXT: xxmrghd vs3, vs6, vs9
272 ; CHECK-P8-NEXT: xvcvdpuxds v0, vs1
273 ; CHECK-P8-NEXT: xvcvdpuxds v1, vs2
274 ; CHECK-P8-NEXT: xvcvdpuxds v6, vs0
275 ; CHECK-P8-NEXT: xxswapd vs0, v3
276 ; CHECK-P8-NEXT: xvcvdpuxds v7, vs3
277 ; CHECK-P8-NEXT: xxswapd vs4, v2
278 ; CHECK-P8-NEXT: xxswapd vs3, v4
279 ; CHECK-P8-NEXT: xxswapd vs1, v5
280 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r4
281 ; CHECK-P8-NEXT: li r4, 96
282 ; CHECK-P8-NEXT: xxswapd vs2, v0
283 ; CHECK-P8-NEXT: xxswapd vs0, v1
284 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
285 ; CHECK-P8-NEXT: xxswapd vs5, v6
286 ; CHECK-P8-NEXT: li r4, 80
287 ; CHECK-P8-NEXT: xxswapd vs1, v7
288 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
289 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r8
290 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r7
291 ; CHECK-P8-NEXT: stxvd2x vs4, r3, r6
292 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
293 ; CHECK-P8-NEXT: stxvd2x vs5, 0, r3
294 ; CHECK-P8-NEXT: blr
295 ;
296 ; CHECK-P9-LABEL: test16elt:
297 ; CHECK-P9: # %bb.0: # %entry
298 ; CHECK-P9-NEXT: lxv vs4, 16(r4)
299 ; CHECK-P9-NEXT: xxsldwi vs5, vs4, vs4, 3
300 ; CHECK-P9-NEXT: xxswapd vs6, vs4
301 ; CHECK-P9-NEXT: lxv vs0, 0(r4)
302 ; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3
303 ; CHECK-P9-NEXT: xxswapd vs2, vs0
304 ; CHECK-P9-NEXT: xscvspdpn f5, vs5
305 ; CHECK-P9-NEXT: xscvspdpn f6, vs6
306 ; CHECK-P9-NEXT: xxmrghd vs5, vs6, vs5
307 ; CHECK-P9-NEXT: xscvspdpn f6, vs4
308 ; CHECK-P9-NEXT: xxsldwi vs4, vs4, vs4, 1
309 ; CHECK-P9-NEXT: lxv vs3, 32(r4)
310 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
311 ; CHECK-P9-NEXT: xxswapd vs7, vs3
312 ; CHECK-P9-NEXT: xscvspdpn f7, vs7
313 ; CHECK-P9-NEXT: xscvspdpn f4, vs4
314 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
315 ; CHECK-P9-NEXT: xxmrghd vs1, vs2, vs1
316 ; CHECK-P9-NEXT: xscvspdpn f2, vs0
317 ; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
318 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
319 ; CHECK-P9-NEXT: xxmrghd vs0, vs2, vs0
320 ; CHECK-P9-NEXT: xxmrghd vs4, vs6, vs4
321 ; CHECK-P9-NEXT: xxsldwi vs6, vs3, vs3, 3
322 ; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1
323 ; CHECK-P9-NEXT: xvcvdpuxds vs5, vs5
324 ; CHECK-P9-NEXT: xscvspdpn f6, vs6
325 ; CHECK-P9-NEXT: xxmrghd vs6, vs7, vs6
326 ; CHECK-P9-NEXT: xscvspdpn f7, vs3
327 ; CHECK-P9-NEXT: xxsldwi vs3, vs3, vs3, 1
328 ; CHECK-P9-NEXT: lxv vs2, 48(r4)
329 ; CHECK-P9-NEXT: xxswapd vs8, vs2
330 ; CHECK-P9-NEXT: xscvspdpn f8, vs8
331 ; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0
332 ; CHECK-P9-NEXT: stxv vs5, 32(r3)
333 ; CHECK-P9-NEXT: xvcvdpuxds vs6, vs6
334 ; CHECK-P9-NEXT: xscvspdpn f3, vs3
335 ; CHECK-P9-NEXT: xxmrghd vs3, vs7, vs3
336 ; CHECK-P9-NEXT: xxsldwi vs7, vs2, vs2, 3
337 ; CHECK-P9-NEXT: xscvspdpn f7, vs7
338 ; CHECK-P9-NEXT: xxmrghd vs7, vs8, vs7
339 ; CHECK-P9-NEXT: xscvspdpn f8, vs2
340 ; CHECK-P9-NEXT: xxsldwi vs2, vs2, vs2, 1
341 ; CHECK-P9-NEXT: stxv vs6, 64(r3)
342 ; CHECK-P9-NEXT: xvcvdpuxds vs4, vs4
343 ; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3
344 ; CHECK-P9-NEXT: xvcvdpuxds vs7, vs7
345 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
346 ; CHECK-P9-NEXT: stxv vs3, 80(r3)
347 ; CHECK-P9-NEXT: xxmrghd vs2, vs8, vs2
348 ; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2
349 ; CHECK-P9-NEXT: stxv vs2, 112(r3)
350 ; CHECK-P9-NEXT: stxv vs7, 96(r3)
351 ; CHECK-P9-NEXT: stxv vs4, 48(r3)
352 ; CHECK-P9-NEXT: stxv vs0, 16(r3)
353 ; CHECK-P9-NEXT: stxv vs1, 0(r3)
354 ; CHECK-P9-NEXT: blr
355 ;
356 ; CHECK-BE-LABEL: test16elt:
357 ; CHECK-BE: # %bb.0: # %entry
358 ; CHECK-BE-NEXT: lxv vs0, 0(r4)
359 ; CHECK-BE-NEXT: lxv vs4, 16(r4)
360 ; CHECK-BE-NEXT: xxsldwi vs2, vs0, vs0, 1
361 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
362 ; CHECK-BE-NEXT: xxsldwi vs5, vs0, vs0, 3
363 ; CHECK-BE-NEXT: xxswapd vs0, vs0
364 ; CHECK-BE-NEXT: xscvspdpn f5, vs5
365 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
366 ; CHECK-BE-NEXT: xxsldwi vs6, vs4, vs4, 1
367 ; CHECK-BE-NEXT: xscvspdpn f6, vs6
368 ; CHECK-BE-NEXT: xxmrghd vs0, vs0, vs5
369 ; CHECK-BE-NEXT: xscvspdpn f5, vs4
370 ; CHECK-BE-NEXT: lxv vs3, 32(r4)
371 ; CHECK-BE-NEXT: xxsldwi vs7, vs3, vs3, 1
372 ; CHECK-BE-NEXT: xscvspdpn f7, vs7
373 ; CHECK-BE-NEXT: xxmrghd vs5, vs5, vs6
374 ; CHECK-BE-NEXT: xxsldwi vs6, vs4, vs4, 3
375 ; CHECK-BE-NEXT: xxswapd vs4, vs4
376 ; CHECK-BE-NEXT: xscvspdpn f6, vs6
377 ; CHECK-BE-NEXT: xscvspdpn f4, vs4
378 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
379 ; CHECK-BE-NEXT: xxmrghd vs1, vs1, vs2
380 ; CHECK-BE-NEXT: lxv vs2, 48(r4)
381 ; CHECK-BE-NEXT: xxsldwi vs8, vs2, vs2, 1
382 ; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1
383 ; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0
384 ; CHECK-BE-NEXT: xvcvdpuxds vs5, vs5
385 ; CHECK-BE-NEXT: xscvspdpn f8, vs8
386 ; CHECK-BE-NEXT: xxmrghd vs4, vs4, vs6
387 ; CHECK-BE-NEXT: xscvspdpn f6, vs3
388 ; CHECK-BE-NEXT: stxv vs0, 16(r3)
389 ; CHECK-BE-NEXT: xxmrghd vs6, vs6, vs7
390 ; CHECK-BE-NEXT: xxsldwi vs7, vs3, vs3, 3
391 ; CHECK-BE-NEXT: xxswapd vs3, vs3
392 ; CHECK-BE-NEXT: xscvspdpn f7, vs7
393 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
394 ; CHECK-BE-NEXT: xxmrghd vs3, vs3, vs7
395 ; CHECK-BE-NEXT: xscvspdpn f7, vs2
396 ; CHECK-BE-NEXT: xxmrghd vs7, vs7, vs8
397 ; CHECK-BE-NEXT: xxsldwi vs8, vs2, vs2, 3
398 ; CHECK-BE-NEXT: xxswapd vs2, vs2
399 ; CHECK-BE-NEXT: xscvspdpn f8, vs8
400 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
401 ; CHECK-BE-NEXT: xxmrghd vs2, vs2, vs8
402 ; CHECK-BE-NEXT: stxv vs5, 32(r3)
403 ; CHECK-BE-NEXT: xvcvdpuxds vs4, vs4
404 ; CHECK-BE-NEXT: xvcvdpuxds vs6, vs6
405 ; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3
406 ; CHECK-BE-NEXT: xvcvdpuxds vs7, vs7
407 ; CHECK-BE-NEXT: stxv vs3, 80(r3)
408 ; CHECK-BE-NEXT: stxv vs7, 96(r3)
409 ; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2
410 ; CHECK-BE-NEXT: stxv vs2, 112(r3)
411 ; CHECK-BE-NEXT: stxv vs6, 64(r3)
412 ; CHECK-BE-NEXT: stxv vs4, 48(r3)
413 ; CHECK-BE-NEXT: stxv vs1, 0(r3)
414 ; CHECK-BE-NEXT: blr
415 entry:
416 %a = load <16 x float>, <16 x float>* %0, align 64
417 %1 = fptoui <16 x float> %a to <16 x i64>
418 store <16 x i64> %1, <16 x i64>* %agg.result, align 128
419 ret void
420 }
422 define <2 x i64> @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
423 ; CHECK-P8-LABEL: test2elt_signed:
424 ; CHECK-P8: # %bb.0: # %entry
425 ; CHECK-P8-NEXT: mtvsrd f0, r3
426 ; CHECK-P8-NEXT: xxswapd v2, vs0
427 ; CHECK-P8-NEXT: xscvspdpn f0, vs0
428 ; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 3
429 ; CHECK-P8-NEXT: xscvspdpn f1, vs1
430 ; CHECK-P8-NEXT: xxmrghd vs0, vs0, vs1
431 ; CHECK-P8-NEXT: xvcvdpuxds v2, vs0
432 ; CHECK-P8-NEXT: blr
433 ;
434 ; CHECK-P9-LABEL: test2elt_signed:
435 ; CHECK-P9: # %bb.0: # %entry
436 ; CHECK-P9-NEXT: mtvsrd f0, r3
437 ; CHECK-P9-NEXT: xxswapd v2, vs0
438 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
439 ; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3
440 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
441 ; CHECK-P9-NEXT: xxmrghd vs0, vs0, vs1
442 ; CHECK-P9-NEXT: xvcvdpuxds v2, vs0
443 ; CHECK-P9-NEXT: blr
444 ;
445 ; CHECK-BE-LABEL: test2elt_signed:
446 ; CHECK-BE: # %bb.0: # %entry
447 ; CHECK-BE-NEXT: mtvsrd f0, r3
448 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
449 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
450 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
451 ; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0
452 ; CHECK-BE-NEXT: xvcvdpuxds v2, vs0
453 ; CHECK-BE-NEXT: blr
454 entry:
455 %0 = bitcast i64 %a.coerce to <2 x float>
456 %1 = fptoui <2 x float> %0 to <2 x i64>
457 ret <2 x i64> %1
458 }
460 define void @test4elt_signed(<4 x i64>* noalias nocapture sret %agg.result, <4 x float> %a) local_unnamed_addr #1 {
461 ; CHECK-P8-LABEL: test4elt_signed:
462 ; CHECK-P8: # %bb.0: # %entry
463 ; CHECK-P8-NEXT: xxsldwi vs0, v2, v2, 3
464 ; CHECK-P8-NEXT: xxswapd vs1, v2
465 ; CHECK-P8-NEXT: li r4, 16
466 ; CHECK-P8-NEXT: xxsldwi vs3, v2, v2, 1
467 ; CHECK-P8-NEXT: xscvspdpn f2, v2
468 ; CHECK-P8-NEXT: xscvspdpn f0, vs0
469 ; CHECK-P8-NEXT: xscvspdpn f1, vs1
470 ; CHECK-P8-NEXT: xscvspdpn f3, vs3
471 ; CHECK-P8-NEXT: xxmrghd vs0, vs1, vs0
472 ; CHECK-P8-NEXT: xxmrghd vs1, vs2, vs3
473 ; CHECK-P8-NEXT: xvcvdpuxds v2, vs0
474 ; CHECK-P8-NEXT: xvcvdpuxds v3, vs1
475 ; CHECK-P8-NEXT: xxswapd vs1, v2
476 ; CHECK-P8-NEXT: xxswapd vs0, v3
477 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r4
478 ; CHECK-P8-NEXT: stxvd2x vs1, 0, r3
479 ; CHECK-P8-NEXT: blr
480 ;
481 ; CHECK-P9-LABEL: test4elt_signed:
482 ; CHECK-P9: # %bb.0: # %entry
483 ; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 3
484 ; CHECK-P9-NEXT: xxswapd vs1, v2
485 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
486 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
487 ; CHECK-P9-NEXT: xxsldwi vs2, v2, v2, 1
488 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
489 ; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0
490 ; CHECK-P9-NEXT: xscvspdpn f1, v2
491 ; CHECK-P9-NEXT: xxmrghd vs1, vs1, vs2
492 ; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0
493 ; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1
494 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
495 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
496 ; CHECK-P9-NEXT: blr
497 ;
498 ; CHECK-BE-LABEL: test4elt_signed:
499 ; CHECK-BE: # %bb.0: # %entry
500 ; CHECK-BE-NEXT: xxsldwi vs1, v2, v2, 1
501 ; CHECK-BE-NEXT: xscvspdpn f0, v2
502 ; CHECK-BE-NEXT: xxswapd vs2, v2
503 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
504 ; CHECK-BE-NEXT: xxmrghd vs0, vs0, vs1
505 ; CHECK-BE-NEXT: xxsldwi vs1, v2, v2, 3
506 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
507 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
508 ; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0
509 ; CHECK-BE-NEXT: xxmrghd vs1, vs2, vs1
510 ; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1
511 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
512 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
513 ; CHECK-BE-NEXT: blr
514 entry:
515 %0 = fptoui <4 x float> %a to <4 x i64>
516 store <4 x i64> %0, <4 x i64>* %agg.result, align 32
517 ret void
518 }
520 define void @test8elt_signed(<8 x i64>* noalias nocapture sret %agg.result, <8 x float>* nocapture readonly) local_unnamed_addr #2 {
521 ; CHECK-P8-LABEL: test8elt_signed:
522 ; CHECK-P8: # %bb.0: # %entry
523 ; CHECK-P8-NEXT: li r5, 16
524 ; CHECK-P8-NEXT: lvx v3, 0, r4
525 ; CHECK-P8-NEXT: li r6, 32
526 ; CHECK-P8-NEXT: lvx v2, r4, r5
527 ; CHECK-P8-NEXT: li r4, 48
528 ; CHECK-P8-NEXT: xxsldwi vs5, v3, v3, 3
529 ; CHECK-P8-NEXT: xxswapd vs6, v3
530 ; CHECK-P8-NEXT: xxsldwi vs0, v2, v2, 3
531 ; CHECK-P8-NEXT: xxswapd vs1, v2
532 ; CHECK-P8-NEXT: xxsldwi vs3, v2, v2, 1
533 ; CHECK-P8-NEXT: xxsldwi vs7, v3, v3, 1
534 ; CHECK-P8-NEXT: xscvspdpn f2, v2
535 ; CHECK-P8-NEXT: xscvspdpn f4, v3
536 ; CHECK-P8-NEXT: xscvspdpn f0, vs0
537 ; CHECK-P8-NEXT: xscvspdpn f1, vs1
538 ; CHECK-P8-NEXT: xscvspdpn f3, vs3
539 ; CHECK-P8-NEXT: xscvspdpn f5, vs5
540 ; CHECK-P8-NEXT: xscvspdpn f6, vs6
541 ; CHECK-P8-NEXT: xscvspdpn f7, vs7
542 ; CHECK-P8-NEXT: xxmrghd vs0, vs1, vs0
543 ; CHECK-P8-NEXT: xxmrghd vs1, vs2, vs3
544 ; CHECK-P8-NEXT: xxmrghd vs2, vs6, vs5
545 ; CHECK-P8-NEXT: xvcvdpuxds v2, vs0
546 ; CHECK-P8-NEXT: xxmrghd vs3, vs4, vs7
547 ; CHECK-P8-NEXT: xvcvdpuxds v3, vs1
548 ; CHECK-P8-NEXT: xvcvdpuxds v4, vs2
549 ; CHECK-P8-NEXT: xvcvdpuxds v5, vs3
550 ; CHECK-P8-NEXT: xxswapd vs1, v2
551 ; CHECK-P8-NEXT: xxswapd vs0, v3
552 ; CHECK-P8-NEXT: xxswapd vs3, v4
553 ; CHECK-P8-NEXT: xxswapd vs2, v5
554 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r4
555 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r6
556 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r5
557 ; CHECK-P8-NEXT: stxvd2x vs3, 0, r3
558 ; CHECK-P8-NEXT: blr
559 ;
560 ; CHECK-P9-LABEL: test8elt_signed:
561 ; CHECK-P9: # %bb.0: # %entry
562 ; CHECK-P9-NEXT: lxv vs0, 0(r4)
563 ; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3
564 ; CHECK-P9-NEXT: xxswapd vs2, vs0
565 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
566 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
567 ; CHECK-P9-NEXT: xscvspdpn f3, vs0
568 ; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
569 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
570 ; CHECK-P9-NEXT: xxmrghd vs1, vs2, vs1
571 ; CHECK-P9-NEXT: lxv vs2, 16(r4)
572 ; CHECK-P9-NEXT: xxmrghd vs0, vs3, vs0
573 ; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1
574 ; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0
575 ; CHECK-P9-NEXT: xxsldwi vs3, vs2, vs2, 3
576 ; CHECK-P9-NEXT: xxswapd vs4, vs2
577 ; CHECK-P9-NEXT: xscvspdpn f3, vs3
578 ; CHECK-P9-NEXT: xscvspdpn f4, vs4
579 ; CHECK-P9-NEXT: stxv vs0, 16(r3)
580 ; CHECK-P9-NEXT: xxmrghd vs3, vs4, vs3
581 ; CHECK-P9-NEXT: xscvspdpn f4, vs2
582 ; CHECK-P9-NEXT: xxsldwi vs2, vs2, vs2, 1
583 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
584 ; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3
585 ; CHECK-P9-NEXT: xxmrghd vs2, vs4, vs2
586 ; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2
587 ; CHECK-P9-NEXT: stxv vs3, 32(r3)
588 ; CHECK-P9-NEXT: stxv vs2, 48(r3)
589 ; CHECK-P9-NEXT: stxv vs1, 0(r3)
590 ; CHECK-P9-NEXT: blr
591 ;
592 ; CHECK-BE-LABEL: test8elt_signed:
593 ; CHECK-BE: # %bb.0: # %entry
594 ; CHECK-BE-NEXT: lxv vs1, 0(r4)
595 ; CHECK-BE-NEXT: xxsldwi vs3, vs1, vs1, 1
596 ; CHECK-BE-NEXT: xscvspdpn f2, vs1
597 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
598 ; CHECK-BE-NEXT: lxv vs0, 16(r4)
599 ; CHECK-BE-NEXT: xxsldwi vs4, vs0, vs0, 1
600 ; CHECK-BE-NEXT: xscvspdpn f4, vs4
601 ; CHECK-BE-NEXT: xxmrghd vs2, vs2, vs3
602 ; CHECK-BE-NEXT: xxsldwi vs3, vs1, vs1, 3
603 ; CHECK-BE-NEXT: xxswapd vs1, vs1
604 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
605 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
606 ; CHECK-BE-NEXT: xxmrghd vs1, vs1, vs3
607 ; CHECK-BE-NEXT: xscvspdpn f3, vs0
608 ; CHECK-BE-NEXT: xxmrghd vs3, vs3, vs4
609 ; CHECK-BE-NEXT: xxsldwi vs4, vs0, vs0, 3
610 ; CHECK-BE-NEXT: xxswapd vs0, vs0
611 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
612 ; CHECK-BE-NEXT: xscvspdpn f4, vs4
613 ; CHECK-BE-NEXT: xxmrghd vs0, vs0, vs4
614 ; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2
615 ; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1
616 ; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3
617 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
618 ; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0
619 ; CHECK-BE-NEXT: stxv vs3, 32(r3)
620 ; CHECK-BE-NEXT: stxv vs0, 48(r3)
621 ; CHECK-BE-NEXT: stxv vs2, 0(r3)
622 ; CHECK-BE-NEXT: blr
623 entry:
624 %a = load <8 x float>, <8 x float>* %0, align 32
625 %1 = fptoui <8 x float> %a to <8 x i64>
626 store <8 x i64> %1, <8 x i64>* %agg.result, align 64
627 ret void
628 }
630 define void @test16elt_signed(<16 x i64>* noalias nocapture sret %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #2 {
631 ; CHECK-P8-LABEL: test16elt_signed:
632 ; CHECK-P8: # %bb.0: # %entry
633 ; CHECK-P8-NEXT: li r5, 16
634 ; CHECK-P8-NEXT: li r7, 48
635 ; CHECK-P8-NEXT: li r6, 32
636 ; CHECK-P8-NEXT: lvx v4, 0, r4
637 ; CHECK-P8-NEXT: li r8, 64
638 ; CHECK-P8-NEXT: lvx v5, r4, r5
639 ; CHECK-P8-NEXT: lvx v3, r4, r7
640 ; CHECK-P8-NEXT: lvx v2, r4, r6
641 ; CHECK-P8-NEXT: li r4, 112
642 ; CHECK-P8-NEXT: xxsldwi vs13, v4, v4, 3
643 ; CHECK-P8-NEXT: xscvspdpn f6, v4
644 ; CHECK-P8-NEXT: xxsldwi vs1, v5, v5, 3
645 ; CHECK-P8-NEXT: xxswapd vs3, v5
646 ; CHECK-P8-NEXT: xxsldwi vs9, v3, v3, 1
647 ; CHECK-P8-NEXT: xscvspdpn f4, v3
648 ; CHECK-P8-NEXT: xxsldwi vs5, v5, v5, 1
649 ; CHECK-P8-NEXT: xxsldwi vs10, v3, v3, 3
650 ; CHECK-P8-NEXT: xscvspdpn f1, vs1
651 ; CHECK-P8-NEXT: xxswapd vs11, v3
652 ; CHECK-P8-NEXT: xscvspdpn f3, vs3
653 ; CHECK-P8-NEXT: xxsldwi vs7, v2, v2, 3
654 ; CHECK-P8-NEXT: xscvspdpn f9, vs9
655 ; CHECK-P8-NEXT: xxswapd vs8, v2
656 ; CHECK-P8-NEXT: xscvspdpn f0, v5
657 ; CHECK-P8-NEXT: xxsldwi vs12, v2, v2, 1
658 ; CHECK-P8-NEXT: xscvspdpn f2, v2
659 ; CHECK-P8-NEXT: xxswapd v2, v4
660 ; CHECK-P8-NEXT: xscvspdpn f5, vs5
661 ; CHECK-P8-NEXT: xxsldwi v3, v4, v4, 1
662 ; CHECK-P8-NEXT: xscvspdpn f10, vs10
663 ; CHECK-P8-NEXT: xscvspdpn f11, vs11
664 ; CHECK-P8-NEXT: xxmrghd vs1, vs3, vs1
665 ; CHECK-P8-NEXT: xscvspdpn f7, vs7
666 ; CHECK-P8-NEXT: xxmrghd vs4, vs4, vs9
667 ; CHECK-P8-NEXT: xscvspdpn f8, vs8
668 ; CHECK-P8-NEXT: xscvspdpn f12, vs12
669 ; CHECK-P8-NEXT: xscvspdpn f13, vs13
670 ; CHECK-P8-NEXT: xxmrghd vs0, vs0, vs5
671 ; CHECK-P8-NEXT: xscvspdpn f3, v2
672 ; CHECK-P8-NEXT: xscvspdpn f9, v3
673 ; CHECK-P8-NEXT: xxmrghd vs5, vs11, vs10
674 ; CHECK-P8-NEXT: xvcvdpuxds v3, vs4
675 ; CHECK-P8-NEXT: xvcvdpuxds v2, vs1
676 ; CHECK-P8-NEXT: xxmrghd vs1, vs2, vs12
677 ; CHECK-P8-NEXT: xxmrghd vs2, vs8, vs7
678 ; CHECK-P8-NEXT: xvcvdpuxds v4, vs0
679 ; CHECK-P8-NEXT: xxmrghd vs0, vs3, vs13
680 ; CHECK-P8-NEXT: xvcvdpuxds v5, vs5
681 ; CHECK-P8-NEXT: xxmrghd vs3, vs6, vs9
682 ; CHECK-P8-NEXT: xvcvdpuxds v0, vs1
683 ; CHECK-P8-NEXT: xvcvdpuxds v1, vs2
684 ; CHECK-P8-NEXT: xvcvdpuxds v6, vs0
685 ; CHECK-P8-NEXT: xxswapd vs0, v3
686 ; CHECK-P8-NEXT: xvcvdpuxds v7, vs3
687 ; CHECK-P8-NEXT: xxswapd vs4, v2
688 ; CHECK-P8-NEXT: xxswapd vs3, v4
689 ; CHECK-P8-NEXT: xxswapd vs1, v5
690 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r4
691 ; CHECK-P8-NEXT: li r4, 96
692 ; CHECK-P8-NEXT: xxswapd vs2, v0
693 ; CHECK-P8-NEXT: xxswapd vs0, v1
694 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
695 ; CHECK-P8-NEXT: xxswapd vs5, v6
696 ; CHECK-P8-NEXT: li r4, 80
697 ; CHECK-P8-NEXT: xxswapd vs1, v7
698 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
699 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r8
700 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r7
701 ; CHECK-P8-NEXT: stxvd2x vs4, r3, r6
702 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
703 ; CHECK-P8-NEXT: stxvd2x vs5, 0, r3
704 ; CHECK-P8-NEXT: blr
705 ;
706 ; CHECK-P9-LABEL: test16elt_signed:
707 ; CHECK-P9: # %bb.0: # %entry
708 ; CHECK-P9-NEXT: lxv vs4, 16(r4)
709 ; CHECK-P9-NEXT: xxsldwi vs5, vs4, vs4, 3
710 ; CHECK-P9-NEXT: xxswapd vs6, vs4
711 ; CHECK-P9-NEXT: lxv vs0, 0(r4)
712 ; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3
713 ; CHECK-P9-NEXT: xxswapd vs2, vs0
714 ; CHECK-P9-NEXT: xscvspdpn f5, vs5
715 ; CHECK-P9-NEXT: xscvspdpn f6, vs6
716 ; CHECK-P9-NEXT: xxmrghd vs5, vs6, vs5
717 ; CHECK-P9-NEXT: xscvspdpn f6, vs4
718 ; CHECK-P9-NEXT: xxsldwi vs4, vs4, vs4, 1
719 ; CHECK-P9-NEXT: lxv vs3, 32(r4)
720 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
721 ; CHECK-P9-NEXT: xxswapd vs7, vs3
722 ; CHECK-P9-NEXT: xscvspdpn f7, vs7
723 ; CHECK-P9-NEXT: xscvspdpn f4, vs4
724 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
725 ; CHECK-P9-NEXT: xxmrghd vs1, vs2, vs1
726 ; CHECK-P9-NEXT: xscvspdpn f2, vs0
727 ; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
728 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
729 ; CHECK-P9-NEXT: xxmrghd vs0, vs2, vs0
730 ; CHECK-P9-NEXT: xxmrghd vs4, vs6, vs4
731 ; CHECK-P9-NEXT: xxsldwi vs6, vs3, vs3, 3
732 ; CHECK-P9-NEXT: xvcvdpuxds vs1, vs1
733 ; CHECK-P9-NEXT: xvcvdpuxds vs5, vs5
734 ; CHECK-P9-NEXT: xscvspdpn f6, vs6
735 ; CHECK-P9-NEXT: xxmrghd vs6, vs7, vs6
736 ; CHECK-P9-NEXT: xscvspdpn f7, vs3
737 ; CHECK-P9-NEXT: xxsldwi vs3, vs3, vs3, 1
738 ; CHECK-P9-NEXT: lxv vs2, 48(r4)
739 ; CHECK-P9-NEXT: xxswapd vs8, vs2
740 ; CHECK-P9-NEXT: xscvspdpn f8, vs8
741 ; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0
742 ; CHECK-P9-NEXT: stxv vs5, 32(r3)
743 ; CHECK-P9-NEXT: xvcvdpuxds vs6, vs6
744 ; CHECK-P9-NEXT: xscvspdpn f3, vs3
745 ; CHECK-P9-NEXT: xxmrghd vs3, vs7, vs3
746 ; CHECK-P9-NEXT: xxsldwi vs7, vs2, vs2, 3
747 ; CHECK-P9-NEXT: xscvspdpn f7, vs7
748 ; CHECK-P9-NEXT: xxmrghd vs7, vs8, vs7
749 ; CHECK-P9-NEXT: xscvspdpn f8, vs2
750 ; CHECK-P9-NEXT: xxsldwi vs2, vs2, vs2, 1
751 ; CHECK-P9-NEXT: stxv vs6, 64(r3)
752 ; CHECK-P9-NEXT: xvcvdpuxds vs4, vs4
753 ; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3
754 ; CHECK-P9-NEXT: xvcvdpuxds vs7, vs7
755 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
756 ; CHECK-P9-NEXT: stxv vs3, 80(r3)
757 ; CHECK-P9-NEXT: xxmrghd vs2, vs8, vs2
758 ; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2
759 ; CHECK-P9-NEXT: stxv vs2, 112(r3)
760 ; CHECK-P9-NEXT: stxv vs7, 96(r3)
761 ; CHECK-P9-NEXT: stxv vs4, 48(r3)
762 ; CHECK-P9-NEXT: stxv vs0, 16(r3)
763 ; CHECK-P9-NEXT: stxv vs1, 0(r3)
764 ; CHECK-P9-NEXT: blr
765 ;
766 ; CHECK-BE-LABEL: test16elt_signed:
767 ; CHECK-BE: # %bb.0: # %entry
768 ; CHECK-BE-NEXT: lxv vs0, 0(r4)
769 ; CHECK-BE-NEXT: lxv vs4, 16(r4)
770 ; CHECK-BE-NEXT: xxsldwi vs2, vs0, vs0, 1
771 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
772 ; CHECK-BE-NEXT: xxsldwi vs5, vs0, vs0, 3
773 ; CHECK-BE-NEXT: xxswapd vs0, vs0
774 ; CHECK-BE-NEXT: xscvspdpn f5, vs5
775 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
776 ; CHECK-BE-NEXT: xxsldwi vs6, vs4, vs4, 1
777 ; CHECK-BE-NEXT: xscvspdpn f6, vs6
778 ; CHECK-BE-NEXT: xxmrghd vs0, vs0, vs5
779 ; CHECK-BE-NEXT: xscvspdpn f5, vs4
780 ; CHECK-BE-NEXT: lxv vs3, 32(r4)
781 ; CHECK-BE-NEXT: xxsldwi vs7, vs3, vs3, 1
782 ; CHECK-BE-NEXT: xscvspdpn f7, vs7
783 ; CHECK-BE-NEXT: xxmrghd vs5, vs5, vs6
784 ; CHECK-BE-NEXT: xxsldwi vs6, vs4, vs4, 3
785 ; CHECK-BE-NEXT: xxswapd vs4, vs4
786 ; CHECK-BE-NEXT: xscvspdpn f6, vs6
787 ; CHECK-BE-NEXT: xscvspdpn f4, vs4
788 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
789 ; CHECK-BE-NEXT: xxmrghd vs1, vs1, vs2
790 ; CHECK-BE-NEXT: lxv vs2, 48(r4)
791 ; CHECK-BE-NEXT: xxsldwi vs8, vs2, vs2, 1
792 ; CHECK-BE-NEXT: xvcvdpuxds vs1, vs1
793 ; CHECK-BE-NEXT: xvcvdpuxds vs0, vs0
794 ; CHECK-BE-NEXT: xvcvdpuxds vs5, vs5
795 ; CHECK-BE-NEXT: xscvspdpn f8, vs8
796 ; CHECK-BE-NEXT: xxmrghd vs4, vs4, vs6
797 ; CHECK-BE-NEXT: xscvspdpn f6, vs3
798 ; CHECK-BE-NEXT: stxv vs0, 16(r3)
799 ; CHECK-BE-NEXT: xxmrghd vs6, vs6, vs7
800 ; CHECK-BE-NEXT: xxsldwi vs7, vs3, vs3, 3
801 ; CHECK-BE-NEXT: xxswapd vs3, vs3
802 ; CHECK-BE-NEXT: xscvspdpn f7, vs7
803 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
804 ; CHECK-BE-NEXT: xxmrghd vs3, vs3, vs7
805 ; CHECK-BE-NEXT: xscvspdpn f7, vs2
806 ; CHECK-BE-NEXT: xxmrghd vs7, vs7, vs8
807 ; CHECK-BE-NEXT: xxsldwi vs8, vs2, vs2, 3
808 ; CHECK-BE-NEXT: xxswapd vs2, vs2
809 ; CHECK-BE-NEXT: xscvspdpn f8, vs8
810 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
811 ; CHECK-BE-NEXT: xxmrghd vs2, vs2, vs8
812 ; CHECK-BE-NEXT: stxv vs5, 32(r3)
813 ; CHECK-BE-NEXT: xvcvdpuxds vs4, vs4
814 ; CHECK-BE-NEXT: xvcvdpuxds vs6, vs6
815 ; CHECK-BE-NEXT: xvcvdpuxds vs3, vs3
816 ; CHECK-BE-NEXT: xvcvdpuxds vs7, vs7
817 ; CHECK-BE-NEXT: stxv vs3, 80(r3)
818 ; CHECK-BE-NEXT: stxv vs7, 96(r3)
819 ; CHECK-BE-NEXT: xvcvdpuxds vs2, vs2
820 ; CHECK-BE-NEXT: stxv vs2, 112(r3)
821 ; CHECK-BE-NEXT: stxv vs6, 64(r3)
822 ; CHECK-BE-NEXT: stxv vs4, 48(r3)
823 ; CHECK-BE-NEXT: stxv vs1, 0(r3)
824 ; CHECK-BE-NEXT: blr
825 entry:
826 %a = load <16 x float>, <16 x float>* %0, align 64
827 %1 = fptoui <16 x float> %a to <16 x i64>
828 store <16 x i64> %1, <16 x i64>* %agg.result, align 128
829 ret void
830 }