| blob | 1a9790106db77cbc0e5e1b09a2561df2074acf08 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3 ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
4 ; RUN: FileCheck %s --check-prefix=CHECK-P8
5 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
6 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
7 ; RUN: FileCheck %s --check-prefix=CHECK-P9
8 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
9 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
10 ; RUN: FileCheck %s --check-prefix=CHECK-BE
12 define <2 x double> @test2elt(i16 %a.coerce) local_unnamed_addr #0 {
13 ; CHECK-P8-LABEL: test2elt:
14 ; CHECK-P8: # %bb.0: # %entry
15 ; CHECK-P8-NEXT: addis r4, r2, .LCPI0_0@toc@ha
16 ; CHECK-P8-NEXT: mtvsrd f0, r3
17 ; CHECK-P8-NEXT: addi r3, r4, .LCPI0_0@toc@l
18 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
19 ; CHECK-P8-NEXT: xxswapd v2, vs0
20 ; CHECK-P8-NEXT: lvx v3, 0, r3
21 ; CHECK-P8-NEXT: vperm v2, v4, v2, v3
22 ; CHECK-P8-NEXT: xvcvuxddp v2, v2
23 ; CHECK-P8-NEXT: blr
24 ;
25 ; CHECK-P9-LABEL: test2elt:
26 ; CHECK-P9: # %bb.0: # %entry
27 ; CHECK-P9-NEXT: mtvsrws v2, r3
28 ; CHECK-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha
29 ; CHECK-P9-NEXT: addi r3, r3, .LCPI0_0@toc@l
30 ; CHECK-P9-NEXT: lxvx v3, 0, r3
31 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
32 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
33 ; CHECK-P9-NEXT: xvcvuxddp v2, v2
34 ; CHECK-P9-NEXT: blr
35 ;
36 ; CHECK-BE-LABEL: test2elt:
37 ; CHECK-BE: # %bb.0: # %entry
38 ; CHECK-BE-NEXT: mtvsrws v2, r3
39 ; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha
40 ; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l
41 ; CHECK-BE-NEXT: lxvx v3, 0, r3
42 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
43 ; CHECK-BE-NEXT: vperm v2, v2, v4, v3
44 ; CHECK-BE-NEXT: xvcvuxddp v2, v2
45 ; CHECK-BE-NEXT: blr
46 entry:
47 %0 = bitcast i16 %a.coerce to <2 x i8>
48 %1 = uitofp <2 x i8> %0 to <2 x double>
49 ret <2 x double> %1
50 }
52 define void @test4elt(<4 x double>* noalias nocapture sret %agg.result, i32 %a.coerce) local_unnamed_addr #1 {
53 ; CHECK-P8-LABEL: test4elt:
54 ; CHECK-P8: # %bb.0: # %entry
55 ; CHECK-P8-NEXT: addis r5, r2, .LCPI1_0@toc@ha
56 ; CHECK-P8-NEXT: mtvsrd f0, r4
57 ; CHECK-P8-NEXT: addis r4, r2, .LCPI1_1@toc@ha
58 ; CHECK-P8-NEXT: addi r5, r5, .LCPI1_0@toc@l
59 ; CHECK-P8-NEXT: addi r4, r4, .LCPI1_1@toc@l
60 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
61 ; CHECK-P8-NEXT: lvx v2, 0, r5
62 ; CHECK-P8-NEXT: xxswapd v3, vs0
63 ; CHECK-P8-NEXT: lvx v5, 0, r4
64 ; CHECK-P8-NEXT: li r4, 16
65 ; CHECK-P8-NEXT: vperm v2, v4, v3, v2
66 ; CHECK-P8-NEXT: vperm v3, v4, v3, v5
67 ; CHECK-P8-NEXT: xvcvuxddp vs0, v2
68 ; CHECK-P8-NEXT: xvcvuxddp vs1, v3
69 ; CHECK-P8-NEXT: xxswapd vs0, vs0
70 ; CHECK-P8-NEXT: xxswapd vs1, vs1
71 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
72 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
73 ; CHECK-P8-NEXT: blr
74 ;
75 ; CHECK-P9-LABEL: test4elt:
76 ; CHECK-P9: # %bb.0: # %entry
77 ; CHECK-P9-NEXT: mtvsrws v2, r4
78 ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha
79 ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l
80 ; CHECK-P9-NEXT: lxvx v3, 0, r4
81 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
82 ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_1@toc@ha
83 ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_1@toc@l
84 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
85 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3
86 ; CHECK-P9-NEXT: lxvx v3, 0, r4
87 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
88 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
89 ; CHECK-P9-NEXT: xvcvuxddp vs1, v2
90 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
91 ; CHECK-P9-NEXT: blr
92 ;
93 ; CHECK-BE-LABEL: test4elt:
94 ; CHECK-BE: # %bb.0: # %entry
95 ; CHECK-BE-NEXT: mtvsrws v2, r4
96 ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha
97 ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_0@toc@l
98 ; CHECK-BE-NEXT: lxvx v3, 0, r4
99 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
100 ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_1@toc@ha
101 ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_1@toc@l
102 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
103 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3
104 ; CHECK-BE-NEXT: lxvx v3, 0, r4
105 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
106 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
107 ; CHECK-BE-NEXT: xvcvuxddp vs1, v2
108 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
109 ; CHECK-BE-NEXT: blr
110 entry:
111 %0 = bitcast i32 %a.coerce to <4 x i8>
112 %1 = uitofp <4 x i8> %0 to <4 x double>
113 store <4 x double> %1, <4 x double>* %agg.result, align 32
114 ret void
115 }
117 define void @test8elt(<8 x double>* noalias nocapture sret %agg.result, i64 %a.coerce) local_unnamed_addr #1 {
118 ; CHECK-P8-LABEL: test8elt:
119 ; CHECK-P8: # %bb.0: # %entry
120 ; CHECK-P8-NEXT: addis r5, r2, .LCPI2_0@toc@ha
121 ; CHECK-P8-NEXT: mtvsrd f0, r4
122 ; CHECK-P8-NEXT: addis r4, r2, .LCPI2_2@toc@ha
123 ; CHECK-P8-NEXT: addi r5, r5, .LCPI2_0@toc@l
124 ; CHECK-P8-NEXT: addi r4, r4, .LCPI2_2@toc@l
125 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
126 ; CHECK-P8-NEXT: lvx v2, 0, r5
127 ; CHECK-P8-NEXT: addis r5, r2, .LCPI2_3@toc@ha
128 ; CHECK-P8-NEXT: lvx v5, 0, r4
129 ; CHECK-P8-NEXT: addis r4, r2, .LCPI2_1@toc@ha
130 ; CHECK-P8-NEXT: xxswapd v3, vs0
131 ; CHECK-P8-NEXT: addi r5, r5, .LCPI2_3@toc@l
132 ; CHECK-P8-NEXT: addi r4, r4, .LCPI2_1@toc@l
133 ; CHECK-P8-NEXT: lvx v0, 0, r5
134 ; CHECK-P8-NEXT: lvx v1, 0, r4
135 ; CHECK-P8-NEXT: li r4, 48
136 ; CHECK-P8-NEXT: li r5, 32
137 ; CHECK-P8-NEXT: vperm v2, v4, v3, v2
138 ; CHECK-P8-NEXT: vperm v5, v4, v3, v5
139 ; CHECK-P8-NEXT: vperm v0, v4, v3, v0
140 ; CHECK-P8-NEXT: vperm v3, v4, v3, v1
141 ; CHECK-P8-NEXT: xvcvuxddp vs0, v2
142 ; CHECK-P8-NEXT: xvcvuxddp vs1, v5
143 ; CHECK-P8-NEXT: xvcvuxddp vs2, v0
144 ; CHECK-P8-NEXT: xvcvuxddp vs3, v3
145 ; CHECK-P8-NEXT: xxswapd vs0, vs0
146 ; CHECK-P8-NEXT: xxswapd vs1, vs1
147 ; CHECK-P8-NEXT: xxswapd vs2, vs2
148 ; CHECK-P8-NEXT: xxswapd vs3, vs3
149 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
150 ; CHECK-P8-NEXT: li r4, 16
151 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
152 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
153 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
154 ; CHECK-P8-NEXT: blr
155 ;
156 ; CHECK-P9-LABEL: test8elt:
157 ; CHECK-P9: # %bb.0: # %entry
158 ; CHECK-P9-NEXT: mtvsrd f0, r4
159 ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha
160 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l
161 ; CHECK-P9-NEXT: lxvx v3, 0, r4
162 ; CHECK-P9-NEXT: xxswapd v2, vs0
163 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
164 ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha
165 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l
166 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
167 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3
168 ; CHECK-P9-NEXT: lxvx v3, 0, r4
169 ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_2@toc@ha
170 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_2@toc@l
171 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
172 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
173 ; CHECK-P9-NEXT: xvcvuxddp vs1, v3
174 ; CHECK-P9-NEXT: lxvx v3, 0, r4
175 ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_3@toc@ha
176 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_3@toc@l
177 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
178 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
179 ; CHECK-P9-NEXT: xvcvuxddp vs2, v3
180 ; CHECK-P9-NEXT: lxvx v3, 0, r4
181 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
182 ; CHECK-P9-NEXT: stxv vs2, 32(r3)
183 ; CHECK-P9-NEXT: xvcvuxddp vs3, v2
184 ; CHECK-P9-NEXT: stxv vs3, 48(r3)
185 ; CHECK-P9-NEXT: blr
186 ;
187 ; CHECK-BE-LABEL: test8elt:
188 ; CHECK-BE: # %bb.0: # %entry
189 ; CHECK-BE-NEXT: mtvsrd v2, r4
190 ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha
191 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l
192 ; CHECK-BE-NEXT: lxvx v3, 0, r4
193 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
194 ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha
195 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l
196 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
197 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3
198 ; CHECK-BE-NEXT: lxvx v3, 0, r4
199 ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_2@toc@ha
200 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_2@toc@l
201 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
202 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
203 ; CHECK-BE-NEXT: xvcvuxddp vs1, v3
204 ; CHECK-BE-NEXT: lxvx v3, 0, r4
205 ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_3@toc@ha
206 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_3@toc@l
207 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
208 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
209 ; CHECK-BE-NEXT: xvcvuxddp vs2, v3
210 ; CHECK-BE-NEXT: lxvx v3, 0, r4
211 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
212 ; CHECK-BE-NEXT: stxv vs2, 32(r3)
213 ; CHECK-BE-NEXT: xvcvuxddp vs3, v2
214 ; CHECK-BE-NEXT: stxv vs3, 48(r3)
215 ; CHECK-BE-NEXT: blr
216 entry:
217 %0 = bitcast i64 %a.coerce to <8 x i8>
218 %1 = uitofp <8 x i8> %0 to <8 x double>
219 store <8 x double> %1, <8 x double>* %agg.result, align 64
220 ret void
221 }
223 define void @test16elt(<16 x double>* noalias nocapture sret %agg.result, <16 x i8> %a) local_unnamed_addr #2 {
224 ; CHECK-P8-LABEL: test16elt:
225 ; CHECK-P8: # %bb.0: # %entry
226 ; CHECK-P8-NEXT: addis r4, r2, .LCPI3_0@toc@ha
227 ; CHECK-P8-NEXT: addis r5, r2, .LCPI3_1@toc@ha
228 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
229 ; CHECK-P8-NEXT: addi r4, r4, .LCPI3_0@toc@l
230 ; CHECK-P8-NEXT: addi r5, r5, .LCPI3_1@toc@l
231 ; CHECK-P8-NEXT: lvx v3, 0, r4
232 ; CHECK-P8-NEXT: addis r4, r2, .LCPI3_2@toc@ha
233 ; CHECK-P8-NEXT: lvx v5, 0, r5
234 ; CHECK-P8-NEXT: addis r5, r2, .LCPI3_4@toc@ha
235 ; CHECK-P8-NEXT: addi r4, r4, .LCPI3_2@toc@l
236 ; CHECK-P8-NEXT: addi r5, r5, .LCPI3_4@toc@l
237 ; CHECK-P8-NEXT: lvx v0, 0, r4
238 ; CHECK-P8-NEXT: addis r4, r2, .LCPI3_6@toc@ha
239 ; CHECK-P8-NEXT: lvx v1, 0, r5
240 ; CHECK-P8-NEXT: addis r5, r2, .LCPI3_7@toc@ha
241 ; CHECK-P8-NEXT: addi r4, r4, .LCPI3_6@toc@l
242 ; CHECK-P8-NEXT: addi r5, r5, .LCPI3_7@toc@l
243 ; CHECK-P8-NEXT: vperm v3, v4, v2, v3
244 ; CHECK-P8-NEXT: lvx v6, 0, r4
245 ; CHECK-P8-NEXT: addis r4, r2, .LCPI3_5@toc@ha
246 ; CHECK-P8-NEXT: lvx v7, 0, r5
247 ; CHECK-P8-NEXT: addis r5, r2, .LCPI3_3@toc@ha
248 ; CHECK-P8-NEXT: vperm v5, v4, v2, v5
249 ; CHECK-P8-NEXT: addi r4, r4, .LCPI3_5@toc@l
250 ; CHECK-P8-NEXT: addi r5, r5, .LCPI3_3@toc@l
251 ; CHECK-P8-NEXT: vperm v0, v4, v2, v0
252 ; CHECK-P8-NEXT: lvx v8, 0, r4
253 ; CHECK-P8-NEXT: lvx v9, 0, r5
254 ; CHECK-P8-NEXT: vperm v1, v4, v2, v1
255 ; CHECK-P8-NEXT: li r4, 112
256 ; CHECK-P8-NEXT: li r5, 96
257 ; CHECK-P8-NEXT: vperm v6, v4, v2, v6
258 ; CHECK-P8-NEXT: vperm v7, v4, v2, v7
259 ; CHECK-P8-NEXT: vperm v8, v4, v2, v8
260 ; CHECK-P8-NEXT: vperm v2, v4, v2, v9
261 ; CHECK-P8-NEXT: xvcvuxddp vs0, v0
262 ; CHECK-P8-NEXT: xvcvuxddp vs1, v1
263 ; CHECK-P8-NEXT: xvcvuxddp vs2, v6
264 ; CHECK-P8-NEXT: xvcvuxddp vs3, v7
265 ; CHECK-P8-NEXT: xvcvuxddp vs4, v8
266 ; CHECK-P8-NEXT: xvcvuxddp vs5, v2
267 ; CHECK-P8-NEXT: xvcvuxddp vs6, v3
268 ; CHECK-P8-NEXT: xxswapd vs0, vs0
269 ; CHECK-P8-NEXT: xvcvuxddp vs7, v5
270 ; CHECK-P8-NEXT: xxswapd vs1, vs1
271 ; CHECK-P8-NEXT: xxswapd vs2, vs2
272 ; CHECK-P8-NEXT: xxswapd vs3, vs3
273 ; CHECK-P8-NEXT: xxswapd vs4, vs4
274 ; CHECK-P8-NEXT: xxswapd vs5, vs5
275 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
276 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r5
277 ; CHECK-P8-NEXT: li r4, 80
278 ; CHECK-P8-NEXT: li r5, 64
279 ; CHECK-P8-NEXT: xxswapd vs2, vs7
280 ; CHECK-P8-NEXT: xxswapd vs3, vs6
281 ; CHECK-P8-NEXT: stxvd2x vs4, r3, r4
282 ; CHECK-P8-NEXT: li r4, 48
283 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
284 ; CHECK-P8-NEXT: li r5, 32
285 ; CHECK-P8-NEXT: stxvd2x vs5, r3, r4
286 ; CHECK-P8-NEXT: li r4, 16
287 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
288 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
289 ; CHECK-P8-NEXT: stxvd2x vs3, 0, r3
290 ; CHECK-P8-NEXT: blr
291 ;
292 ; CHECK-P9-LABEL: test16elt:
293 ; CHECK-P9: # %bb.0: # %entry
294 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha
295 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l
296 ; CHECK-P9-NEXT: lxvx v3, 0, r4
297 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
298 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha
299 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l
300 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
301 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3
302 ; CHECK-P9-NEXT: lxvx v3, 0, r4
303 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha
304 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l
305 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
306 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
307 ; CHECK-P9-NEXT: xvcvuxddp vs1, v3
308 ; CHECK-P9-NEXT: lxvx v3, 0, r4
309 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha
310 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l
311 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
312 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
313 ; CHECK-P9-NEXT: xvcvuxddp vs2, v3
314 ; CHECK-P9-NEXT: lxvx v3, 0, r4
315 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_4@toc@ha
316 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_4@toc@l
317 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
318 ; CHECK-P9-NEXT: stxv vs2, 32(r3)
319 ; CHECK-P9-NEXT: xvcvuxddp vs3, v3
320 ; CHECK-P9-NEXT: lxvx v3, 0, r4
321 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_5@toc@ha
322 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_5@toc@l
323 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
324 ; CHECK-P9-NEXT: stxv vs3, 48(r3)
325 ; CHECK-P9-NEXT: xvcvuxddp vs4, v3
326 ; CHECK-P9-NEXT: lxvx v3, 0, r4
327 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_6@toc@ha
328 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_6@toc@l
329 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
330 ; CHECK-P9-NEXT: stxv vs4, 64(r3)
331 ; CHECK-P9-NEXT: xvcvuxddp vs5, v3
332 ; CHECK-P9-NEXT: lxvx v3, 0, r4
333 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_7@toc@ha
334 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_7@toc@l
335 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
336 ; CHECK-P9-NEXT: stxv vs5, 80(r3)
337 ; CHECK-P9-NEXT: xvcvuxddp vs6, v3
338 ; CHECK-P9-NEXT: lxvx v3, 0, r4
339 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
340 ; CHECK-P9-NEXT: stxv vs6, 96(r3)
341 ; CHECK-P9-NEXT: xvcvuxddp vs7, v2
342 ; CHECK-P9-NEXT: stxv vs7, 112(r3)
343 ; CHECK-P9-NEXT: blr
344 ;
345 ; CHECK-BE-LABEL: test16elt:
346 ; CHECK-BE: # %bb.0: # %entry
347 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha
348 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l
349 ; CHECK-BE-NEXT: lxvx v3, 0, r4
350 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
351 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha
352 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l
353 ; CHECK-BE-NEXT: vperm v3, v2, v4, v3
354 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3
355 ; CHECK-BE-NEXT: lxvx v3, 0, r4
356 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha
357 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l
358 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
359 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
360 ; CHECK-BE-NEXT: xvcvuxddp vs1, v3
361 ; CHECK-BE-NEXT: lxvx v3, 0, r4
362 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha
363 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l
364 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
365 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
366 ; CHECK-BE-NEXT: xvcvuxddp vs2, v3
367 ; CHECK-BE-NEXT: lxvx v3, 0, r4
368 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_4@toc@ha
369 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_4@toc@l
370 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
371 ; CHECK-BE-NEXT: stxv vs2, 32(r3)
372 ; CHECK-BE-NEXT: xvcvuxddp vs3, v3
373 ; CHECK-BE-NEXT: lxvx v3, 0, r4
374 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_5@toc@ha
375 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_5@toc@l
376 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
377 ; CHECK-BE-NEXT: stxv vs3, 48(r3)
378 ; CHECK-BE-NEXT: xvcvuxddp vs4, v3
379 ; CHECK-BE-NEXT: lxvx v3, 0, r4
380 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_6@toc@ha
381 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_6@toc@l
382 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
383 ; CHECK-BE-NEXT: stxv vs4, 64(r3)
384 ; CHECK-BE-NEXT: xvcvuxddp vs5, v3
385 ; CHECK-BE-NEXT: lxvx v3, 0, r4
386 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_7@toc@ha
387 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_7@toc@l
388 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
389 ; CHECK-BE-NEXT: stxv vs5, 80(r3)
390 ; CHECK-BE-NEXT: xvcvuxddp vs6, v3
391 ; CHECK-BE-NEXT: lxvx v3, 0, r4
392 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
393 ; CHECK-BE-NEXT: stxv vs6, 96(r3)
394 ; CHECK-BE-NEXT: xvcvuxddp vs7, v2
395 ; CHECK-BE-NEXT: stxv vs7, 112(r3)
396 ; CHECK-BE-NEXT: blr
397 entry:
398 %0 = uitofp <16 x i8> %a to <16 x double>
399 store <16 x double> %0, <16 x double>* %agg.result, align 128
400 ret void
401 }
403 define <2 x double> @test2elt_signed(i16 %a.coerce) local_unnamed_addr #0 {
404 ; CHECK-P8-LABEL: test2elt_signed:
405 ; CHECK-P8: # %bb.0: # %entry
406 ; CHECK-P8-NEXT: addis r4, r2, .LCPI4_0@toc@ha
407 ; CHECK-P8-NEXT: mtvsrd f0, r3
408 ; CHECK-P8-NEXT: addi r3, r4, .LCPI4_0@toc@l
409 ; CHECK-P8-NEXT: xxswapd v2, vs0
410 ; CHECK-P8-NEXT: lvx v3, 0, r3
411 ; CHECK-P8-NEXT: addis r3, r2, .LCPI4_1@toc@ha
412 ; CHECK-P8-NEXT: addi r3, r3, .LCPI4_1@toc@l
413 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
414 ; CHECK-P8-NEXT: vperm v2, v2, v2, v3
415 ; CHECK-P8-NEXT: xxswapd v3, vs0
416 ; CHECK-P8-NEXT: vsld v2, v2, v3
417 ; CHECK-P8-NEXT: vsrad v2, v2, v3
418 ; CHECK-P8-NEXT: xvcvsxddp v2, v2
419 ; CHECK-P8-NEXT: blr
420 ;
421 ; CHECK-P9-LABEL: test2elt_signed:
422 ; CHECK-P9: # %bb.0: # %entry
423 ; CHECK-P9-NEXT: mtvsrws v2, r3
424 ; CHECK-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha
425 ; CHECK-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l
426 ; CHECK-P9-NEXT: lxvx v3, 0, r3
427 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
428 ; CHECK-P9-NEXT: vextsb2d v2, v2
429 ; CHECK-P9-NEXT: xvcvsxddp v2, v2
430 ; CHECK-P9-NEXT: blr
431 ;
432 ; CHECK-BE-LABEL: test2elt_signed:
433 ; CHECK-BE: # %bb.0: # %entry
434 ; CHECK-BE-NEXT: mtvsrws v2, r3
435 ; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha
436 ; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l
437 ; CHECK-BE-NEXT: lxvx v3, 0, r3
438 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
439 ; CHECK-BE-NEXT: vextsb2d v2, v2
440 ; CHECK-BE-NEXT: xvcvsxddp v2, v2
441 ; CHECK-BE-NEXT: blr
442 entry:
443 %0 = bitcast i16 %a.coerce to <2 x i8>
444 %1 = sitofp <2 x i8> %0 to <2 x double>
445 ret <2 x double> %1
446 }
448 define void @test4elt_signed(<4 x double>* noalias nocapture sret %agg.result, i32 %a.coerce) local_unnamed_addr #1 {
449 ; CHECK-P8-LABEL: test4elt_signed:
450 ; CHECK-P8: # %bb.0: # %entry
451 ; CHECK-P8-NEXT: addis r5, r2, .LCPI5_0@toc@ha
452 ; CHECK-P8-NEXT: mtvsrd f0, r4
453 ; CHECK-P8-NEXT: addis r4, r2, .LCPI5_2@toc@ha
454 ; CHECK-P8-NEXT: addi r5, r5, .LCPI5_0@toc@l
455 ; CHECK-P8-NEXT: addi r4, r4, .LCPI5_2@toc@l
456 ; CHECK-P8-NEXT: lvx v2, 0, r5
457 ; CHECK-P8-NEXT: xxswapd v3, vs0
458 ; CHECK-P8-NEXT: lvx v4, 0, r4
459 ; CHECK-P8-NEXT: addis r4, r2, .LCPI5_1@toc@ha
460 ; CHECK-P8-NEXT: addi r4, r4, .LCPI5_1@toc@l
461 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
462 ; CHECK-P8-NEXT: li r4, 16
463 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2
464 ; CHECK-P8-NEXT: vperm v3, v3, v3, v4
465 ; CHECK-P8-NEXT: xxswapd v4, vs0
466 ; CHECK-P8-NEXT: vsld v2, v2, v4
467 ; CHECK-P8-NEXT: vsld v3, v3, v4
468 ; CHECK-P8-NEXT: vsrad v2, v2, v4
469 ; CHECK-P8-NEXT: vsrad v3, v3, v4
470 ; CHECK-P8-NEXT: xvcvsxddp vs0, v2
471 ; CHECK-P8-NEXT: xvcvsxddp vs1, v3
472 ; CHECK-P8-NEXT: xxswapd vs0, vs0
473 ; CHECK-P8-NEXT: xxswapd vs1, vs1
474 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
475 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
476 ; CHECK-P8-NEXT: blr
477 ;
478 ; CHECK-P9-LABEL: test4elt_signed:
479 ; CHECK-P9: # %bb.0: # %entry
480 ; CHECK-P9-NEXT: mtvsrws v2, r4
481 ; CHECK-P9-NEXT: addis r4, r2, .LCPI5_0@toc@ha
482 ; CHECK-P9-NEXT: addi r4, r4, .LCPI5_0@toc@l
483 ; CHECK-P9-NEXT: lxvx v3, 0, r4
484 ; CHECK-P9-NEXT: addis r4, r2, .LCPI5_1@toc@ha
485 ; CHECK-P9-NEXT: addi r4, r4, .LCPI5_1@toc@l
486 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
487 ; CHECK-P9-NEXT: vextsb2d v3, v3
488 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3
489 ; CHECK-P9-NEXT: lxvx v3, 0, r4
490 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
491 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
492 ; CHECK-P9-NEXT: vextsb2d v2, v2
493 ; CHECK-P9-NEXT: xvcvsxddp vs1, v2
494 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
495 ; CHECK-P9-NEXT: blr
496 ;
497 ; CHECK-BE-LABEL: test4elt_signed:
498 ; CHECK-BE: # %bb.0: # %entry
499 ; CHECK-BE-NEXT: mtvsrws v2, r4
500 ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha
501 ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l
502 ; CHECK-BE-NEXT: lxvx v4, 0, r4
503 ; CHECK-BE-NEXT: xxlxor v3, v3, v3
504 ; CHECK-BE-NEXT: vperm v3, v3, v2, v4
505 ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_1@toc@ha
506 ; CHECK-BE-NEXT: vextsb2d v3, v3
507 ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_1@toc@l
508 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3
509 ; CHECK-BE-NEXT: lxvx v3, 0, r4
510 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
511 ; CHECK-BE-NEXT: stxv vs0, 16(r3)
512 ; CHECK-BE-NEXT: vextsb2d v2, v2
513 ; CHECK-BE-NEXT: xvcvsxddp vs1, v2
514 ; CHECK-BE-NEXT: stxv vs1, 0(r3)
515 ; CHECK-BE-NEXT: blr
516 entry:
517 %0 = bitcast i32 %a.coerce to <4 x i8>
518 %1 = sitofp <4 x i8> %0 to <4 x double>
519 store <4 x double> %1, <4 x double>* %agg.result, align 32
520 ret void
521 }
523 define void @test8elt_signed(<8 x double>* noalias nocapture sret %agg.result, i64 %a.coerce) local_unnamed_addr #1 {
524 ; CHECK-P8-LABEL: test8elt_signed:
525 ; CHECK-P8: # %bb.0: # %entry
526 ; CHECK-P8-NEXT: mtvsrd f0, r4
527 ; CHECK-P8-NEXT: addis r4, r2, .LCPI6_2@toc@ha
528 ; CHECK-P8-NEXT: addis r5, r2, .LCPI6_0@toc@ha
529 ; CHECK-P8-NEXT: addis r6, r2, .LCPI6_3@toc@ha
530 ; CHECK-P8-NEXT: addi r4, r4, .LCPI6_2@toc@l
531 ; CHECK-P8-NEXT: addi r5, r5, .LCPI6_0@toc@l
532 ; CHECK-P8-NEXT: addi r6, r6, .LCPI6_3@toc@l
533 ; CHECK-P8-NEXT: lvx v4, 0, r4
534 ; CHECK-P8-NEXT: addis r4, r2, .LCPI6_4@toc@ha
535 ; CHECK-P8-NEXT: lvx v2, 0, r5
536 ; CHECK-P8-NEXT: xxswapd v3, vs0
537 ; CHECK-P8-NEXT: lvx v5, 0, r6
538 ; CHECK-P8-NEXT: addis r5, r2, .LCPI6_1@toc@ha
539 ; CHECK-P8-NEXT: addi r4, r4, .LCPI6_4@toc@l
540 ; CHECK-P8-NEXT: addi r5, r5, .LCPI6_1@toc@l
541 ; CHECK-P8-NEXT: lvx v0, 0, r4
542 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r5
543 ; CHECK-P8-NEXT: li r4, 48
544 ; CHECK-P8-NEXT: li r5, 32
545 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2
546 ; CHECK-P8-NEXT: vperm v4, v3, v3, v4
547 ; CHECK-P8-NEXT: vperm v5, v3, v3, v5
548 ; CHECK-P8-NEXT: vperm v3, v3, v3, v0
549 ; CHECK-P8-NEXT: xxswapd v0, vs0
550 ; CHECK-P8-NEXT: vsld v2, v2, v0
551 ; CHECK-P8-NEXT: vsld v4, v4, v0
552 ; CHECK-P8-NEXT: vsld v5, v5, v0
553 ; CHECK-P8-NEXT: vsld v3, v3, v0
554 ; CHECK-P8-NEXT: vsrad v2, v2, v0
555 ; CHECK-P8-NEXT: vsrad v3, v3, v0
556 ; CHECK-P8-NEXT: vsrad v4, v4, v0
557 ; CHECK-P8-NEXT: vsrad v5, v5, v0
558 ; CHECK-P8-NEXT: xvcvsxddp vs2, v3
559 ; CHECK-P8-NEXT: xvcvsxddp vs0, v2
560 ; CHECK-P8-NEXT: xvcvsxddp vs1, v5
561 ; CHECK-P8-NEXT: xvcvsxddp vs3, v4
562 ; CHECK-P8-NEXT: xxswapd vs2, vs2
563 ; CHECK-P8-NEXT: xxswapd vs0, vs0
564 ; CHECK-P8-NEXT: xxswapd vs1, vs1
565 ; CHECK-P8-NEXT: xxswapd vs3, vs3
566 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
567 ; CHECK-P8-NEXT: li r4, 16
568 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
569 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
570 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
571 ; CHECK-P8-NEXT: blr
572 ;
573 ; CHECK-P9-LABEL: test8elt_signed:
574 ; CHECK-P9: # %bb.0: # %entry
575 ; CHECK-P9-NEXT: mtvsrd f0, r4
576 ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha
577 ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l
578 ; CHECK-P9-NEXT: lxvx v3, 0, r4
579 ; CHECK-P9-NEXT: xxswapd v2, vs0
580 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
581 ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_1@toc@ha
582 ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_1@toc@l
583 ; CHECK-P9-NEXT: vextsb2d v3, v3
584 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3
585 ; CHECK-P9-NEXT: lxvx v3, 0, r4
586 ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_2@toc@ha
587 ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_2@toc@l
588 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
589 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
590 ; CHECK-P9-NEXT: vextsb2d v3, v3
591 ; CHECK-P9-NEXT: xvcvsxddp vs1, v3
592 ; CHECK-P9-NEXT: lxvx v3, 0, r4
593 ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_3@toc@ha
594 ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_3@toc@l
595 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
596 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
597 ; CHECK-P9-NEXT: vextsb2d v3, v3
598 ; CHECK-P9-NEXT: xvcvsxddp vs2, v3
599 ; CHECK-P9-NEXT: lxvx v3, 0, r4
600 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
601 ; CHECK-P9-NEXT: stxv vs2, 32(r3)
602 ; CHECK-P9-NEXT: vextsb2d v2, v2
603 ; CHECK-P9-NEXT: xvcvsxddp vs3, v2
604 ; CHECK-P9-NEXT: stxv vs3, 48(r3)
605 ; CHECK-P9-NEXT: blr
606 ;
607 ; CHECK-BE-LABEL: test8elt_signed:
608 ; CHECK-BE: # %bb.0: # %entry
609 ; CHECK-BE-NEXT: mtvsrd v2, r4
610 ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha
611 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l
612 ; CHECK-BE-NEXT: lxvx v3, 0, r4
613 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
614 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
615 ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha
616 ; CHECK-BE-NEXT: vextsb2d v3, v3
617 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l
618 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3
619 ; CHECK-BE-NEXT: lxvx v3, 0, r4
620 ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_2@toc@ha
621 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_2@toc@l
622 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
623 ; CHECK-BE-NEXT: stxv vs0, 16(r3)
624 ; CHECK-BE-NEXT: vextsb2d v3, v3
625 ; CHECK-BE-NEXT: xvcvsxddp vs1, v3
626 ; CHECK-BE-NEXT: lxvx v3, 0, r4
627 ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_3@toc@ha
628 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_3@toc@l
629 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
630 ; CHECK-BE-NEXT: stxv vs1, 48(r3)
631 ; CHECK-BE-NEXT: vextsb2d v3, v3
632 ; CHECK-BE-NEXT: xvcvsxddp vs2, v3
633 ; CHECK-BE-NEXT: lxvx v3, 0, r4
634 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
635 ; CHECK-BE-NEXT: stxv vs2, 0(r3)
636 ; CHECK-BE-NEXT: vextsb2d v2, v2
637 ; CHECK-BE-NEXT: xvcvsxddp vs3, v2
638 ; CHECK-BE-NEXT: stxv vs3, 32(r3)
639 ; CHECK-BE-NEXT: blr
640 entry:
641 %0 = bitcast i64 %a.coerce to <8 x i8>
642 %1 = sitofp <8 x i8> %0 to <8 x double>
643 store <8 x double> %1, <8 x double>* %agg.result, align 64
644 ret void
645 }
647 define void @test16elt_signed(<16 x double>* noalias nocapture sret %agg.result, <16 x i8> %a) local_unnamed_addr #2 {
648 ; CHECK-P8-LABEL: test16elt_signed:
649 ; CHECK-P8: # %bb.0: # %entry
650 ; CHECK-P8-NEXT: addis r4, r2, .LCPI7_0@toc@ha
651 ; CHECK-P8-NEXT: addis r5, r2, .LCPI7_2@toc@ha
652 ; CHECK-P8-NEXT: addis r6, r2, .LCPI7_3@toc@ha
653 ; CHECK-P8-NEXT: addi r4, r4, .LCPI7_0@toc@l
654 ; CHECK-P8-NEXT: addi r5, r5, .LCPI7_2@toc@l
655 ; CHECK-P8-NEXT: addi r6, r6, .LCPI7_3@toc@l
656 ; CHECK-P8-NEXT: lvx v3, 0, r4
657 ; CHECK-P8-NEXT: addis r4, r2, .LCPI7_4@toc@ha
658 ; CHECK-P8-NEXT: lvx v4, 0, r5
659 ; CHECK-P8-NEXT: addis r5, r2, .LCPI7_5@toc@ha
660 ; CHECK-P8-NEXT: lvx v5, 0, r6
661 ; CHECK-P8-NEXT: addis r6, r2, .LCPI7_1@toc@ha
662 ; CHECK-P8-NEXT: addi r4, r4, .LCPI7_4@toc@l
663 ; CHECK-P8-NEXT: addi r5, r5, .LCPI7_5@toc@l
664 ; CHECK-P8-NEXT: addi r6, r6, .LCPI7_1@toc@l
665 ; CHECK-P8-NEXT: lvx v0, 0, r4
666 ; CHECK-P8-NEXT: addis r4, r2, .LCPI7_6@toc@ha
667 ; CHECK-P8-NEXT: lvx v1, 0, r5
668 ; CHECK-P8-NEXT: addis r5, r2, .LCPI7_7@toc@ha
669 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r6
670 ; CHECK-P8-NEXT: addi r4, r4, .LCPI7_6@toc@l
671 ; CHECK-P8-NEXT: addi r5, r5, .LCPI7_7@toc@l
672 ; CHECK-P8-NEXT: vperm v3, v2, v2, v3
673 ; CHECK-P8-NEXT: lvx v6, 0, r4
674 ; CHECK-P8-NEXT: addis r4, r2, .LCPI7_8@toc@ha
675 ; CHECK-P8-NEXT: lvx v7, 0, r5
676 ; CHECK-P8-NEXT: vperm v4, v2, v2, v4
677 ; CHECK-P8-NEXT: li r5, 96
678 ; CHECK-P8-NEXT: addi r4, r4, .LCPI7_8@toc@l
679 ; CHECK-P8-NEXT: vperm v5, v2, v2, v5
680 ; CHECK-P8-NEXT: xxswapd v9, vs0
681 ; CHECK-P8-NEXT: lvx v8, 0, r4
682 ; CHECK-P8-NEXT: vperm v0, v2, v2, v0
683 ; CHECK-P8-NEXT: li r4, 112
684 ; CHECK-P8-NEXT: vperm v1, v2, v2, v1
685 ; CHECK-P8-NEXT: vperm v6, v2, v2, v6
686 ; CHECK-P8-NEXT: vperm v7, v2, v2, v7
687 ; CHECK-P8-NEXT: vperm v2, v2, v2, v8
688 ; CHECK-P8-NEXT: vsld v3, v3, v9
689 ; CHECK-P8-NEXT: vsld v0, v0, v9
690 ; CHECK-P8-NEXT: vsld v1, v1, v9
691 ; CHECK-P8-NEXT: vsld v6, v6, v9
692 ; CHECK-P8-NEXT: vsld v7, v7, v9
693 ; CHECK-P8-NEXT: vsld v2, v2, v9
694 ; CHECK-P8-NEXT: vsrad v7, v7, v9
695 ; CHECK-P8-NEXT: vsrad v2, v2, v9
696 ; CHECK-P8-NEXT: vsld v4, v4, v9
697 ; CHECK-P8-NEXT: vsld v5, v5, v9
698 ; CHECK-P8-NEXT: vsrad v6, v6, v9
699 ; CHECK-P8-NEXT: vsrad v0, v0, v9
700 ; CHECK-P8-NEXT: vsrad v1, v1, v9
701 ; CHECK-P8-NEXT: xvcvsxddp vs2, v7
702 ; CHECK-P8-NEXT: xvcvsxddp vs3, v2
703 ; CHECK-P8-NEXT: vsrad v3, v3, v9
704 ; CHECK-P8-NEXT: vsrad v4, v4, v9
705 ; CHECK-P8-NEXT: vsrad v5, v5, v9
706 ; CHECK-P8-NEXT: xvcvsxddp vs4, v6
707 ; CHECK-P8-NEXT: xvcvsxddp vs1, v1
708 ; CHECK-P8-NEXT: xxswapd vs2, vs2
709 ; CHECK-P8-NEXT: xvcvsxddp vs5, v0
710 ; CHECK-P8-NEXT: xxswapd vs3, vs3
711 ; CHECK-P8-NEXT: xvcvsxddp vs0, v5
712 ; CHECK-P8-NEXT: xvcvsxddp vs6, v3
713 ; CHECK-P8-NEXT: xvcvsxddp vs7, v4
714 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
715 ; CHECK-P8-NEXT: li r4, 80
716 ; CHECK-P8-NEXT: xxswapd vs4, vs4
717 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r5
718 ; CHECK-P8-NEXT: li r5, 64
719 ; CHECK-P8-NEXT: xxswapd vs1, vs1
720 ; CHECK-P8-NEXT: xxswapd vs5, vs5
721 ; CHECK-P8-NEXT: xxswapd vs0, vs0
722 ; CHECK-P8-NEXT: stxvd2x vs4, r3, r4
723 ; CHECK-P8-NEXT: li r4, 48
724 ; CHECK-P8-NEXT: xxswapd vs3, vs6
725 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
726 ; CHECK-P8-NEXT: li r5, 32
727 ; CHECK-P8-NEXT: xxswapd vs2, vs7
728 ; CHECK-P8-NEXT: stxvd2x vs5, r3, r4
729 ; CHECK-P8-NEXT: li r4, 16
730 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r5
731 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
732 ; CHECK-P8-NEXT: stxvd2x vs3, 0, r3
733 ; CHECK-P8-NEXT: blr
734 ;
735 ; CHECK-P9-LABEL: test16elt_signed:
736 ; CHECK-P9: # %bb.0: # %entry
737 ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_0@toc@ha
738 ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_0@toc@l
739 ; CHECK-P9-NEXT: lxvx v3, 0, r4
740 ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_1@toc@ha
741 ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_1@toc@l
742 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
743 ; CHECK-P9-NEXT: vextsb2d v3, v3
744 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3
745 ; CHECK-P9-NEXT: lxvx v3, 0, r4
746 ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_2@toc@ha
747 ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_2@toc@l
748 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
749 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
750 ; CHECK-P9-NEXT: vextsb2d v3, v3
751 ; CHECK-P9-NEXT: xvcvsxddp vs1, v3
752 ; CHECK-P9-NEXT: lxvx v3, 0, r4
753 ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_3@toc@ha
754 ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_3@toc@l
755 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
756 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
757 ; CHECK-P9-NEXT: vextsb2d v3, v3
758 ; CHECK-P9-NEXT: xvcvsxddp vs2, v3
759 ; CHECK-P9-NEXT: lxvx v3, 0, r4
760 ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_4@toc@ha
761 ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_4@toc@l
762 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
763 ; CHECK-P9-NEXT: stxv vs2, 32(r3)
764 ; CHECK-P9-NEXT: vextsb2d v3, v3
765 ; CHECK-P9-NEXT: xvcvsxddp vs3, v3
766 ; CHECK-P9-NEXT: lxvx v3, 0, r4
767 ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_5@toc@ha
768 ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_5@toc@l
769 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
770 ; CHECK-P9-NEXT: stxv vs3, 48(r3)
771 ; CHECK-P9-NEXT: vextsb2d v3, v3
772 ; CHECK-P9-NEXT: xvcvsxddp vs4, v3
773 ; CHECK-P9-NEXT: lxvx v3, 0, r4
774 ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_6@toc@ha
775 ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_6@toc@l
776 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
777 ; CHECK-P9-NEXT: stxv vs4, 64(r3)
778 ; CHECK-P9-NEXT: vextsb2d v3, v3
779 ; CHECK-P9-NEXT: xvcvsxddp vs5, v3
780 ; CHECK-P9-NEXT: lxvx v3, 0, r4
781 ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_7@toc@ha
782 ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_7@toc@l
783 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
784 ; CHECK-P9-NEXT: stxv vs5, 80(r3)
785 ; CHECK-P9-NEXT: vextsb2d v3, v3
786 ; CHECK-P9-NEXT: xvcvsxddp vs6, v3
787 ; CHECK-P9-NEXT: lxvx v3, 0, r4
788 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
789 ; CHECK-P9-NEXT: stxv vs6, 96(r3)
790 ; CHECK-P9-NEXT: vextsb2d v2, v2
791 ; CHECK-P9-NEXT: xvcvsxddp vs7, v2
792 ; CHECK-P9-NEXT: stxv vs7, 112(r3)
793 ; CHECK-P9-NEXT: blr
794 ;
795 ; CHECK-BE-LABEL: test16elt_signed:
796 ; CHECK-BE: # %bb.0: # %entry
797 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha
798 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l
799 ; CHECK-BE-NEXT: lxvx v4, 0, r4
800 ; CHECK-BE-NEXT: xxlxor v3, v3, v3
801 ; CHECK-BE-NEXT: vperm v4, v3, v2, v4
802 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_1@toc@ha
803 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_1@toc@l
804 ; CHECK-BE-NEXT: vextsb2d v4, v4
805 ; CHECK-BE-NEXT: xvcvsxddp vs0, v4
806 ; CHECK-BE-NEXT: lxvx v4, 0, r4
807 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha
808 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l
809 ; CHECK-BE-NEXT: vperm v4, v3, v2, v4
810 ; CHECK-BE-NEXT: stxv vs0, 16(r3)
811 ; CHECK-BE-NEXT: vextsb2d v4, v4
812 ; CHECK-BE-NEXT: xvcvsxddp vs1, v4
813 ; CHECK-BE-NEXT: lxvx v4, 0, r4
814 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha
815 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l
816 ; CHECK-BE-NEXT: vperm v4, v3, v2, v4
817 ; CHECK-BE-NEXT: stxv vs1, 48(r3)
818 ; CHECK-BE-NEXT: vextsb2d v4, v4
819 ; CHECK-BE-NEXT: xvcvsxddp vs2, v4
820 ; CHECK-BE-NEXT: lxvx v4, 0, r4
821 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_4@toc@ha
822 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_4@toc@l
823 ; CHECK-BE-NEXT: vperm v3, v3, v2, v4
824 ; CHECK-BE-NEXT: stxv vs2, 80(r3)
825 ; CHECK-BE-NEXT: vextsb2d v3, v3
826 ; CHECK-BE-NEXT: xvcvsxddp vs3, v3
827 ; CHECK-BE-NEXT: lxvx v3, 0, r4
828 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_5@toc@ha
829 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_5@toc@l
830 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
831 ; CHECK-BE-NEXT: stxv vs3, 112(r3)
832 ; CHECK-BE-NEXT: vextsb2d v3, v3
833 ; CHECK-BE-NEXT: xvcvsxddp vs4, v3
834 ; CHECK-BE-NEXT: lxvx v3, 0, r4
835 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_6@toc@ha
836 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_6@toc@l
837 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
838 ; CHECK-BE-NEXT: stxv vs4, 0(r3)
839 ; CHECK-BE-NEXT: vextsb2d v3, v3
840 ; CHECK-BE-NEXT: xvcvsxddp vs5, v3
841 ; CHECK-BE-NEXT: lxvx v3, 0, r4
842 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_7@toc@ha
843 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_7@toc@l
844 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
845 ; CHECK-BE-NEXT: stxv vs5, 32(r3)
846 ; CHECK-BE-NEXT: vextsb2d v3, v3
847 ; CHECK-BE-NEXT: xvcvsxddp vs6, v3
848 ; CHECK-BE-NEXT: lxvx v3, 0, r4
849 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
850 ; CHECK-BE-NEXT: stxv vs6, 64(r3)
851 ; CHECK-BE-NEXT: vextsb2d v2, v2
852 ; CHECK-BE-NEXT: xvcvsxddp vs7, v2
853 ; CHECK-BE-NEXT: stxv vs7, 96(r3)
854 ; CHECK-BE-NEXT: blr
855 entry:
856 %0 = sitofp <16 x i8> %a to <16 x double>
857 store <16 x double> %0, <16 x double>* %agg.result, align 128
858 ret void
859 }