| blob | dfb86c028eb1dbedcc3d5ecd0664e3c58b864d05 |
1 # RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -run-pass=regallocbasic %s -o - | FileCheck %s
2 # This test used to assert in RABasic. The problem was when we split live-ranges,
3 # we were not updating the LiveRegMatrix properly and the interference calculation
4 # wouldn't match what the assignment thought it could do.
5 # In other words, this test case needs to trigger live-range splitting to exercise
6 # the problem.
7 #
8 # PR33057
9 --- |
10 target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64"
11 target triple = "s390x--linux-gnu"
13 define void @autogen_SD21418() #0 {
14 ret void
15 }
17 attributes #0 = { "target-cpu"="z13" }
19 ...
21 # CHECK: name: autogen_SD21418
22 # Check that at least one live-range has been split
23 # CHECK: id: 114, class
24 ---
25 name: autogen_SD21418
26 alignment: 2
27 tracksRegLiveness: true
28 registers:
29 - { id: 0, class: vr128bit }
30 - { id: 1, class: vr128bit }
31 - { id: 2, class: vr128bit }
32 - { id: 3, class: vr64bit }
33 - { id: 4, class: gr64bit }
34 - { id: 5, class: vr128bit }
35 - { id: 6, class: grx32bit }
36 - { id: 7, class: vr128bit }
37 - { id: 8, class: vr128bit }
38 - { id: 9, class: gr32bit }
39 - { id: 10, class: gr64bit }
40 - { id: 11, class: vr128bit }
41 - { id: 12, class: fp64bit }
42 - { id: 13, class: vr64bit }
43 - { id: 14, class: vr64bit }
44 - { id: 15, class: gr64bit }
45 - { id: 16, class: gr128bit }
46 - { id: 17, class: gr64bit }
47 - { id: 18, class: gr32bit }
48 - { id: 19, class: gr32bit }
49 - { id: 20, class: gr128bit }
50 - { id: 21, class: gr32bit }
51 - { id: 22, class: gr64bit }
52 - { id: 23, class: gr32bit }
53 - { id: 24, class: gr32bit }
54 - { id: 25, class: gr128bit }
55 - { id: 26, class: grx32bit }
56 - { id: 27, class: gr64bit }
57 - { id: 28, class: gr64bit }
58 - { id: 29, class: vr128bit }
59 - { id: 30, class: vr128bit }
60 - { id: 31, class: gr64bit }
61 - { id: 32, class: gr32bit }
62 - { id: 33, class: gr32bit }
63 - { id: 34, class: gr128bit }
64 - { id: 35, class: gr32bit }
65 - { id: 36, class: vr128bit }
66 - { id: 37, class: gr64bit }
67 - { id: 38, class: gr32bit }
68 - { id: 39, class: gr32bit }
69 - { id: 40, class: gr128bit }
70 - { id: 41, class: gr32bit }
71 - { id: 42, class: addr64bit }
72 - { id: 43, class: grx32bit }
73 - { id: 44, class: addr64bit }
74 - { id: 45, class: vr64bit }
75 - { id: 46, class: vr64bit }
76 - { id: 47, class: gr32bit }
77 - { id: 48, class: gr32bit }
78 - { id: 49, class: grx32bit }
79 - { id: 50, class: vr64bit }
80 - { id: 51, class: gr64bit }
81 - { id: 52, class: grx32bit }
82 - { id: 53, class: gr32bit }
83 - { id: 54, class: gr64bit }
84 - { id: 55, class: grx32bit }
85 - { id: 56, class: gr32bit }
86 - { id: 57, class: gr128bit }
87 - { id: 58, class: gr128bit }
88 - { id: 59, class: gr32bit }
89 - { id: 60, class: gr64bit }
90 - { id: 61, class: grx32bit }
91 - { id: 62, class: gr32bit }
92 - { id: 63, class: gr64bit }
93 - { id: 64, class: grx32bit }
94 - { id: 65, class: gr32bit }
95 - { id: 66, class: gr128bit }
96 - { id: 67, class: gr128bit }
97 - { id: 68, class: grx32bit }
98 - { id: 69, class: gr64bit }
99 - { id: 70, class: gr64bit }
100 - { id: 71, class: vr128bit }
101 - { id: 72, class: vr128bit }
102 - { id: 73, class: gr64bit }
103 - { id: 74, class: grx32bit }
104 - { id: 75, class: gr32bit }
105 - { id: 76, class: gr64bit }
106 - { id: 77, class: grx32bit }
107 - { id: 78, class: gr32bit }
108 - { id: 79, class: gr128bit }
109 - { id: 80, class: gr128bit }
110 - { id: 81, class: gr32bit }
111 - { id: 82, class: vr128bit }
112 - { id: 83, class: gr64bit }
113 - { id: 84, class: grx32bit }
114 - { id: 85, class: gr32bit }
115 - { id: 86, class: gr64bit }
116 - { id: 87, class: grx32bit }
117 - { id: 88, class: gr32bit }
118 - { id: 89, class: gr128bit }
119 - { id: 90, class: gr128bit }
120 - { id: 91, class: gr32bit }
121 - { id: 92, class: grx32bit }
122 - { id: 93, class: gr64bit }
123 - { id: 94, class: gr32bit }
124 - { id: 95, class: gr32bit }
125 - { id: 96, class: gr32bit }
126 - { id: 97, class: gr64bit }
127 - { id: 98, class: gr64bit }
128 - { id: 99, class: grx32bit }
129 - { id: 100, class: grx32bit }
130 - { id: 101, class: gr128bit }
131 - { id: 102, class: gr128bit }
132 - { id: 103, class: gr128bit }
133 - { id: 104, class: gr64bit }
134 - { id: 105, class: gr128bit }
135 - { id: 106, class: gr128bit }
136 - { id: 107, class: gr64bit }
137 - { id: 108, class: gr128bit }
138 - { id: 109, class: gr128bit }
139 - { id: 110, class: gr64bit }
140 - { id: 111, class: gr128bit }
141 - { id: 112, class: gr128bit }
142 - { id: 113, class: gr64bit }
143 constants:
144 - id: 0
145 value: double 0xD55960F86F577076
146 alignment: 8
147 body: |
148 bb.0:
149 %11 = VGBM 0
150 %43 = LHIMux 0
151 %44 = LARL %const.0
152 %45 = VL64 %44, 0, $noreg :: (load 8 from constant-pool)
154 bb.1:
155 ADJCALLSTACKDOWN 0, 0
156 %12 = LZDR
157 $f0d = COPY %12
158 CallBRASL &fmod, killed $f0d, undef $f2d, csr_systemz, implicit-def dead $r14d, implicit-def dead $cc, implicit-def $f0d
159 ADJCALLSTACKUP 0, 0
160 KILL killed $f0d
162 bb.2:
163 %17 = VLGVH %11, $noreg, 0
164 %19 = LHR %17.subreg_l32
165 undef %20.subreg_l64 = LGHI 0
166 %20 = DSGFR %20, %19
167 %22 = VLGVH %11, $noreg, 3
168 %24 = LHR %22.subreg_l32
169 undef %25.subreg_l64 = LGHI 0
170 %25 = DSGFR %25, %24
171 %31 = VLGVH %11, $noreg, 1
172 %33 = LHR %31.subreg_l32
173 undef %34.subreg_l64 = LGHI 0
174 %34 = DSGFR %34, %33
175 %37 = VLGVH %11, $noreg, 2
176 %39 = LHR %37.subreg_l32
177 undef %40.subreg_l64 = LGHI 0
178 %40 = DSGFR %40, %39
179 CHIMux %43, 0, implicit-def $cc
180 BRC 14, 6, %bb.2, implicit killed $cc
181 J %bb.3
183 bb.3:
184 WFCDB undef %46, %45, implicit-def $cc, implicit $fpc
185 %48 = IPM implicit killed $cc
186 %48 = AFIMux %48, 268435456, implicit-def dead $cc
187 %6 = RISBMux undef %6, %48, 31, 159, 35
188 WFCDB undef %50, %45, implicit-def $cc, implicit $fpc
189 BRC 15, 6, %bb.1, implicit killed $cc
190 J %bb.4
192 bb.4:
193 %36 = VLVGP %25.subreg_l64, %25.subreg_l64
194 %36 = VLVGH %36, %20.subreg_l32, $noreg, 0
195 %36 = VLVGH %36, %34.subreg_l32, $noreg, 1
196 dead %36 = VLVGH %36, %40.subreg_l32, $noreg, 2
197 %4 = LG undef %42, 0, $noreg :: (load 8 from `i64* undef`)
198 undef %57.subreg_h64 = LLILL 0
199 undef %66.subreg_h64 = LLILL 0
200 undef %79.subreg_h64 = LLILL 0
201 undef %89.subreg_h64 = LLILL 0
202 %92 = LHIMux 0
204 bb.5:
206 bb.6:
207 %51 = VLGVH undef %7, $noreg, 0
208 %53 = LLHRMux %51.subreg_l32
209 %54 = VLGVH undef %1, $noreg, 0
210 %57.subreg_l32 = LLHRMux %54.subreg_l32
211 %58 = COPY %57
212 %58 = DLR %58, %53
213 %60 = VLGVH undef %7, $noreg, 3
214 %62 = LLHRMux %60.subreg_l32
215 %63 = VLGVH undef %1, $noreg, 3
216 %66.subreg_l32 = LLHRMux %63.subreg_l32
217 %67 = COPY %66
218 %67 = DLR %67, %62
219 %73 = VLGVH undef %7, $noreg, 1
220 %75 = LLHRMux %73.subreg_l32
221 %76 = VLGVH undef %1, $noreg, 1
222 %79.subreg_l32 = LLHRMux %76.subreg_l32
223 %80 = COPY %79
224 %80 = DLR %80, %75
225 %83 = VLGVH undef %7, $noreg, 2
226 %85 = LLHRMux %83.subreg_l32
227 %86 = VLGVH undef %1, $noreg, 2
228 %89.subreg_l32 = LLHRMux %86.subreg_l32
229 %90 = COPY %89
230 %90 = DLR %90, %85
231 CHIMux %92, 0, implicit-def $cc
232 BRC 14, 6, %bb.7, implicit killed $cc
233 J %bb.6
235 bb.7:
236 CGHI undef %93, 0, implicit-def $cc
237 %96 = IPM implicit killed $cc
238 CGHI undef %97, 0, implicit-def $cc
239 BRC 14, 6, %bb.6, implicit killed $cc
241 bb.8:
242 CHIMux %6, 0, implicit-def $cc
243 %10 = LLILL 41639
244 dead %10 = LOCGR %10, %4, 14, 6, implicit killed $cc
245 CHIMux %92, 0, implicit-def $cc
246 BRC 14, 6, %bb.5, implicit killed $cc
247 J %bb.9
249 bb.9:
250 %82 = VLVGP %67.subreg_h64, %67.subreg_h64
251 %82 = VLVGH %82, %58.subreg_hl32, $noreg, 0
252 %82 = VLVGH %82, %80.subreg_hl32, $noreg, 1
253 dead %82 = VLVGH %82, %90.subreg_hl32, $noreg, 2
254 %96 = AFIMux %96, 1879048192, implicit-def dead $cc
255 %96 = SRL %96, $noreg, 31
256 dead %11 = VLVGF %11, %96, $noreg, 1
257 %100 = LHIMux 0
259 bb.10:
260 CHIMux %100, 0, implicit-def $cc
261 BRC 14, 6, %bb.10, implicit killed $cc
262 J %bb.11
264 bb.11:
265 Return
267 ...