1 # RUN: llc -mtriple thumbv8m.base-none-eabi -run-pass=peephole-opt -verify-machineinstrs -o - %s | FileCheck %s
3 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4 target triple = "thumbv8m.base-none-none-eabi"
6 define i32 @test_adc(i32 %a, i32 %b) { ret i32 %a }
7 define i32 @test_adc_mov(i32 %a, i32 %b) { ret i32 %a }
8 define i32 @test_sbc(i32 %a, i32 %b) { ret i32 %a }
9 define i32 @test_rsb(i32 %a) { ret i32 %a }
10 define i32 @test_and(i32 %a, i32 %b) { ret i32 %a }
11 define i32 @test_orr(i32 %a, i32 %b) { ret i32 %a }
12 define i32 @test_eor(i32 %a, i32 %b) { ret i32 %a }
13 define i32 @test_bic(i32 %a, i32 %b) { ret i32 %a }
14 define i32 @test_mvn(i32 %a) { ret i32 %a }
15 define i32 @test_asrrr(i32 %a, i32 %b) { ret i32 %a }
16 define i32 @test_asrri(i32 %a) { ret i32 %a }
17 define i32 @test_ror(i32 %a, i32 %b) { ret i32 %a }
23 - { reg: '$r0', virtual-reg: '%0' }
24 - { reg: '$r1', virtual-reg: '%1' }
26 ; CHECK-LABEL: name: test_adc
27 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
28 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
29 ; CHECK: [[tADDrr:%[0-9]+]]:tgpr, $cpsr = tADDrr [[COPY1]], [[COPY]], 14, $noreg
30 ; CHECK: [[tADC:%[0-9]+]]:tgpr, $cpsr = tADC [[COPY1]], [[COPY]], 14, $noreg, implicit $cpsr
31 ; CHECK: tBcc %bb.2, 1, $cpsr
32 ; CHECK: tB %bb.1, 14, $noreg
34 successors: %bb.2(0x40000000), %bb.1(0x40000000)
39 %3:tgpr, $cpsr = tADDrr %0, %1, 14, $noreg
40 %2:tgpr, dead $cpsr = tADC %0, %1, 14, $noreg, implicit $cpsr
41 tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
47 tBX_RET 14, $noreg, implicit $r0
50 %4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
52 tBX_RET 14, $noreg, implicit $r0
57 - { reg: '$r0', virtual-reg: '%0' }
58 - { reg: '$r1', virtual-reg: '%1' }
60 ; CHECK-LABEL: name: test_adc_mov
61 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
62 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
63 ; CHECK: [[tADDrr:%[0-9]+]]:tgpr, $cpsr = tADDrr [[COPY1]], [[COPY]], 14, $noreg
64 ; CHECK: [[tADC:%[0-9]+]]:tgpr, dead $cpsr = tADC [[COPY1]], [[COPY]], 14, $noreg, implicit $cpsr
65 ; CHECK: [[tMOVi8_:%[0-9]+]]:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
66 ; CHECK: tCMPi8 [[tADC]], 0, 14, $noreg, implicit-def $cpsr
67 ; CHECK: tBcc %bb.2, 1, $cpsr
68 ; CHECK: tB %bb.1, 14, $noreg
70 successors: %bb.2(0x40000000), %bb.1(0x40000000)
75 %3:tgpr, $cpsr = tADDrr %0, %1, 14, $noreg
76 %2:tgpr, dead $cpsr = tADC %0, %1, 14, $noreg, implicit $cpsr
77 %5:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
78 tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
84 tBX_RET 14, $noreg, implicit $r0
87 %4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
89 tBX_RET 14, $noreg, implicit $r0
94 - { reg: '$r0', virtual-reg: '%0' }
95 - { reg: '$r1', virtual-reg: '%1' }
97 ; CHECK-LABEL: name: test_sbc
98 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
99 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
100 ; CHECK: [[tADDrr:%[0-9]+]]:tgpr, $cpsr = tADDrr [[COPY1]], [[COPY]], 14, $noreg
101 ; CHECK: [[tSBC:%[0-9]+]]:tgpr, $cpsr = tSBC [[COPY1]], [[COPY]], 14, $noreg, implicit $cpsr
102 ; CHECK: tBcc %bb.2, 1, $cpsr
103 ; CHECK: tB %bb.1, 14, $noreg
105 successors: %bb.2(0x40000000), %bb.1(0x40000000)
110 %3:tgpr, $cpsr = tADDrr %0, %1, 14, $noreg
111 %2:tgpr, dead $cpsr = tSBC %0, %1, 14, $noreg, implicit $cpsr
112 tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
118 tBX_RET 14, $noreg, implicit $r0
121 %4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
123 tBX_RET 14, $noreg, implicit $r0
128 - { reg: '$r0', virtual-reg: '%0' }
130 ; CHECK-LABEL: name: test_rsb
131 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
132 ; CHECK: [[tRSB:%[0-9]+]]:tgpr, $cpsr = tRSB [[COPY]], 14, $noreg
133 ; CHECK: tBcc %bb.2, 1, $cpsr
134 ; CHECK: tB %bb.1, 14, $noreg
136 successors: %bb.2(0x40000000), %bb.1(0x40000000)
140 %1:tgpr, dead $cpsr = tRSB %0, 14, $noreg
141 tCMPi8 %1, 0, 14, $noreg, implicit-def $cpsr
147 tBX_RET 14, $noreg, implicit $r0
150 %4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
152 tBX_RET 14, $noreg, implicit $r0
157 - { reg: '$r0', virtual-reg: '%0' }
158 - { reg: '$r1', virtual-reg: '%1' }
160 ; CHECK-LABEL: name: test_and
161 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
162 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
163 ; CHECK: [[tAND:%[0-9]+]]:tgpr, $cpsr = tAND [[COPY1]], [[COPY]], 14, $noreg
164 ; CHECK: tBcc %bb.2, 1, $cpsr
165 ; CHECK: tB %bb.1, 14, $noreg
167 successors: %bb.2(0x40000000), %bb.1(0x40000000)
172 %2:tgpr, dead $cpsr = tAND %0, %1, 14, $noreg
173 tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
179 tBX_RET 14, $noreg, implicit $r0
182 %4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
184 tBX_RET 14, $noreg, implicit $r0
189 - { reg: '$r0', virtual-reg: '%0' }
190 - { reg: '$r1', virtual-reg: '%1' }
192 ; CHECK-LABEL: name: test_orr
193 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
194 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
195 ; CHECK: [[tORR:%[0-9]+]]:tgpr, $cpsr = tORR [[COPY1]], [[COPY]], 14, $noreg
196 ; CHECK: tBcc %bb.2, 1, $cpsr
197 ; CHECK: tB %bb.1, 14, $noreg
199 successors: %bb.2(0x40000000), %bb.1(0x40000000)
204 %2:tgpr, dead $cpsr = tORR %0, %1, 14, $noreg
205 tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
211 tBX_RET 14, $noreg, implicit $r0
214 %4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
216 tBX_RET 14, $noreg, implicit $r0
221 - { reg: '$r0', virtual-reg: '%0' }
222 - { reg: '$r1', virtual-reg: '%1' }
224 ; CHECK-LABEL: name: test_eor
225 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
226 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
227 ; CHECK: [[tEOR:%[0-9]+]]:tgpr, $cpsr = tEOR [[COPY1]], [[COPY]], 14, $noreg
228 ; CHECK: tBcc %bb.2, 1, $cpsr
229 ; CHECK: tB %bb.1, 14, $noreg
231 successors: %bb.2(0x40000000), %bb.1(0x40000000)
236 %2:tgpr, dead $cpsr = tEOR %0, %1, 14, $noreg
237 tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
243 tBX_RET 14, $noreg, implicit $r0
246 %4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
248 tBX_RET 14, $noreg, implicit $r0
253 - { reg: '$r0', virtual-reg: '%0' }
254 - { reg: '$r1', virtual-reg: '%1' }
256 ; CHECK-LABEL: name: test_bic
257 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
258 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
259 ; CHECK: [[tBIC:%[0-9]+]]:tgpr, $cpsr = tBIC [[COPY1]], [[COPY]], 14, $noreg
260 ; CHECK: tBcc %bb.2, 1, $cpsr
261 ; CHECK: tB %bb.1, 14, $noreg
263 successors: %bb.2(0x40000000), %bb.1(0x40000000)
268 %2:tgpr, dead $cpsr = tBIC %0, %1, 14, $noreg
269 tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
275 tBX_RET 14, $noreg, implicit $r0
278 %4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
280 tBX_RET 14, $noreg, implicit $r0
285 - { reg: '$r0', virtual-reg: '%0' }
287 ; CHECK-LABEL: name: test_mvn
288 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
289 ; CHECK: [[tMVN:%[0-9]+]]:tgpr, $cpsr = tMVN [[COPY]], 14, $noreg
290 ; CHECK: tBcc %bb.2, 1, $cpsr
291 ; CHECK: tB %bb.1, 14, $noreg
293 successors: %bb.2(0x40000000), %bb.1(0x40000000)
297 %1:tgpr, dead $cpsr = tMVN %0, 14, $noreg
298 tCMPi8 %1, 0, 14, $noreg, implicit-def $cpsr
304 tBX_RET 14, $noreg, implicit $r0
307 %4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
309 tBX_RET 14, $noreg, implicit $r0
314 - { reg: '$r0', virtual-reg: '%0' }
315 - { reg: '$r1', virtual-reg: '%1' }
317 ; CHECK-LABEL: name: test_asrrr
318 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
319 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
320 ; CHECK: [[tASRrr:%[0-9]+]]:tgpr, $cpsr = tASRrr [[COPY1]], [[COPY]], 14, $noreg
321 ; CHECK: tBcc %bb.2, 1, $cpsr
322 ; CHECK: tB %bb.1, 14, $noreg
324 successors: %bb.2(0x40000000), %bb.1(0x40000000)
329 %2:tgpr, dead $cpsr = tASRrr %0, %1, 14, $noreg
330 tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
336 tBX_RET 14, $noreg, implicit $r0
339 %4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
341 tBX_RET 14, $noreg, implicit $r0
346 - { reg: '$r0', virtual-reg: '%0' }
348 ; CHECK-LABEL: name: test_asrri
349 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
350 ; CHECK: [[tASRri:%[0-9]+]]:tgpr, $cpsr = tASRri [[COPY]], 1, 14, $noreg
351 ; CHECK: tBcc %bb.2, 1, $cpsr
352 ; CHECK: tB %bb.1, 14, $noreg
354 successors: %bb.2(0x40000000), %bb.1(0x40000000)
358 %2:tgpr, dead $cpsr = tASRri %0, 1, 14, $noreg
359 tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
365 tBX_RET 14, $noreg, implicit $r0
368 %4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
370 tBX_RET 14, $noreg, implicit $r0
375 - { reg: '$r0', virtual-reg: '%0' }
376 - { reg: '$r1', virtual-reg: '%1' }
378 ; CHECK-LABEL: name: test_ror
379 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1
380 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
381 ; CHECK: [[tROR:%[0-9]+]]:tgpr, $cpsr = tROR [[COPY1]], [[COPY]], 14, $noreg
382 ; CHECK: tBcc %bb.2, 1, $cpsr
383 ; CHECK: tB %bb.1, 14, $noreg
385 successors: %bb.2(0x40000000), %bb.1(0x40000000)
390 %2:tgpr, dead $cpsr = tROR %0, %1, 14, $noreg
391 tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
397 tBX_RET 14, $noreg, implicit $r0
400 %4:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
402 tBX_RET 14, $noreg, implicit $r0