[ARM] More MVE compare vector splat combines for ANDs
[llvm-complete.git] / test / MC / ARM / clrm-asm.s
blob0ab7f36ee2d4f1e12eaf280dfdae13d25c545fcf
1 // RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -show-encoding < %s 2>%t \
2 // RUN: | FileCheck --check-prefix=CHECK %s
3 // RUN: FileCheck --check-prefix=ERROR < %t %s
5 // CHECK: clrm {r0, r1, r2, r3} @ encoding: [0x9f,0xe8,0x0f,0x00]
6 clrm {r0, r1, r2, r3}
8 // CHECK: clrm {r1, r2, r3, r4} @ encoding: [0x9f,0xe8,0x1e,0x00]
9 // ERROR-NOT: register list not in ascending order
10 clrm {r3, r4, r1, r2}
12 // CHECK: clrm {r0, apsr, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr} @ encoding: [0x9f,0xe8,0xff,0xdf]
13 clrm {r0-r12, lr, apsr}
15 // CHECK: clrm {apsr, lr} @ encoding: [0x9f,0xe8,0x00,0xc0]
16 clrm {apsr, lr}
18 // CHECK: clrm {r0, apsr, r1, r2, r3, r4, lr} @ encoding: [0x9f,0xe8,0x1f,0xc0]
19 clrm {r0-r4, apsr, lr}
21 // ERROR: invalid register in register list. Valid registers are r0-r12, lr/r14 and APSR.
22 clrm {sp}
24 // ERROR: invalid register in register list. Valid registers are r0-r12, lr/r14 and APSR.
25 clrm {r13}
27 // ERROR: invalid register in register list. Valid registers are r0-r12, lr/r14 and APSR.
28 clrm {r0-r12, sp}