include/llvm/CodeGen/TargetPassConfig.h

   1 //===- TargetPassConfig.h - Code Generation pass options --------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 /// Target-Independent Code Generator Pass Configuration Options pass.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_CODEGEN_TARGETPASSCONFIG_H
  14 #define LLVM_CODEGEN_TARGETPASSCONFIG_H
  15
  16 #include "llvm/Pass.h"
  17 #include "llvm/Support/CodeGen.h"
  18 #include <cassert>
  19 #include <string>
  20
  21 namespace llvm {
  22
  23 class LLVMTargetMachine;
  24 struct MachineSchedContext;
  25 class PassConfigImpl;
  26 class ScheduleDAGInstrs;
  27
  28 // The old pass manager infrastructure is hidden in a legacy namespace now.
  29 namespace legacy {
  30
  31 class PassManagerBase;
  32
  33 } // end namespace legacy
  34
  35 using legacy::PassManagerBase;
  36
  37 /// Discriminated union of Pass ID types.
  38 ///
  39 /// The PassConfig API prefers dealing with IDs because they are safer and more
  40 /// efficient. IDs decouple configuration from instantiation. This way, when a
  41 /// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to
  42 /// refer to a Pass pointer after adding it to a pass manager, which deletes
  43 /// redundant pass instances.
  44 ///
  45 /// However, it is convient to directly instantiate target passes with
  46 /// non-default ctors. These often don't have a registered PassInfo. Rather than
  47 /// force all target passes to implement the pass registry boilerplate, allow
  48 /// the PassConfig API to handle either type.
  49 ///
  50 /// AnalysisID is sadly char*, so PointerIntPair won't work.
  51 class IdentifyingPassPtr {
  52   union {
  53     AnalysisID ID;
  54     Pass *P;
  55   };
  56   bool IsInstance = false;
  57
  58 public:
  59   IdentifyingPassPtr() : P(nullptr) {}
  60   IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr) {}
  61   IdentifyingPassPtr(Pass *InstancePtr) : P(InstancePtr), IsInstance(true) {}
  62
  63   bool isValid() const { return P; }
  64   bool isInstance() const { return IsInstance; }
  65
  66   AnalysisID getID() const {
  67     assert(!IsInstance && "Not a Pass ID");
  68     return ID;
  69   }
  70
  71   Pass *getInstance() const {
  72     assert(IsInstance && "Not a Pass Instance");
  73     return P;
  74   }
  75 };
  76
  77
  78 /// Target-Independent Code Generator Pass Configuration Options.
  79 ///
  80 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
  81 /// to the internals of other CodeGen passes.
  82 class TargetPassConfig : public ImmutablePass {
  83 private:
  84   PassManagerBase *PM = nullptr;
  85   AnalysisID StartBefore = nullptr;
  86   AnalysisID StartAfter = nullptr;
  87   AnalysisID StopBefore = nullptr;
  88   AnalysisID StopAfter = nullptr;
  89
  90   unsigned StartBeforeInstanceNum = 0;
  91   unsigned StartBeforeCount = 0;
  92
  93   unsigned StartAfterInstanceNum = 0;
  94   unsigned StartAfterCount = 0;
  95
  96   unsigned StopBeforeInstanceNum = 0;
  97   unsigned StopBeforeCount = 0;
  98
  99   unsigned StopAfterInstanceNum = 0;
 100   unsigned StopAfterCount = 0;
 101
 102   bool Started = true;
 103   bool Stopped = false;
 104   bool AddingMachinePasses = false;
 105
 106   /// Set the StartAfter, StartBefore and StopAfter passes to allow running only
 107   /// a portion of the normal code-gen pass sequence.
 108   ///
 109   /// If the StartAfter and StartBefore pass ID is zero, then compilation will
 110   /// begin at the normal point; otherwise, clear the Started flag to indicate
 111   /// that passes should not be added until the starting pass is seen.  If the
 112   /// Stop pass ID is zero, then compilation will continue to the end.
 113   ///
 114   /// This function expects that at least one of the StartAfter or the
 115   /// StartBefore pass IDs is null.
 116   void setStartStopPasses();
 117
 118 protected:
 119   LLVMTargetMachine *TM;
 120   PassConfigImpl *Impl = nullptr; // Internal data structures
 121   bool Initialized = false; // Flagged after all passes are configured.
 122
 123   // Target Pass Options
 124   // Targets provide a default setting, user flags override.
 125   bool DisableVerify = false;
 126
 127   /// Default setting for -enable-tail-merge on this target.
 128   bool EnableTailMerge = true;
 129
 130   /// Require processing of functions such that callees are generated before
 131   /// callers.
 132   bool RequireCodeGenSCCOrder = false;
 133
 134   /// Add the actual instruction selection passes. This does not include
 135   /// preparation passes on IR.
 136   bool addCoreISelPasses();
 137
 138 public:
 139   TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm);
 140   // Dummy constructor.
 141   TargetPassConfig();
 142
 143   ~TargetPassConfig() override;
 144
 145   static char ID;
 146
 147   /// Get the right type of TargetMachine for this target.
 148   template<typename TMC> TMC &getTM() const {
 149     return *static_cast<TMC*>(TM);
 150   }
 151
 152   //
 153   void setInitialized() { Initialized = true; }
 154
 155   CodeGenOpt::Level getOptLevel() const;
 156
 157   /// Returns true if one of the `-start-after`, `-start-before`, `-stop-after`
 158   /// or `-stop-before` options is set.
 159   static bool hasLimitedCodeGenPipeline();
 160
 161   /// Returns true if none of the `-stop-before` and `-stop-after` options is
 162   /// set.
 163   static bool willCompleteCodeGenPipeline();
 164
 165   /// If hasLimitedCodeGenPipeline is true, this method
 166   /// returns a string with the name of the options, separated
 167   /// by \p Separator that caused this pipeline to be limited.
 168   std::string
 169   getLimitedCodeGenPipelineReason(const char *Separator = "/") const;
 170
 171   void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
 172
 173   bool getEnableTailMerge() const { return EnableTailMerge; }
 174   void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
 175
 176   bool requiresCodeGenSCCOrder() const { return RequireCodeGenSCCOrder; }
 177   void setRequiresCodeGenSCCOrder(bool Enable = true) {
 178     setOpt(RequireCodeGenSCCOrder, Enable);
 179   }
 180
 181   /// Allow the target to override a specific pass without overriding the pass
 182   /// pipeline. When passes are added to the standard pipeline at the
 183   /// point where StandardID is expected, add TargetID in its place.
 184   void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID);
 185
 186   /// Insert InsertedPassID pass after TargetPassID pass.
 187   void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
 188                   bool VerifyAfter = true, bool PrintAfter = true);
 189
 190   /// Allow the target to enable a specific standard pass by default.
 191   void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
 192
 193   /// Allow the target to disable a specific standard pass by default.
 194   void disablePass(AnalysisID PassID) {
 195     substitutePass(PassID, IdentifyingPassPtr());
 196   }
 197
 198   /// Return the pass substituted for StandardID by the target.
 199   /// If no substitution exists, return StandardID.
 200   IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const;
 201
 202   /// Return true if the pass has been substituted by the target or
 203   /// overridden on the command line.
 204   bool isPassSubstitutedOrOverridden(AnalysisID ID) const;
 205
 206   /// Return true if the optimized regalloc pipeline is enabled.
 207   bool getOptimizeRegAlloc() const;
 208
 209   /// Return true if the default global register allocator is in use and
 210   /// has not be overriden on the command line with '-regalloc=...'
 211   bool usingDefaultRegAlloc() const;
 212
 213   /// High level function that adds all passes necessary to go from llvm IR
 214   /// representation to the MI representation.
 215   /// Adds IR based lowering and target specific optimization passes and finally
 216   /// the core instruction selection passes.
 217   /// \returns true if an error occurred, false otherwise.
 218   bool addISelPasses();
 219
 220   /// Add common target configurable passes that perform LLVM IR to IR
 221   /// transforms following machine independent optimization.
 222   virtual void addIRPasses();
 223
 224   /// Add passes to lower exception handling for the code generator.
 225   void addPassesToHandleExceptions();
 226
 227   /// Add pass to prepare the LLVM IR for code generation. This should be done
 228   /// before exception handling preparation passes.
 229   virtual void addCodeGenPrepare();
 230
 231   /// Add common passes that perform LLVM IR to IR transforms in preparation for
 232   /// instruction selection.
 233   virtual void addISelPrepare();
 234
 235   /// addInstSelector - This method should install an instruction selector pass,
 236   /// which converts from LLVM code to machine instructions.
 237   virtual bool addInstSelector() {
 238     return true;
 239   }
 240
 241   /// This method should install an IR translator pass, which converts from
 242   /// LLVM code to machine instructions with possibly generic opcodes.
 243   virtual bool addIRTranslator() { return true; }
 244
 245   /// This method may be implemented by targets that want to run passes
 246   /// immediately before legalization.
 247   virtual void addPreLegalizeMachineIR() {}
 248
 249   /// This method should install a legalize pass, which converts the instruction
 250   /// sequence into one that can be selected by the target.
 251   virtual bool addLegalizeMachineIR() { return true; }
 252
 253   /// This method may be implemented by targets that want to run passes
 254   /// immediately before the register bank selection.
 255   virtual void addPreRegBankSelect() {}
 256
 257   /// This method should install a register bank selector pass, which
 258   /// assigns register banks to virtual registers without a register
 259   /// class or register banks.
 260   virtual bool addRegBankSelect() { return true; }
 261
 262   /// This method may be implemented by targets that want to run passes
 263   /// immediately before the (global) instruction selection.
 264   virtual void addPreGlobalInstructionSelect() {}
 265
 266   /// This method should install a (global) instruction selector pass, which
 267   /// converts possibly generic instructions to fully target-specific
 268   /// instructions, thereby constraining all generic virtual registers to
 269   /// register classes.
 270   virtual bool addGlobalInstructionSelect() { return true; }
 271
 272   /// Add the complete, standard set of LLVM CodeGen passes.
 273   /// Fully developed targets will not generally override this.
 274   virtual void addMachinePasses();
 275
 276   /// Create an instance of ScheduleDAGInstrs to be run within the standard
 277   /// MachineScheduler pass for this function and target at the current
 278   /// optimization level.
 279   ///
 280   /// This can also be used to plug a new MachineSchedStrategy into an instance
 281   /// of the standard ScheduleDAGMI:
 282   ///   return new ScheduleDAGMI(C, make_unique<MyStrategy>(C), /*RemoveKillFlags=*/false)
 283   ///
 284   /// Return NULL to select the default (generic) machine scheduler.
 285   virtual ScheduleDAGInstrs *
 286   createMachineScheduler(MachineSchedContext *C) const {
 287     return nullptr;
 288   }
 289
 290   /// Similar to createMachineScheduler but used when postRA machine scheduling
 291   /// is enabled.
 292   virtual ScheduleDAGInstrs *
 293   createPostMachineScheduler(MachineSchedContext *C) const {
 294     return nullptr;
 295   }
 296
 297   /// printAndVerify - Add a pass to dump then verify the machine function, if
 298   /// those steps are enabled.
 299   void printAndVerify(const std::string &Banner);
 300
 301   /// Add a pass to print the machine function if printing is enabled.
 302   void addPrintPass(const std::string &Banner);
 303
 304   /// Add a pass to perform basic verification of the machine function if
 305   /// verification is enabled.
 306   void addVerifyPass(const std::string &Banner);
 307
 308   /// Check whether or not GlobalISel should abort on error.
 309   /// When this is disabled, GlobalISel will fall back on SDISel instead of
 310   /// erroring out.
 311   bool isGlobalISelAbortEnabled() const;
 312
 313   /// Check whether or not a diagnostic should be emitted when GlobalISel
 314   /// uses the fallback path. In other words, it will emit a diagnostic
 315   /// when GlobalISel failed and isGlobalISelAbortEnabled is false.
 316   virtual bool reportDiagnosticWhenGlobalISelFallback() const;
 317
 318   /// Check whether continuous CSE should be enabled in GISel passes.
 319   /// By default, it's enabled for non O0 levels.
 320   virtual bool isGISelCSEEnabled() const;
 321
 322 protected:
 323   // Helper to verify the analysis is really immutable.
 324   void setOpt(bool &Opt, bool Val);
 325
 326   /// Methods with trivial inline returns are convenient points in the common
 327   /// codegen pass pipeline where targets may insert passes. Methods with
 328   /// out-of-line standard implementations are major CodeGen stages called by
 329   /// addMachinePasses. Some targets may override major stages when inserting
 330   /// passes is insufficient, but maintaining overriden stages is more work.
 331   ///
 332
 333   /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
 334   /// passes (which are run just before instruction selector).
 335   virtual bool addPreISel() {
 336     return true;
 337   }
 338
 339   /// addMachineSSAOptimization - Add standard passes that optimize machine
 340   /// instructions in SSA form.
 341   virtual void addMachineSSAOptimization();
 342
 343   /// Add passes that optimize instruction level parallelism for out-of-order
 344   /// targets. These passes are run while the machine code is still in SSA
 345   /// form, so they can use MachineTraceMetrics to control their heuristics.
 346   ///
 347   /// All passes added here should preserve the MachineDominatorTree,
 348   /// MachineLoopInfo, and MachineTraceMetrics analyses.
 349   virtual bool addILPOpts() {
 350     return false;
 351   }
 352
 353   /// This method may be implemented by targets that want to run passes
 354   /// immediately before register allocation.
 355   virtual void addPreRegAlloc() { }
 356
 357   /// createTargetRegisterAllocator - Create the register allocator pass for
 358   /// this target at the current optimization level.
 359   virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
 360
 361   /// addFastRegAlloc - Add the minimum set of target-independent passes that
 362   /// are required for fast register allocation.
 363   virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
 364
 365   /// addOptimizedRegAlloc - Add passes related to register allocation.
 366   /// LLVMTargetMachine provides standard regalloc passes for most targets.
 367   virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
 368
 369   /// addPreRewrite - Add passes to the optimized register allocation pipeline
 370   /// after register allocation is complete, but before virtual registers are
 371   /// rewritten to physical registers.
 372   ///
 373   /// These passes must preserve VirtRegMap and LiveIntervals, and when running
 374   /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
 375   /// When these passes run, VirtRegMap contains legal physreg assignments for
 376   /// all virtual registers.
 377   virtual bool addPreRewrite() {
 378     return false;
 379   }
 380
 381   /// This method may be implemented by targets that want to run passes after
 382   /// register allocation pass pipeline but before prolog-epilog insertion.
 383   virtual void addPostRegAlloc() { }
 384
 385   /// Add passes that optimize machine instructions after register allocation.
 386   virtual void addMachineLateOptimization();
 387
 388   /// This method may be implemented by targets that want to run passes after
 389   /// prolog-epilog insertion and before the second instruction scheduling pass.
 390   virtual void addPreSched2() { }
 391
 392   /// addGCPasses - Add late codegen passes that analyze code for garbage
 393   /// collection. This should return true if GC info should be printed after
 394   /// these passes.
 395   virtual bool addGCPasses();
 396
 397   /// Add standard basic block placement passes.
 398   virtual void addBlockPlacement();
 399
 400   /// This pass may be implemented by targets that want to run passes
 401   /// immediately before machine code is emitted.
 402   virtual void addPreEmitPass() { }
 403
 404   /// Targets may add passes immediately before machine code is emitted in this
 405   /// callback. This is called even later than `addPreEmitPass`.
 406   // FIXME: Rename `addPreEmitPass` to something more sensible given its actual
 407   // position and remove the `2` suffix here as this callback is what
 408   // `addPreEmitPass` *should* be but in reality isn't.
 409   virtual void addPreEmitPass2() {}
 410
 411   /// Utilities for targets to add passes to the pass manager.
 412   ///
 413
 414   /// Add a CodeGen pass at this point in the pipeline after checking overrides.
 415   /// Return the pass that was added, or zero if no pass was added.
 416   /// @p printAfter    if true and adding a machine function pass add an extra
 417   ///                  machine printer pass afterwards
 418   /// @p verifyAfter   if true and adding a machine function pass add an extra
 419   ///                  machine verification pass afterwards.
 420   AnalysisID addPass(AnalysisID PassID, bool verifyAfter = true,
 421                      bool printAfter = true);
 422
 423   /// Add a pass to the PassManager if that pass is supposed to be run, as
 424   /// determined by the StartAfter and StopAfter options. Takes ownership of the
 425   /// pass.
 426   /// @p printAfter    if true and adding a machine function pass add an extra
 427   ///                  machine printer pass afterwards
 428   /// @p verifyAfter   if true and adding a machine function pass add an extra
 429   ///                  machine verification pass afterwards.
 430   void addPass(Pass *P, bool verifyAfter = true, bool printAfter = true);
 431
 432   /// addMachinePasses helper to create the target-selected or overriden
 433   /// regalloc pass.
 434   FunctionPass *createRegAllocPass(bool Optimized);
 435 };
 436
 437 } // end namespace llvm
 438
 439 #endif // LLVM_CODEGEN_TARGETPASSCONFIG_H