lib/Target/Mips/MipsLegalizerInfo.cpp

   1 //===- MipsLegalizerInfo.cpp ------------------------------------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 /// \file
   9 /// This file implements the targeting of the Machinelegalizer class for Mips.
  10 /// \todo This should be generated by TableGen.
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "MipsLegalizerInfo.h"
  14 #include "MipsTargetMachine.h"
  15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
  16
  17 using namespace llvm;
  18
  19 MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
  20   using namespace TargetOpcode;
  21
  22   const LLT s1 = LLT::scalar(1);
  23   const LLT s32 = LLT::scalar(32);
  24   const LLT s64 = LLT::scalar(64);
  25   const LLT p0 = LLT::pointer(0, 32);
  26
  27   getActionDefinitionsBuilder({G_ADD, G_SUB})
  28       .legalFor({s32})
  29       .clampScalar(0, s32, s32);
  30
  31   getActionDefinitionsBuilder(G_MUL)
  32       .legalFor({s32})
  33       .minScalar(0, s32);
  34
  35   getActionDefinitionsBuilder({G_UADDE, G_USUBO, G_USUBE})
  36       .lowerFor({{s32, s1}});
  37
  38   getActionDefinitionsBuilder({G_LOAD, G_STORE})
  39       .legalForTypesWithMemDesc({{s32, p0, 8, 8},
  40                                  {s32, p0, 16, 8},
  41                                  {s32, p0, 32, 8},
  42                                  {p0, p0, 32, 8}})
  43       .minScalar(0, s32);
  44
  45   getActionDefinitionsBuilder({G_ZEXTLOAD, G_SEXTLOAD})
  46     .legalForTypesWithMemDesc({{s32, p0, 8, 8},
  47                                {s32, p0, 16, 8}})
  48       .minScalar(0, s32);
  49
  50   getActionDefinitionsBuilder(G_SELECT)
  51       .legalForCartesianProduct({p0, s32}, {s32})
  52       .minScalar(0, s32)
  53       .minScalar(1, s32);
  54
  55   getActionDefinitionsBuilder(G_BRCOND)
  56       .legalFor({s32})
  57       .minScalar(0, s32);
  58
  59   getActionDefinitionsBuilder(G_PHI)
  60       .legalFor({p0, s32})
  61       .minScalar(0, s32);
  62
  63   getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
  64       .legalFor({s32})
  65       .clampScalar(0, s32, s32);
  66
  67   getActionDefinitionsBuilder({G_SDIV, G_SREM, G_UREM, G_UDIV})
  68       .legalFor({s32})
  69       .minScalar(0, s32)
  70       .libcallFor({s64});
  71
  72   getActionDefinitionsBuilder({G_SHL, G_ASHR, G_LSHR})
  73     .legalFor({s32, s32})
  74     .minScalar(1, s32);
  75
  76   getActionDefinitionsBuilder(G_ICMP)
  77       .legalFor({{s32, s32}})
  78       .minScalar(0, s32);
  79
  80   getActionDefinitionsBuilder(G_CONSTANT)
  81       .legalFor({s32})
  82       .clampScalar(0, s32, s32);
  83
  84   getActionDefinitionsBuilder(G_GEP)
  85       .legalFor({{p0, s32}});
  86
  87   getActionDefinitionsBuilder(G_FRAME_INDEX)
  88       .legalFor({p0});
  89
  90   getActionDefinitionsBuilder(G_GLOBAL_VALUE)
  91       .legalFor({p0});
  92
  93   computeTables();
  94   verify(*ST.getInstrInfo());
  95 }
  96
  97 bool MipsLegalizerInfo::legalizeCustom(MachineInstr &MI,
  98                                        MachineRegisterInfo &MRI,
  99                                        MachineIRBuilder &MIRBuilder,
 100                                        GISelChangeObserver &Observer) const {
 101
 102   using namespace TargetOpcode;
 103
 104   MIRBuilder.setInstr(MI);
 105
 106   return false;
 107 }