test/CodeGen/AMDGPU/si-lower-control-flow.mir

   1 # RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=si-lower-control-flow -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN %s
   2
   3 # Check that assert is not triggered
   4 # GCN-LABEL: name: si-lower-control-flow{{$}}
   5 # GCN-CHECK: S_LOAD_DWORD_IMM
   6
   7 --- |
   8
   9   define amdgpu_kernel void @si-lower-control-flow() {
  10     ret void
  11   }
  12
  13 ...
  14 ---
  15 name: si-lower-control-flow
  16 body: |
  17   bb.0:
  18     %0:sgpr_64 = COPY $sgpr4_sgpr5
  19     %1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0, 16, 0
  20     %2:sreg_32_xm0 = S_AND_B32 %1, 255, implicit-def $scc
  21     %3:sreg_32_xm0 = S_AND_B32 65535, %2, implicit-def $scc
  22     S_ENDPGM
  23 ...