1 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=SICIVI -check-prefix=SICI -check-prefix=SIVIGFX9 %s
2 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=CI -check-prefix=GCN -check-prefix=SICIVI -check-prefix=SICI %s
3 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=SICIVI -check-prefix=VIGFX9 -check-prefix=SIVIGFX9 %s
4 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN -check-prefix=VIGFX9 -check-prefix=SIVIGFX9 %s
6 ; SMRD load with an immediate offset.
7 ; GCN-LABEL: {{^}}smrd0:
8 ; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x1 ; encoding: [0x01
9 ; VIGFX9: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4
10 define amdgpu_kernel void @smrd0(i32 addrspace(1)* %out, i32 addrspace(4)* %ptr) #0 {
12 %tmp = getelementptr i32, i32 addrspace(4)* %ptr, i64 1
13 %tmp1 = load i32, i32 addrspace(4)* %tmp
14 store i32 %tmp1, i32 addrspace(1)* %out
18 ; SMRD load with the largest possible immediate offset.
19 ; GCN-LABEL: {{^}}smrd1:
20 ; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff,0x{{[0-9]+[137]}}
21 ; VIGFX9: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc
22 define amdgpu_kernel void @smrd1(i32 addrspace(1)* %out, i32 addrspace(4)* %ptr) #0 {
24 %tmp = getelementptr i32, i32 addrspace(4)* %ptr, i64 255
25 %tmp1 = load i32, i32 addrspace(4)* %tmp
26 store i32 %tmp1, i32 addrspace(1)* %out
30 ; SMRD load with an offset greater than the largest possible immediate.
31 ; GCN-LABEL: {{^}}smrd2:
32 ; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x400
33 ; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]
34 ; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x100
35 ; VIGFX9: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400
37 define amdgpu_kernel void @smrd2(i32 addrspace(1)* %out, i32 addrspace(4)* %ptr) #0 {
39 %tmp = getelementptr i32, i32 addrspace(4)* %ptr, i64 256
40 %tmp1 = load i32, i32 addrspace(4)* %tmp
41 store i32 %tmp1, i32 addrspace(1)* %out
45 ; SMRD load with a 64-bit offset
46 ; GCN-LABEL: {{^}}smrd3:
47 ; FIXME: There are too many copies here because we don't fold immediates
48 ; through REG_SEQUENCE
49 ; SI: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[{{[0-9]:[0-9]}}], 0x13 ; encoding: [0x13
52 define amdgpu_kernel void @smrd3(i32 addrspace(1)* %out, [8 x i32], i32 addrspace(4)* %ptr) #0 {
54 %tmp = getelementptr i32, i32 addrspace(4)* %ptr, i64 4294967296
55 %tmp1 = load i32, i32 addrspace(4)* %tmp
56 store i32 %tmp1, i32 addrspace(1)* %out
60 ; SMRD load with the largest possible immediate offset on VI
61 ; GCN-LABEL: {{^}}smrd4:
62 ; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc
63 ; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
64 ; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff
65 ; VIGFX9: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc
66 define amdgpu_kernel void @smrd4(i32 addrspace(1)* %out, i32 addrspace(4)* %ptr) #0 {
68 %tmp = getelementptr i32, i32 addrspace(4)* %ptr, i64 262143
69 %tmp1 = load i32, i32 addrspace(4)* %tmp
70 store i32 %tmp1, i32 addrspace(1)* %out
74 ; SMRD load with an offset greater than the largest possible immediate on VI
75 ; GCN-LABEL: {{^}}smrd5:
76 ; SIVIGFX9: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000
77 ; SIVIGFX9: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
78 ; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40000
80 define amdgpu_kernel void @smrd5(i32 addrspace(1)* %out, i32 addrspace(4)* %ptr) #0 {
82 %tmp = getelementptr i32, i32 addrspace(4)* %ptr, i64 262144
83 %tmp1 = load i32, i32 addrspace(4)* %tmp
84 store i32 %tmp1, i32 addrspace(1)* %out
88 ; GCN-LABEL: {{^}}smrd_hazard:
89 ; GCN-DAG: s_mov_b32 s3, 3
90 ; GCN-DAG: s_mov_b32 s2, 2
91 ; GCN-DAG: s_mov_b32 s1, 1
92 ; GCN-DAG: s_mov_b32 s0, 0
94 ; GCN-NEXT: s_buffer_load_dword s0, s[0:3], 0x0
95 define amdgpu_ps float @smrd_hazard(<4 x i32> inreg %desc) #0 {
97 %d0 = insertelement <4 x i32> undef, i32 0, i32 0
98 %d1 = insertelement <4 x i32> %d0, i32 1, i32 1
99 %d2 = insertelement <4 x i32> %d1, i32 2, i32 2
100 %d3 = insertelement <4 x i32> %d2, i32 3, i32 3
101 %r = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %d3, i32 0, i32 0)
105 ; SMRD load using the load.const.v4i32 intrinsic with an immediate offset
106 ; GCN-LABEL: {{^}}smrd_load_const0:
107 ; SICI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4 ; encoding: [0x04
108 ; VIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x10
109 define amdgpu_ps void @smrd_load_const0(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, <4 x i32> addrspace(4)* inreg %in) #0 {
111 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0
112 %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp
113 %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 16, i32 0)
114 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %tmp21, i1 true, i1 true) #0
118 ; SMRD load using the load.const.v4i32 intrinsic with the largest possible immediate
120 ; GCN-LABEL: {{^}}smrd_load_const1:
121 ; SICI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff
122 ; SICI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff glc ; encoding: [0xff
123 ; VIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc
124 ; VIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc glc
125 define amdgpu_ps void @smrd_load_const1(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, <4 x i32> addrspace(4)* inreg %in) #0 {
127 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0
128 %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp
129 %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 1020, i32 0)
130 %tmp22 = load <4 x i32>, <4 x i32> addrspace(4)* %in
131 %s.buffer = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %tmp22, i32 1020, i32 1)
132 %s.buffer.float = bitcast i32 %s.buffer to float
133 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %s.buffer.float, i1 true, i1 true) #0
137 ; SMRD load using the load.const.v4i32 intrinsic with an offset greater than the
138 ; largets possible immediate.
140 ; GCN-LABEL: {{^}}smrd_load_const2:
141 ; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x400
142 ; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]
143 ; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]
144 ; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x100
145 ; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x100
146 ; VIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400
147 ; VIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400
148 define amdgpu_ps void @smrd_load_const2(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, <4 x i32> addrspace(4)* inreg %in) #0 {
150 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0
151 %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp
152 %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 1024, i32 0)
153 %tmp22 = load <4 x i32>, <4 x i32> addrspace(4)* %in
154 %s.buffer = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %tmp22, i32 1024, i32 0)
155 %s.buffer.float = bitcast i32 %s.buffer to float
156 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %s.buffer.float, i1 true, i1 true) #0
160 ; SMRD load with the largest possible immediate offset on VI
161 ; GCN-LABEL: {{^}}smrd_load_const3:
162 ; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc
163 ; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
164 ; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
165 ; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff
166 ; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff
167 ; VIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc
168 ; VIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc
169 define amdgpu_ps void @smrd_load_const3(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, <4 x i32> addrspace(4)* inreg %in) #0 {
171 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0
172 %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp
173 %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 1048572, i32 0)
174 %tmp22 = load <4 x i32>, <4 x i32> addrspace(4)* %in
175 %s.buffer = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %tmp22, i32 1048572, i32 0)
176 %s.buffer.float = bitcast i32 %s.buffer to float
177 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %s.buffer.float, i1 true, i1 true) #0
181 ; SMRD load with an offset greater than the largest possible immediate on VI
182 ; GCN-LABEL: {{^}}smrd_load_const4:
183 ; SIVIGFX9: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000
184 ; SIVIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
185 ; SIVIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
186 ; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40000
187 ; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40000
189 define amdgpu_ps void @smrd_load_const4(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, <4 x i32> addrspace(4)* inreg %in) #0 {
191 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0
192 %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp
193 %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 1048576, i32 0)
194 %tmp22 = load <4 x i32>, <4 x i32> addrspace(4)* %in
195 %s.buffer = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %tmp22, i32 1048576, i32 0)
196 %s.buffer.float = bitcast i32 %s.buffer to float
197 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %s.buffer.float, i1 true, i1 true) #0
201 ; dwordx2 s.buffer.load
202 ; GCN-LABEL: {{^}}s_buffer_load_dwordx2:
203 ; VIGFX9: s_buffer_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0x80
204 ; SICI: s_buffer_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0x20
205 define amdgpu_ps void @s_buffer_load_dwordx2(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, <4 x i32> addrspace(4)* inreg %in) #0 {
207 %tmp22 = load <4 x i32>, <4 x i32> addrspace(4)* %in
208 %s.buffer = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %tmp22, i32 128, i32 0)
209 %s.buffer.0 = extractelement <2 x i32> %s.buffer, i32 0
210 %s.buffer.0.float = bitcast i32 %s.buffer.0 to float
211 %s.buffer.1 = extractelement <2 x i32> %s.buffer, i32 1
212 %s.buffer.1.float = bitcast i32 %s.buffer.1 to float
213 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %s.buffer.0.float, float %s.buffer.1.float, float %s.buffer.0.float, float %s.buffer.1.float, i1 true, i1 true) #0
217 ; dwordx4 s.buffer.load
218 ; GCN-LABEL: {{^}}s_buffer_load_dwordx4:
219 ; VIGFX9: s_buffer_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0x80
220 ; SICI: s_buffer_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0x20
221 define amdgpu_ps void @s_buffer_load_dwordx4(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, <4 x i32> addrspace(4)* inreg %in) #0 {
223 %tmp22 = load <4 x i32>, <4 x i32> addrspace(4)* %in
224 %s.buffer = call <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32> %tmp22, i32 128, i32 0)
225 %s.buffer.0 = extractelement <4 x i32> %s.buffer, i32 0
226 %s.buffer.0.float = bitcast i32 %s.buffer.0 to float
227 %s.buffer.1 = extractelement <4 x i32> %s.buffer, i32 1
228 %s.buffer.1.float = bitcast i32 %s.buffer.1 to float
229 %s.buffer.2 = extractelement <4 x i32> %s.buffer, i32 2
230 %s.buffer.2.float = bitcast i32 %s.buffer.2 to float
231 %s.buffer.3 = extractelement <4 x i32> %s.buffer, i32 3
232 %s.buffer.3.float = bitcast i32 %s.buffer.3 to float
233 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %s.buffer.0.float, float %s.buffer.1.float, float %s.buffer.2.float, float %s.buffer.3.float, i1 true, i1 true) #0
237 ; dwordx8 s.buffer.load
238 ; GCN-LABEL: {{^}}s_buffer_load_dwordx8:
239 ; VIGFX9: s_buffer_load_dwordx8 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0x80
240 ; SICI: s_buffer_load_dwordx8 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0x20
241 define amdgpu_ps void @s_buffer_load_dwordx8(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, <4 x i32> addrspace(4)* inreg %in) #0 {
243 %tmp22 = load <4 x i32>, <4 x i32> addrspace(4)* %in
244 %s.buffer = call <8 x i32> @llvm.amdgcn.s.buffer.load.v8i32(<4 x i32> %tmp22, i32 128, i32 0)
245 %s.buffer.0 = extractelement <8 x i32> %s.buffer, i32 0
246 %s.buffer.0.float = bitcast i32 %s.buffer.0 to float
247 %s.buffer.1 = extractelement <8 x i32> %s.buffer, i32 2
248 %s.buffer.1.float = bitcast i32 %s.buffer.1 to float
249 %s.buffer.2 = extractelement <8 x i32> %s.buffer, i32 5
250 %s.buffer.2.float = bitcast i32 %s.buffer.2 to float
251 %s.buffer.3 = extractelement <8 x i32> %s.buffer, i32 7
252 %s.buffer.3.float = bitcast i32 %s.buffer.3 to float
253 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %s.buffer.0.float, float %s.buffer.1.float, float %s.buffer.2.float, float %s.buffer.3.float, i1 true, i1 true) #0
257 ; dwordx16 s.buffer.load
258 ; GCN-LABEL: {{^}}s_buffer_load_dwordx16:
259 ; VIGFX9: s_buffer_load_dwordx16 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0x80
260 ; SICI: s_buffer_load_dwordx16 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0x20
261 define amdgpu_ps void @s_buffer_load_dwordx16(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, <4 x i32> addrspace(4)* inreg %in) #0 {
263 %tmp22 = load <4 x i32>, <4 x i32> addrspace(4)* %in
264 %s.buffer = call <16 x i32> @llvm.amdgcn.s.buffer.load.v16i32(<4 x i32> %tmp22, i32 128, i32 0)
265 %s.buffer.0 = extractelement <16 x i32> %s.buffer, i32 0
266 %s.buffer.0.float = bitcast i32 %s.buffer.0 to float
267 %s.buffer.1 = extractelement <16 x i32> %s.buffer, i32 3
268 %s.buffer.1.float = bitcast i32 %s.buffer.1 to float
269 %s.buffer.2 = extractelement <16 x i32> %s.buffer, i32 12
270 %s.buffer.2.float = bitcast i32 %s.buffer.2 to float
271 %s.buffer.3 = extractelement <16 x i32> %s.buffer, i32 15
272 %s.buffer.3.float = bitcast i32 %s.buffer.3 to float
273 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %s.buffer.0.float, float %s.buffer.1.float, float %s.buffer.2.float, float %s.buffer.3.float, i1 true, i1 true) #0
277 ; GCN-LABEL: {{^}}smrd_sgpr_offset:
278 ; GCN: s_buffer_load_dword s{{[0-9]}}, s[0:3], s4
279 define amdgpu_ps float @smrd_sgpr_offset(<4 x i32> inreg %desc, i32 inreg %offset) #0 {
281 %r = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %offset, i32 0)
285 ; GCN-LABEL: {{^}}smrd_vgpr_offset:
286 ; GCN: buffer_load_dword v{{[0-9]}}, v0, s[0:3], 0 offen ;
287 define amdgpu_ps float @smrd_vgpr_offset(<4 x i32> inreg %desc, i32 %offset) #0 {
289 %r = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %offset, i32 0)
293 ; GCN-LABEL: {{^}}smrd_vgpr_offset_imm:
295 ; GCN-NEXT: buffer_load_dword v{{[0-9]}}, v0, s[0:3], 0 offen offset:4092 ;
296 define amdgpu_ps float @smrd_vgpr_offset_imm(<4 x i32> inreg %desc, i32 %offset) #0 {
298 %off = add i32 %offset, 4092
299 %r = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %off, i32 0)
303 ; GCN-LABEL: {{^}}smrd_vgpr_offset_imm_too_large:
305 ; SICI-NEXT: v_add_{{i|u}}32_e32 v0, {{(vcc, )?}}0x1000, v0
306 ; SICI-NEXT: buffer_load_dword v{{[0-9]}}, v0, s[0:3], 0 offen ;
307 ; VIGFX9-NEXT: buffer_load_dword v{{[0-9]}}, v0, s[0:3], 4 offen offset:4092 ;
308 define amdgpu_ps float @smrd_vgpr_offset_imm_too_large(<4 x i32> inreg %desc, i32 %offset) #0 {
310 %off = add i32 %offset, 4096
311 %r = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %off, i32 0)
315 ; GCN-LABEL: {{^}}smrd_imm_merged:
317 ; SICI-NEXT: s_buffer_load_dwordx4 s[{{[0-9]}}:{{[0-9]}}], s[0:3], 0x1
318 ; SICI-NEXT: s_buffer_load_dwordx2 s[{{[0-9]}}:{{[0-9]}}], s[0:3], 0x7
319 ; VIGFX9-NEXT: s_buffer_load_dwordx4 s[{{[0-9]}}:{{[0-9]}}], s[0:3], 0x4
320 ; VIGFX9-NEXT: s_buffer_load_dwordx2 s[{{[0-9]}}:{{[0-9]}}], s[0:3], 0x1c
321 define amdgpu_ps void @smrd_imm_merged(<4 x i32> inreg %desc) #0 {
323 %r1 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 4, i32 0)
324 %r2 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 8, i32 0)
325 %r3 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 12, i32 0)
326 %r4 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 16, i32 0)
327 %r5 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 28, i32 0)
328 %r6 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 32, i32 0)
329 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) #0
330 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) #0
334 ; GCN-LABEL: {{^}}smrd_imm_merge_m0:
336 ; GCN: s_buffer_load_dwordx2
337 ; SICIVI: s_mov_b32 m0
338 ; SICIVI_DAG: v_interp_p1_f32
339 ; SICIVI_DAG: v_interp_p1_f32
340 ; SICIVI_DAG: v_interp_p1_f32
341 ; SICIVI_DAG: v_interp_p2_f32
342 ; SICIVI_DAG: v_interp_p2_f32
343 ; SICIVI_DAG: v_interp_p2_f32
345 ; extractelement does not result in movrels anymore for vectors gitting 8 dwords
346 ; SICIVI-NOT: s_mov_b32 m0
347 ; SICIVI-NOT: v_movrels_b32_e32
351 ; Merging is still thwarted on GFX9 due to s_set_gpr_idx
353 define amdgpu_ps float @smrd_imm_merge_m0(<4 x i32> inreg %desc, i32 inreg %prim, float %u, float %v) #0 {
355 %idx1.f = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 0, i32 0)
356 %idx1 = bitcast float %idx1.f to i32
358 %v0.x1 = call nsz float @llvm.amdgcn.interp.p1(float %u, i32 0, i32 0, i32 %prim)
359 %v0.x = call nsz float @llvm.amdgcn.interp.p2(float %v0.x1, float %v, i32 0, i32 0, i32 %prim)
360 %v0.y1 = call nsz float @llvm.amdgcn.interp.p1(float %u, i32 0, i32 1, i32 %prim)
361 %v0.y = call nsz float @llvm.amdgcn.interp.p2(float %v0.y1, float %v, i32 0, i32 1, i32 %prim)
362 %v0.z1 = call nsz float @llvm.amdgcn.interp.p1(float %u, i32 0, i32 2, i32 %prim)
363 %v0.z = call nsz float @llvm.amdgcn.interp.p2(float %v0.z1, float %v, i32 0, i32 2, i32 %prim)
364 %v0.tmp0 = insertelement <3 x float> undef, float %v0.x, i32 0
365 %v0.tmp1 = insertelement <3 x float> %v0.tmp0, float %v0.y, i32 1
366 %v0 = insertelement <3 x float> %v0.tmp1, float %v0.z, i32 2
367 %a = extractelement <3 x float> %v0, i32 %idx1
369 %v1.x1 = call nsz float @llvm.amdgcn.interp.p1(float %u, i32 1, i32 0, i32 %prim)
370 %v1.x = call nsz float @llvm.amdgcn.interp.p2(float %v1.x1, float %v, i32 1, i32 0, i32 %prim)
371 %v1.y1 = call nsz float @llvm.amdgcn.interp.p1(float %u, i32 1, i32 1, i32 %prim)
372 %v1.y = call nsz float @llvm.amdgcn.interp.p2(float %v1.y1, float %v, i32 1, i32 1, i32 %prim)
373 %v1.z1 = call nsz float @llvm.amdgcn.interp.p1(float %u, i32 1, i32 2, i32 %prim)
374 %v1.z = call nsz float @llvm.amdgcn.interp.p2(float %v1.z1, float %v, i32 1, i32 2, i32 %prim)
375 %v1.tmp0 = insertelement <3 x float> undef, float %v0.x, i32 0
376 %v1.tmp1 = insertelement <3 x float> %v0.tmp0, float %v0.y, i32 1
377 %v1 = insertelement <3 x float> %v0.tmp1, float %v0.z, i32 2
379 %b = extractelement <3 x float> %v1, i32 %idx1
380 %c = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 4, i32 0)
382 %res.tmp = fadd float %a, %b
383 %res = fadd float %res.tmp, %c
387 ; GCN-LABEL: {{^}}smrd_vgpr_merged:
389 ; GCN-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4
390 ; GCN-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:28
391 define amdgpu_ps void @smrd_vgpr_merged(<4 x i32> inreg %desc, i32 %a) #0 {
399 %r1 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %a1, i32 0)
400 %r2 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %a2, i32 0)
401 %r3 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %a3, i32 0)
402 %r4 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %a4, i32 0)
403 %r5 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %a5, i32 0)
404 %r6 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %a6, i32 0)
405 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) #0
406 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) #0
410 ; GCN-LABEL: {{^}}smrd_sgpr_descriptor_promoted
411 ; GCN: v_readfirstlane
412 define amdgpu_cs void @smrd_sgpr_descriptor_promoted([0 x i8] addrspace(4)* inreg noalias dereferenceable(18446744073709551615), i32) #0 {
414 %descptr = bitcast [0 x i8] addrspace(4)* %0 to <4 x i32> addrspace(4)*, !amdgpu.uniform !0
415 br label %.outer_loop_header
417 ret_block: ; preds = %.outer, %.label22, %main_body
421 br label %.inner_loop_header
423 .inner_loop_header: ; preds = %.inner_loop_body, %.outer_loop_header
424 %loopctr.1 = phi i32 [ 0, %.outer_loop_header ], [ %loopctr.2, %.inner_loop_body ]
425 %loopctr.2 = add i32 %loopctr.1, 1
426 %inner_br1 = icmp slt i32 %loopctr.2, 10
427 br i1 %inner_br1, label %.inner_loop_body, label %ret_block
430 %descriptor = load <4 x i32>, <4 x i32> addrspace(4)* %descptr, align 16, !invariant.load !0
431 %load1result = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %descriptor, i32 0, i32 0)
432 store float %load1result, float addrspace(1)* undef
433 %inner_br2 = icmp uge i32 %1, 10
434 br i1 %inner_br2, label %.inner_loop_header, label %.outer_loop_body
437 %offset = shl i32 %loopctr.2, 6
438 %load2result = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %descriptor, i32 %offset, i32 0)
439 %outer_br = fcmp ueq float %load2result, 0x0
440 br i1 %outer_br, label %.outer_loop_header, label %ret_block
443 ; SMRD load with a non-const offset
444 ; GCN-LABEL: {{^}}smrd_load_nonconst0:
445 ; SIVIGFX9: s_buffer_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}}
446 ; SIVIGFX9: s_buffer_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}}
447 ; CI: s_buffer_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}}
448 ; CI: s_buffer_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}}
450 define amdgpu_ps void @smrd_load_nonconst0(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, <4 x i32> addrspace(4)* inreg %in, i32 inreg %ncoff) #0 {
452 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0
453 %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp
454 %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 %ncoff, i32 0)
455 %tmp22 = load <4 x i32>, <4 x i32> addrspace(4)* %in
456 %s.buffer = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %tmp22, i32 %ncoff, i32 0)
457 %s.buffer.float = bitcast i32 %s.buffer to float
458 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %s.buffer.float, i1 true, i1 true) #0
462 ; SMRD load with a non-const non-uniform offset
463 ; GCN-LABEL: {{^}}smrd_load_nonconst1:
464 ; SIVIGFX9: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
465 ; SIVIGFX9: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
466 ; CI: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
467 ; CI: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
469 define amdgpu_ps void @smrd_load_nonconst1(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, <4 x i32> addrspace(4)* inreg %in, i32 %ncoff) #0 {
471 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0
472 %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp
473 %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 %ncoff, i32 0)
474 %tmp22 = load <4 x i32>, <4 x i32> addrspace(4)* %in
475 %s.buffer = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %tmp22, i32 %ncoff, i32 0)
476 %s.buffer.float = bitcast i32 %s.buffer to float
477 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %s.buffer.float, i1 true, i1 true) #0
481 ; SMRD load with a non-const non-uniform offset of > 4 dwords (requires splitting)
482 ; GCN-LABEL: {{^}}smrd_load_nonconst2:
483 ; SIVIGFX9: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
484 ; SIVIGFX9: buffer_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
485 ; CI: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
486 ; CI: buffer_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
488 define amdgpu_ps void @smrd_load_nonconst2(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, <4 x i32> addrspace(4)* inreg %in, i32 %ncoff) #0 {
490 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0
491 %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp
492 %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 %ncoff, i32 0)
493 %tmp22 = load <4 x i32>, <4 x i32> addrspace(4)* %in
494 %s.buffer = call <8 x i32> @llvm.amdgcn.s.buffer.load.v8i32(<4 x i32> %tmp22, i32 %ncoff, i32 0)
495 %s.buffer.elt = extractelement <8 x i32> %s.buffer, i32 1
496 %s.buffer.float = bitcast i32 %s.buffer.elt to float
497 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %s.buffer.float, i1 true, i1 true) #0
501 ; SMRD load with a non-const non-uniform offset of > 4 dwords (requires splitting)
502 ; GCN-LABEL: {{^}}smrd_load_nonconst3:
503 ; GCN-DAG: buffer_load_dwordx4 v[0:3], v{{[0-9]+}}, s[0:3], 0 offen ;
504 ; GCN-DAG: buffer_load_dwordx4 v[4:7], v{{[0-9]+}}, s[0:3], 0 offen offset:16 ;
505 ; GCN-DAG: buffer_load_dwordx4 v[8:11], v{{[0-9]+}}, s[0:3], 0 offen offset:32 ;
506 ; GCN-DAG: buffer_load_dwordx4 v[12:15], v{{[0-9]+}}, s[0:3], 0 offen offset:48 ;
507 ; GCN: ; return to shader part epilog
508 define amdgpu_ps <16 x float> @smrd_load_nonconst3(<4 x i32> inreg %rsrc, i32 %off) #0 {
510 %ld = call <16 x i32> @llvm.amdgcn.s.buffer.load.v16i32(<4 x i32> %rsrc, i32 %off, i32 0)
511 %bc = bitcast <16 x i32> %ld to <16 x float>
515 ; GCN-LABEL: {{^}}smrd_load_nonconst4:
516 ; SICI: v_add_i32_e32 v{{[0-9]+}}, vcc, 0xff8, v0 ;
517 ; SICI-DAG: buffer_load_dwordx4 v[0:3], v{{[0-9]+}}, s[0:3], 0 offen ;
518 ; SICI-DAG: buffer_load_dwordx4 v[4:7], v{{[0-9]+}}, s[0:3], 0 offen offset:16 ;
519 ; SICI-DAG: buffer_load_dwordx4 v[8:11], v{{[0-9]+}}, s[0:3], 0 offen offset:32 ;
520 ; SICI-DAG: buffer_load_dwordx4 v[12:15], v{{[0-9]+}}, s[0:3], 0 offen offset:48 ;
521 ; VIGFX9-DAG: buffer_load_dwordx4 v[0:3], v{{[0-9]+}}, s[0:3], 56 offen offset:4032 ;
522 ; VIGFX9-DAG: buffer_load_dwordx4 v[4:7], v{{[0-9]+}}, s[0:3], 56 offen offset:4048 ;
523 ; VIGFX9-DAG: buffer_load_dwordx4 v[8:11], v{{[0-9]+}}, s[0:3], 56 offen offset:4064 ;
524 ; VIGFX9-DAG: buffer_load_dwordx4 v[12:15], v{{[0-9]+}}, s[0:3], 56 offen offset:4080 ;
525 ; GCN: ; return to shader part epilog
526 define amdgpu_ps <16 x float> @smrd_load_nonconst4(<4 x i32> inreg %rsrc, i32 %off) #0 {
528 %off.2 = add i32 %off, 4088
529 %ld = call <16 x i32> @llvm.amdgcn.s.buffer.load.v16i32(<4 x i32> %rsrc, i32 %off.2, i32 0)
530 %bc = bitcast <16 x i32> %ld to <16 x float>
534 ; GCN-LABEL: {{^}}smrd_load_nonconst5:
535 ; SICI: v_add_i32_e32 v{{[0-9]+}}, vcc, 0x1004, v0
536 ; SICI-DAG: buffer_load_dwordx4 v[0:3], v{{[0-9]+}}, s[0:3], 0 offen ;
537 ; SICI-DAG: buffer_load_dwordx4 v[4:7], v{{[0-9]+}}, s[0:3], 0 offen offset:16 ;
538 ; SICI-DAG: buffer_load_dwordx4 v[8:11], v{{[0-9]+}}, s[0:3], 0 offen offset:32 ;
539 ; SICI-DAG: buffer_load_dwordx4 v[12:15], v{{[0-9]+}}, s[0:3], 0 offen offset:48 ;
540 ; VIGFX9: s_movk_i32 s4, 0xfc0
541 ; VIGFX9-DAG: buffer_load_dwordx4 v[0:3], v{{[0-9]+}}, s[0:3], s4 offen offset:68 ;
542 ; VIGFX9-DAG: buffer_load_dwordx4 v[4:7], v{{[0-9]+}}, s[0:3], s4 offen offset:84 ;
543 ; VIGFX9-DAG: buffer_load_dwordx4 v[8:11], v{{[0-9]+}}, s[0:3], s4 offen offset:100 ;
544 ; VIGFX9-DAG: buffer_load_dwordx4 v[12:15], v{{[0-9]+}}, s[0:3], s4 offen offset:116 ;
545 ; GCN: ; return to shader part epilog
546 define amdgpu_ps <16 x float> @smrd_load_nonconst5(<4 x i32> inreg %rsrc, i32 %off) #0 {
548 %off.2 = add i32 %off, 4100
549 %ld = call <16 x i32> @llvm.amdgcn.s.buffer.load.v16i32(<4 x i32> %rsrc, i32 %off.2, i32 0)
550 %bc = bitcast <16 x i32> %ld to <16 x float>
555 ; GCN-LABEL: {{^}}smrd_load_dwordx2:
556 ; SIVIGFX9: s_buffer_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}}
557 ; CI: s_buffer_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}}
559 define amdgpu_ps void @smrd_load_dwordx2(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, <4 x i32> addrspace(4)* inreg %in, i32 inreg %ncoff) #0 {
561 %tmp22 = load <4 x i32>, <4 x i32> addrspace(4)* %in
562 %s.buffer = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %tmp22, i32 %ncoff, i32 0)
563 %s.buffer.float = bitcast <2 x i32> %s.buffer to <2 x float>
564 %r.1 = extractelement <2 x float> %s.buffer.float, i32 0
565 %r.2 = extractelement <2 x float> %s.buffer.float, i32 1
566 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r.1, float %r.1, float %r.1, float %r.2, i1 true, i1 true) #0
570 ; GCN-LABEL: {{^}}smrd_uniform_loop:
572 ; TODO: we should keep the loop counter in an SGPR
574 ; GCN: v_readfirstlane_b32
575 ; GCN: s_buffer_load_dword
576 define amdgpu_ps float @smrd_uniform_loop(<4 x i32> inreg %desc, i32 %bound) #0 {
581 %counter = phi i32 [ 0, %main_body ], [ %counter.next, %loop ]
582 %sum = phi float [ 0.0, %main_body ], [ %sum.next, %loop ]
583 %offset = shl i32 %counter, 2
584 %v = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %offset, i32 0)
585 %sum.next = fadd float %sum, %v
586 %counter.next = add i32 %counter, 1
587 %cc = icmp uge i32 %counter.next, %bound
588 br i1 %cc, label %exit, label %loop
595 ; GCN-LABEL: {{^}}smrd_uniform_loop2:
596 ; (this test differs from smrd_uniform_loop by the more complex structure of phis,
597 ; which used to confuse the DivergenceAnalysis after structurization)
599 ; TODO: we should keep the loop counter in an SGPR and use an S_BUFFER_LOAD
601 ; GCN: buffer_load_dword
602 define amdgpu_ps float @smrd_uniform_loop2(<4 x i32> inreg %desc, i32 %bound, i32 %bound.a) #0 {
607 %counter = phi i32 [ 0, %main_body ], [ %counter.next, %loop.a ], [ %counter.next, %loop.b ]
608 %sum = phi float [ 0.0, %main_body ], [ %sum.next, %loop.a ], [ %sum.next.b, %loop.b ]
609 %offset = shl i32 %counter, 2
610 %v = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %offset, i32 0)
611 %sum.next = fadd float %sum, %v
612 %counter.next = add i32 %counter, 1
613 %cc = icmp uge i32 %counter.next, %bound
614 br i1 %cc, label %exit, label %loop.a
617 %cc.a = icmp uge i32 %counter.next, %bound.a
618 br i1 %cc, label %loop, label %loop.b
621 %sum.next.b = fadd float %sum.next, 1.0
628 ; This test checks that the load after some control flow with an offset based
629 ; on a divergent shader input is correctly recognized as divergent. This was
630 ; reduced from an actual regression. Yes, the %unused argument matters, as
631 ; well as the fact that %arg4 is a vector.
633 ; GCN-LABEL: {{^}}arg_divergence:
634 ; GCN: buffer_load_dword v0, v0,
635 ; GCN-NEXT: s_waitcnt
636 ; GCN-NEXT: ; return to shader part epilog
637 define amdgpu_cs float @arg_divergence(i32 inreg %unused, <3 x i32> %arg4) #0 {
639 br i1 undef, label %if1, label %endif1
641 if1: ; preds = %main_body
642 store i32 0, i32 addrspace(3)* undef, align 4
645 endif1: ; preds = %if1, %main_body
646 %tmp13 = extractelement <3 x i32> %arg4, i32 0
647 %tmp97 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> undef, i32 %tmp13, i32 0)
651 ; GCN-LABEL: {{^}}s_buffer_load_f32:
652 ; GCN: s_buffer_load_dword s0, s[0:3], s4
653 define amdgpu_ps void @s_buffer_load_f32(<4 x i32> inreg %rsrc, i32 inreg %offset) {
654 %sgpr = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %offset, i32 0)
655 call void asm sideeffect "; use $0", "s"(float %sgpr)
659 ; GCN-LABEL: {{^}}s_buffer_load_v2f32:
660 ; GCN: s_buffer_load_dwordx2 s[0:1], s[0:3], s4
661 define amdgpu_ps void @s_buffer_load_v2f32(<4 x i32> inreg %rsrc, i32 inreg %offset) {
662 %sgpr = call <2 x float> @llvm.amdgcn.s.buffer.load.v2f32(<4 x i32> %rsrc, i32 %offset, i32 0)
663 call void asm sideeffect "; use $0", "s"(<2 x float> %sgpr)
667 ; GCN-LABEL: {{^}}s_buffer_load_v4f32:
668 ; GCN: s_buffer_load_dwordx4 s[0:3], s[0:3], s4
669 define amdgpu_ps void @s_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 inreg %offset) {
670 %sgpr = call <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32> %rsrc, i32 %offset, i32 0)
671 call void asm sideeffect "; use $0", "s"(<4 x float> %sgpr)
675 ; GCN-LABEL: {{^}}s_buffer_load_v8f32:
676 ; GCN: s_buffer_load_dwordx8 s[0:7], s[0:3], s4
677 define amdgpu_ps void @s_buffer_load_v8f32(<4 x i32> inreg %rsrc, i32 inreg %offset) {
678 %sgpr = call <8 x float> @llvm.amdgcn.s.buffer.load.v8f32(<4 x i32> %rsrc, i32 %offset, i32 0)
679 call void asm sideeffect "; use $0", "s"(<8 x float> %sgpr)
683 ; GCN-LABEL: {{^}}s_buffer_load_v16f32:
684 ; GCN: s_buffer_load_dwordx16 s[0:15], s[0:3], s4
685 define amdgpu_ps void @s_buffer_load_v16f32(<4 x i32> inreg %rsrc, i32 inreg %offset) {
686 %sgpr = call <16 x float> @llvm.amdgcn.s.buffer.load.v16f32(<4 x i32> %rsrc, i32 %offset, i32 0)
687 call void asm sideeffect "; use $0", "s"(<16 x float> %sgpr)
691 declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
692 declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #2
693 declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #2
695 declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i32) #1
696 declare <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32>, i32, i32)
697 declare <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32>, i32, i32)
698 declare <8 x i32> @llvm.amdgcn.s.buffer.load.v8i32(<4 x i32>, i32, i32)
699 declare <16 x i32> @llvm.amdgcn.s.buffer.load.v16i32(<4 x i32>, i32, i32)
701 declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32)
702 declare <2 x float> @llvm.amdgcn.s.buffer.load.v2f32(<4 x i32>, i32, i32)
703 declare <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32>, i32, i32)
704 declare <8 x float> @llvm.amdgcn.s.buffer.load.v8f32(<4 x i32>, i32, i32)
705 declare <16 x float> @llvm.amdgcn.s.buffer.load.v16f32(<4 x i32>, i32, i32)
707 attributes #0 = { nounwind }
708 attributes #1 = { nounwind readnone }
709 attributes #2 = { nounwind readnone speculatable }