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[ARM] Cortex-M4 schedule additions
[llvm-complete.git]
/
test
/
Assembler
/
invalid-datalayout7.ll
blob
097227ae6ae88732e218fe99fbea4a31ee9fab90
1
; RUN: not llvm-as < %s 2>&1 | FileCheck %s
2
target datalayout = "p:52"
3
; CHECK: number of bits must be a byte width multiple