[ARM] Cortex-M4 schedule additions

[llvm-complete.git] / test / CodeGen / MIR / X86 / expected-machine-operand.mir

# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s

--- |

  define i32 @foo() {
  entry:
    ret i32 0
  }

...
---
name:            foo
body: |
  bb.0.entry:
    ; CHECK: [[@LINE+1]]:20: expected a machine operand
    $eax = XOR32rr =
    RETQ $eax
...