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HEAD
[ARM] Cortex-M4 schedule additions
[llvm-complete.git]
/
test
/
CodeGen
/
MIR
/
X86
/
unknown-register.mir
blob
37c30f6cb316793ac5d84ccaf4a6c83bded40415
1
# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
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# This test ensures that an error is reported when an unknown register is
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# encountered.
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--- |
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define i32 @foo() {
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entry:
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ret i32 0
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}
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...
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---
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name: foo
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body: |
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bb.0.entry:
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; CHECK: [[@LINE+1]]:5: unknown register name 'xax'
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$xax = MOV32r0
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RETQ $xax
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...