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[ARM] Cortex-M4 schedule additions
[llvm-complete.git]
/
test
/
CodeGen
/
Mips
/
2010-11-09-Mul.ll
blob
dcade3c671db181d76755821b49d55dce101abce
1
; RUN: llc -march=mips < %s | FileCheck %s
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; CHECK: mul $2, $5, $4
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define i32 @mul1(i32 %a, i32 %b) nounwind readnone {
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entry:
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%mul = mul i32 %b, %a
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ret i32 %mul
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}
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; CHECK: mul $2, $5, $4
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define i32 @mul2(i32 %a, i32 %b) nounwind readnone {
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entry:
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%mul = mul nsw i32 %b, %a
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ret i32 %mul
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}