[ARM] Cortex-M4 schedule additions
[llvm-complete.git] / test / tools / llvm-mca / X86 / Broadwell / resources-rdrand.s
blob42e59996bbefcb0ac7ae7ce7db51cb33c26d8ac1
1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=broadwell -instruction-tables < %s | FileCheck %s
4 rdrand %ax
5 rdrand %eax
6 rdrand %rax
8 # CHECK: Instruction Info:
9 # CHECK-NEXT: [1]: #uOps
10 # CHECK-NEXT: [2]: Latency
11 # CHECK-NEXT: [3]: RThroughput
12 # CHECK-NEXT: [4]: MayLoad
13 # CHECK-NEXT: [5]: MayStore
14 # CHECK-NEXT: [6]: HasSideEffects (U)
16 # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
17 # CHECK-NEXT: 5 9 1.00 U rdrandw %ax
18 # CHECK-NEXT: 5 9 1.00 U rdrandl %eax
19 # CHECK-NEXT: 5 9 1.00 U rdrandq %rax
21 # CHECK: Resources:
22 # CHECK-NEXT: [0] - BWDivider
23 # CHECK-NEXT: [1] - BWFPDivider
24 # CHECK-NEXT: [2] - BWPort0
25 # CHECK-NEXT: [3] - BWPort1
26 # CHECK-NEXT: [4] - BWPort2
27 # CHECK-NEXT: [5] - BWPort3
28 # CHECK-NEXT: [6] - BWPort4
29 # CHECK-NEXT: [7] - BWPort5
30 # CHECK-NEXT: [8] - BWPort6
31 # CHECK-NEXT: [9] - BWPort7
33 # CHECK: Resource pressure per iteration:
34 # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9]
35 # CHECK-NEXT: - - 3.75 2.25 1.50 1.50 - 2.25 3.75 -
37 # CHECK: Resource pressure by instruction:
38 # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
39 # CHECK-NEXT: - - 1.25 0.75 0.50 0.50 - 0.75 1.25 - rdrandw %ax
40 # CHECK-NEXT: - - 1.25 0.75 0.50 0.50 - 0.75 1.25 - rdrandl %eax
41 # CHECK-NEXT: - - 1.25 0.75 0.50 0.50 - 0.75 1.25 - rdrandq %rax