[ARM] Cortex-M4 schedule additions
[llvm-complete.git] / test / tools / llvm-mca / X86 / print-imm-hex-2.s
blob35d8f1d43e6c404a98409962b47e08643a0b5cad
1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-views=false -instruction-info < %s | FileCheck %s --check-prefix=DEFAULT
3 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-views=false -instruction-info -print-imm-hex=false < %s | FileCheck %s --check-prefix=DEFAULT
4 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-views=false -instruction-info -print-imm-hex < %s | FileCheck %s --check-prefix=HEX
5 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-views=false -instruction-info -print-imm-hex=true < %s | FileCheck %s --check-prefix=HEX
7 .intel_syntax noprefix
8 shl eax, 8
9 shl eax, 0x8
10 shl eax, 8h
11 shl eax, 1000b
13 # DEFAULT: Instruction Info:
14 # DEFAULT-NEXT: [1]: #uOps
15 # DEFAULT-NEXT: [2]: Latency
16 # DEFAULT-NEXT: [3]: RThroughput
17 # DEFAULT-NEXT: [4]: MayLoad
18 # DEFAULT-NEXT: [5]: MayStore
19 # DEFAULT-NEXT: [6]: HasSideEffects (U)
21 # HEX: Instruction Info:
22 # HEX-NEXT: [1]: #uOps
23 # HEX-NEXT: [2]: Latency
24 # HEX-NEXT: [3]: RThroughput
25 # HEX-NEXT: [4]: MayLoad
26 # HEX-NEXT: [5]: MayStore
27 # HEX-NEXT: [6]: HasSideEffects (U)
29 # DEFAULT: [1] [2] [3] [4] [5] [6] Instructions:
30 # DEFAULT-NEXT: 1 1 0.50 shl eax, 8
31 # DEFAULT-NEXT: 1 1 0.50 shl eax, 8
32 # DEFAULT-NEXT: 1 1 0.50 shl eax, 8
33 # DEFAULT-NEXT: 1 1 0.50 shl eax, 8
35 # HEX: [1] [2] [3] [4] [5] [6] Instructions:
36 # HEX-NEXT: 1 1 0.50 shl eax, 0x8
37 # HEX-NEXT: 1 1 0.50 shl eax, 0x8
38 # HEX-NEXT: 1 1 0.50 shl eax, 0x8
39 # HEX-NEXT: 1 1 0.50 shl eax, 0x8