include/llvm/IR/IntrinsicsHexagon.td

   1 //===- IntrinsicsHexagon.td - Defines Hexagon intrinsics ---*- tablegen -*-===//
   2 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   3 // See https://llvm.org/LICENSE.txt for license information.
   4 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   5 //
   6 //===----------------------------------------------------------------------===//
   7 //
   8 // This file defines all of the Hexagon-specific intrinsics.
   9 //
  10 //===----------------------------------------------------------------------===//
  11
  12 //===----------------------------------------------------------------------===//
  13 // Definitions for all Hexagon intrinsics.
  14 //
  15 // All Hexagon intrinsics start with "llvm.hexagon.".
  16 let TargetPrefix = "hexagon" in {
  17   /// Hexagon_Intrinsic - Base class for the majority of Hexagon intrinsics.
  18   class Hexagon_Intrinsic<string GCCIntSuffix, list<LLVMType> ret_types,
  19                               list<LLVMType> param_types,
  20                               list<IntrinsicProperty> properties>
  21     : GCCBuiltin<!strconcat("__builtin_", GCCIntSuffix)>,
  22       Intrinsic<ret_types, param_types, properties>;
  23
  24   /// Hexagon_NonGCC_Intrinsic - Base class for bitcode convertible Hexagon
  25   /// intrinsics.
  26   class Hexagon_NonGCC_Intrinsic<list<LLVMType> ret_types,
  27                                  list<LLVMType> param_types,
  28                                  list<IntrinsicProperty> properties>
  29     : Intrinsic<ret_types, param_types, properties>;
  30 }
  31
  32 class Hexagon_mem_memmemsi_Intrinsic<string GCCIntSuffix>
  33   : Hexagon_Intrinsic<GCCIntSuffix,
  34                           [llvm_ptr_ty], [llvm_ptr_ty, llvm_ptr_ty,
  35                            llvm_i32_ty],
  36                           [IntrArgMemOnly]>;
  37
  38 class Hexagon_mem_memsisi_Intrinsic<string GCCIntSuffix>
  39   : Hexagon_Intrinsic<GCCIntSuffix,
  40                           [llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty,
  41                            llvm_i32_ty],
  42                           [IntrWriteMem]>;
  43
  44 class Hexagon_mem_memdisi_Intrinsic<string GCCIntSuffix>
  45   : Hexagon_Intrinsic<GCCIntSuffix,
  46                           [llvm_ptr_ty], [llvm_ptr_ty, llvm_i64_ty,
  47                            llvm_i32_ty],
  48                           [IntrWriteMem]>;
  49
  50 class Hexagon_mem_memmemsisi_Intrinsic<string GCCIntSuffix>
  51   : Hexagon_Intrinsic<GCCIntSuffix,
  52                           [llvm_ptr_ty], [llvm_ptr_ty, llvm_ptr_ty,
  53                            llvm_i32_ty, llvm_i32_ty],
  54                           [IntrArgMemOnly]>;
  55
  56 class Hexagon_mem_memsisisi_Intrinsic<string GCCIntSuffix>
  57   : Hexagon_Intrinsic<GCCIntSuffix,
  58                           [llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty,
  59                            llvm_i32_ty, llvm_i32_ty],
  60                           [IntrWriteMem]>;
  61
  62 class Hexagon_mem_memdisisi_Intrinsic<string GCCIntSuffix>
  63   : Hexagon_Intrinsic<GCCIntSuffix,
  64                           [llvm_ptr_ty], [llvm_ptr_ty, llvm_i64_ty,
  65                            llvm_i32_ty, llvm_i32_ty],
  66                           [IntrWriteMem]>;
  67
  68 //
  69 // BUILTIN_INFO_NONCONST(circ_ldd,PTR_ftype_PTRPTRSISI,4)
  70 //
  71 def int_hexagon_circ_ldd :
  72 Hexagon_mem_memmemsisi_Intrinsic<"circ_ldd">;
  73 //
  74 // BUILTIN_INFO_NONCONST(circ_ldw,PTR_ftype_PTRPTRSISI,4)
  75 //
  76 def int_hexagon_circ_ldw :
  77 Hexagon_mem_memmemsisi_Intrinsic<"circ_ldw">;
  78 //
  79 // BUILTIN_INFO_NONCONST(circ_ldh,PTR_ftype_PTRPTRSISI,4)
  80 //
  81 def int_hexagon_circ_ldh :
  82 Hexagon_mem_memmemsisi_Intrinsic<"circ_ldh">;
  83 //
  84 // BUILTIN_INFO_NONCONST(circ_lduh,PTR_ftype_PTRPTRSISI,4)
  85 //
  86 def int_hexagon_circ_lduh :
  87 Hexagon_mem_memmemsisi_Intrinsic<"circ_lduh">;
  88 //
  89 // BUILTIN_INFO_NONCONST(circ_ldb,PTR_ftype_PTRPTRSISI,4)
  90 //
  91 def int_hexagon_circ_ldb :
  92 Hexagon_mem_memmemsisi_Intrinsic<"circ_ldb">;
  93 //
  94 // BUILTIN_INFO_NONCONST(circ_ldub,PTR_ftype_PTRPTRSISI,4)
  95 //
  96 def int_hexagon_circ_ldub :
  97 Hexagon_mem_memmemsisi_Intrinsic<"circ_ldub">;
  98
  99 //
 100 // BUILTIN_INFO_NONCONST(circ_std,PTR_ftype_PTRDISISI,4)
 101 //
 102 def int_hexagon_circ_std :
 103 Hexagon_mem_memdisisi_Intrinsic<"circ_std">;
 104 //
 105 // BUILTIN_INFO_NONCONST(circ_stw,PTR_ftype_PTRSISISI,4)
 106 //
 107 def int_hexagon_circ_stw :
 108 Hexagon_mem_memsisisi_Intrinsic<"circ_stw">;
 109 //
 110 // BUILTIN_INFO_NONCONST(circ_sth,PTR_ftype_PTRSISISI,4)
 111 //
 112 def int_hexagon_circ_sth :
 113 Hexagon_mem_memsisisi_Intrinsic<"circ_sth">;
 114 //
 115 // BUILTIN_INFO_NONCONST(circ_sthhi,PTR_ftype_PTRSISISI,4)
 116 //
 117 def int_hexagon_circ_sthhi :
 118 Hexagon_mem_memsisisi_Intrinsic<"circ_sthhi">;
 119 //
 120 // BUILTIN_INFO_NONCONST(circ_stb,PTR_ftype_PTRSISISI,4)
 121 //
 122 def int_hexagon_circ_stb :
 123 Hexagon_mem_memsisisi_Intrinsic<"circ_stb">;
 124
 125 //
 126 // BUILTIN_INFO(HEXAGON.dcfetch_A,v_ftype_DI*,1)
 127 //
 128 def int_hexagon_prefetch :
 129 Hexagon_Intrinsic<"HEXAGON_prefetch", [], [llvm_ptr_ty], []>;
 130 def int_hexagon_Y2_dccleana :
 131 Hexagon_Intrinsic<"HEXAGON_Y2_dccleana", [], [llvm_ptr_ty], []>;
 132 def int_hexagon_Y2_dccleaninva :
 133 Hexagon_Intrinsic<"HEXAGON_Y2_dccleaninva", [], [llvm_ptr_ty], []>;
 134 def int_hexagon_Y2_dcinva :
 135 Hexagon_Intrinsic<"HEXAGON_Y2_dcinva", [], [llvm_ptr_ty], []>;
 136 def int_hexagon_Y2_dczeroa :
 137 Hexagon_Intrinsic<"HEXAGON_Y2_dczeroa", [], [llvm_ptr_ty],
 138       [IntrWriteMem, IntrArgMemOnly, IntrHasSideEffects]>;
 139 def int_hexagon_Y4_l2fetch :
 140 Hexagon_Intrinsic<"HEXAGON_Y4_l2fetch", [], [llvm_ptr_ty, llvm_i32_ty], []>;
 141 def int_hexagon_Y5_l2fetch :
 142 Hexagon_Intrinsic<"HEXAGON_Y5_l2fetch", [], [llvm_ptr_ty, llvm_i64_ty], []>;
 143
 144 def llvm_ptr32_ty : LLVMPointerType<llvm_i32_ty>;
 145 def llvm_ptr64_ty : LLVMPointerType<llvm_i64_ty>;
 146
 147 // Mark locked loads as read/write to prevent any accidental reordering.
 148 def int_hexagon_L2_loadw_locked :
 149 Hexagon_Intrinsic<"HEXAGON_L2_loadw_locked", [llvm_i32_ty], [llvm_ptr32_ty],
 150       [IntrArgMemOnly, NoCapture<0>]>;
 151 def int_hexagon_L4_loadd_locked :
 152 Hexagon_Intrinsic<"HEXAGON_L4_loadd_locked", [llvm_i64_ty], [llvm_ptr64_ty],
 153       [IntrArgMemOnly, NoCapture<0>]>;
 154
 155 def int_hexagon_S2_storew_locked :
 156 Hexagon_Intrinsic<"HEXAGON_S2_storew_locked", [llvm_i32_ty],
 157       [llvm_ptr32_ty, llvm_i32_ty], [IntrArgMemOnly, NoCapture<0>]>;
 158 def int_hexagon_S4_stored_locked :
 159 Hexagon_Intrinsic<"HEXAGON_S4_stored_locked", [llvm_i32_ty],
 160       [llvm_ptr64_ty, llvm_i64_ty], [IntrArgMemOnly, NoCapture<0>]>;
 161
 162 def int_hexagon_vmemcpy : Hexagon_Intrinsic<"hexagon_vmemcpy",
 163     [], [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty],
 164     [IntrArgMemOnly, NoCapture<0>, NoCapture<1>, WriteOnly<0>, ReadOnly<1>]>;
 165
 166 def int_hexagon_vmemset : Hexagon_Intrinsic<"hexagon_vmemset",
 167     [], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
 168     [IntrArgMemOnly, NoCapture<0>, WriteOnly<0>]>;
 169
 170 multiclass Hexagon_custom_circ_ld_Intrinsic<LLVMType ElTy> {
 171   def NAME#_pci : Hexagon_NonGCC_Intrinsic<
 172     [ElTy, llvm_ptr_ty],
 173     [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty],
 174     [IntrArgMemOnly, NoCapture<3>]>;
 175   def NAME#_pcr : Hexagon_NonGCC_Intrinsic<
 176     [ElTy, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_ptr_ty],
 177     [IntrArgMemOnly, NoCapture<2>]>;
 178 }
 179
 180 defm int_hexagon_L2_loadrub : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>;
 181 defm int_hexagon_L2_loadrb : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>;
 182 defm int_hexagon_L2_loadruh : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>;
 183 defm int_hexagon_L2_loadrh : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>;
 184 defm int_hexagon_L2_loadri : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>;
 185 defm int_hexagon_L2_loadrd : Hexagon_custom_circ_ld_Intrinsic<llvm_i64_ty>;
 186
 187 multiclass Hexagon_custom_circ_st_Intrinsic<LLVMType ElTy> {
 188   def NAME#_pci : Hexagon_NonGCC_Intrinsic<
 189     [llvm_ptr_ty],
 190     [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, ElTy, llvm_ptr_ty],
 191     [IntrArgMemOnly, NoCapture<4>]>;
 192   def NAME#_pcr : Hexagon_NonGCC_Intrinsic<
 193     [llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, ElTy, llvm_ptr_ty],
 194     [IntrArgMemOnly, NoCapture<3>]>;
 195 }
 196
 197 defm int_hexagon_S2_storerb : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>;
 198 defm int_hexagon_S2_storerh : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>;
 199 defm int_hexagon_S2_storerf : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>;
 200 defm int_hexagon_S2_storeri : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>;
 201 defm int_hexagon_S2_storerd : Hexagon_custom_circ_st_Intrinsic<llvm_i64_ty>;
 202
 203 // The front-end emits the intrinsic call with only two arguments. The third
 204 // argument from the builtin is already used by front-end to write to memory
 205 // by generating a store.
 206 class Hexagon_custom_brev_ld_Intrinsic<LLVMType ElTy>
 207  : Hexagon_NonGCC_Intrinsic<
 208     [ElTy, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty],
 209     [IntrReadMem]>;
 210
 211 def int_hexagon_L2_loadrub_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
 212 def int_hexagon_L2_loadrb_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
 213 def int_hexagon_L2_loadruh_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
 214 def int_hexagon_L2_loadrh_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
 215 def int_hexagon_L2_loadri_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
 216 def int_hexagon_L2_loadrd_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i64_ty>;
 217
 218 def int_hexagon_S2_storerb_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_stb">;
 219 def int_hexagon_S2_storerh_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_sth">;
 220 def int_hexagon_S2_storerf_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_sthhi">;
 221 def int_hexagon_S2_storeri_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_stw">;
 222 def int_hexagon_S2_storerd_pbr : Hexagon_mem_memdisi_Intrinsic<"brev_std">;
 223
 224 //
 225 // Masked vector stores
 226 //
 227
 228 //
 229 // Hexagon_vv64ivmemv512_Intrinsic<string GCCIntSuffix>
 230 // tag: V6_vS32b_qpred_ai
 231 class Hexagon_vv64ivmemv512_Intrinsic<string GCCIntSuffix>
 232  : Hexagon_Intrinsic<GCCIntSuffix,
 233                           [], [llvm_v512i1_ty,llvm_ptr_ty,llvm_v16i32_ty],
 234                           [IntrArgMemOnly]>;
 235
 236 //
 237 // Hexagon_vv128ivmemv1024_Intrinsic<string GCCIntSuffix>
 238 // tag: V6_vS32b_qpred_ai_128B
 239 class Hexagon_vv128ivmemv1024_Intrinsic<string GCCIntSuffix>
 240  : Hexagon_Intrinsic<GCCIntSuffix,
 241                           [], [llvm_v1024i1_ty,llvm_ptr_ty,llvm_v32i32_ty],
 242                           [IntrArgMemOnly]>;
 243
 244 def int_hexagon_V6_vS32b_qpred_ai :
 245 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai">;
 246
 247 def int_hexagon_V6_vS32b_nqpred_ai :
 248 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai">;
 249
 250 def int_hexagon_V6_vS32b_nt_qpred_ai :
 251 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai">;
 252
 253 def int_hexagon_V6_vS32b_nt_nqpred_ai :
 254 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai">;
 255
 256 def int_hexagon_V6_vS32b_qpred_ai_128B :
 257 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai_128B">;
 258
 259 def int_hexagon_V6_vS32b_nqpred_ai_128B :
 260 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai_128B">;
 261
 262 def int_hexagon_V6_vS32b_nt_qpred_ai_128B :
 263 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai_128B">;
 264
 265 def int_hexagon_V6_vS32b_nt_nqpred_ai_128B :
 266 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai_128B">;
 267
 268 def int_hexagon_V6_vmaskedstoreq :
 269 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstoreq">;
 270
 271 def int_hexagon_V6_vmaskedstorenq :
 272 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstorenq">;
 273
 274 def int_hexagon_V6_vmaskedstorentq :
 275 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstorentq">;
 276
 277 def int_hexagon_V6_vmaskedstorentnq :
 278 Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstorentnq">;
 279
 280 def int_hexagon_V6_vmaskedstoreq_128B :
 281 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstoreq_128B">;
 282
 283 def int_hexagon_V6_vmaskedstorenq_128B :
 284 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstorenq_128B">;
 285
 286 def int_hexagon_V6_vmaskedstorentq_128B :
 287 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstorentq_128B">;
 288
 289 def int_hexagon_V6_vmaskedstorentnq_128B :
 290 Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstorentnq_128B">;
 291
 292 class Hexagon_V65_vvmemiiv512_Intrinsic<string GCCIntSuffix>
 293  : Hexagon_Intrinsic<GCCIntSuffix,
 294                           [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,
 295                                llvm_v16i32_ty],
 296                           [IntrArgMemOnly]>;
 297
 298 class Hexagon_V65_vvmemiiv1024_Intrinsic<string GCCIntSuffix>
 299  : Hexagon_Intrinsic<GCCIntSuffix,
 300                           [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,
 301                                llvm_v32i32_ty],
 302                           [IntrArgMemOnly]>;
 303
 304 class Hexagon_V65_vvmemiiv2048_Intrinsic<string GCCIntSuffix>
 305  : Hexagon_Intrinsic<GCCIntSuffix,
 306                           [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,
 307                                llvm_v64i32_ty],
 308                           [IntrArgMemOnly]>;
 309
 310 class Hexagon_V65_vvmemv64iiiv512_Intrinsic<string GCCIntSuffix>
 311  : Hexagon_Intrinsic<GCCIntSuffix,
 312                           [], [llvm_ptr_ty,llvm_v512i1_ty,llvm_i32_ty,
 313                                llvm_i32_ty,llvm_v16i32_ty],
 314                           [IntrArgMemOnly]>;
 315
 316 class Hexagon_V65_vvmemv128iiiv1024_Intrinsic<string GCCIntSuffix>
 317  : Hexagon_Intrinsic<GCCIntSuffix,
 318                           [], [llvm_ptr_ty,llvm_v1024i1_ty,llvm_i32_ty,
 319                                llvm_i32_ty,llvm_v32i32_ty],
 320                           [IntrArgMemOnly]>;
 321
 322 class Hexagon_V65_vvmemv64iiiv1024_Intrinsic<string GCCIntSuffix>
 323  : Hexagon_Intrinsic<GCCIntSuffix,
 324                           [], [llvm_ptr_ty,llvm_v512i1_ty,llvm_i32_ty,
 325                                llvm_i32_ty,llvm_v32i32_ty],
 326                           [IntrArgMemOnly]>;
 327
 328 class Hexagon_V65_vvmemv128iiiv2048_Intrinsic<string GCCIntSuffix>
 329  : Hexagon_Intrinsic<GCCIntSuffix,
 330                           [], [llvm_ptr_ty,llvm_v1024i1_ty,llvm_i32_ty,
 331                                llvm_i32_ty,llvm_v64i32_ty],
 332                           [IntrArgMemOnly]>;
 333
 334 def int_hexagon_V6_vgathermw :
 335 Hexagon_V65_vvmemiiv512_Intrinsic<"HEXAGON_V6_vgathermw">;
 336
 337 def int_hexagon_V6_vgathermw_128B :
 338 Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermw_128B">;
 339
 340 def int_hexagon_V6_vgathermh :
 341 Hexagon_V65_vvmemiiv512_Intrinsic<"HEXAGON_V6_vgathermh">;
 342
 343 def int_hexagon_V6_vgathermh_128B :
 344 Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermh_128B">;
 345
 346 def int_hexagon_V6_vgathermhw :
 347 Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermhw">;
 348
 349 def int_hexagon_V6_vgathermhw_128B :
 350 Hexagon_V65_vvmemiiv2048_Intrinsic<"HEXAGON_V6_vgathermhw_128B">;
 351
 352 def int_hexagon_V6_vgathermwq :
 353 Hexagon_V65_vvmemv64iiiv512_Intrinsic<"HEXAGON_V6_vgathermwq">;
 354
 355 def int_hexagon_V6_vgathermwq_128B :
 356 Hexagon_V65_vvmemv128iiiv1024_Intrinsic<"HEXAGON_V6_vgathermwq_128B">;
 357
 358 def int_hexagon_V6_vgathermhq :
 359 Hexagon_V65_vvmemv64iiiv512_Intrinsic<"HEXAGON_V6_vgathermhq">;
 360
 361 def int_hexagon_V6_vgathermhq_128B :
 362 Hexagon_V65_vvmemv128iiiv1024_Intrinsic<"HEXAGON_V6_vgathermhq_128B">;
 363
 364 def int_hexagon_V6_vgathermhwq :
 365 Hexagon_V65_vvmemv64iiiv1024_Intrinsic<"HEXAGON_V6_vgathermhwq">;
 366
 367 def int_hexagon_V6_vgathermhwq_128B :
 368 Hexagon_V65_vvmemv128iiiv2048_Intrinsic<"HEXAGON_V6_vgathermhwq_128B">;
 369
 370 class Hexagon_V65_viiv512v512_Intrinsic<string GCCIntSuffix>
 371  : Hexagon_Intrinsic<GCCIntSuffix,
 372                           [], [llvm_i32_ty,llvm_i32_ty,
 373                                            llvm_v16i32_ty,llvm_v16i32_ty],
 374                           [IntrWriteMem]>;
 375
 376 class Hexagon_V65_viiv1024v1024_Intrinsic<string GCCIntSuffix>
 377  : Hexagon_Intrinsic<GCCIntSuffix,
 378                           [], [llvm_i32_ty,llvm_i32_ty,
 379                                            llvm_v32i32_ty,llvm_v32i32_ty],
 380                           [IntrWriteMem]>;
 381
 382 class Hexagon_V65_vv64iiiv512v512_Intrinsic<string GCCIntSuffix>
 383  : Hexagon_Intrinsic<GCCIntSuffix,
 384                           [], [llvm_v512i1_ty,llvm_i32_ty,
 385                                            llvm_i32_ty,llvm_v16i32_ty,
 386                                            llvm_v16i32_ty],
 387                           [IntrWriteMem]>;
 388
 389 class Hexagon_V65_vv128iiiv1024v1024_Intrinsic<string GCCIntSuffix>
 390  : Hexagon_Intrinsic<GCCIntSuffix,
 391                           [], [llvm_v1024i1_ty,llvm_i32_ty,
 392                                            llvm_i32_ty,llvm_v32i32_ty,
 393                                            llvm_v32i32_ty],
 394                           [IntrWriteMem]>;
 395
 396 class Hexagon_V65_viiv1024v512_Intrinsic<string GCCIntSuffix>
 397  : Hexagon_Intrinsic<GCCIntSuffix,
 398                           [], [llvm_i32_ty,llvm_i32_ty,
 399                                            llvm_v32i32_ty,llvm_v16i32_ty],
 400                           [IntrWriteMem]>;
 401
 402 class Hexagon_V65_viiv2048v1024_Intrinsic<string GCCIntSuffix>
 403  : Hexagon_Intrinsic<GCCIntSuffix,
 404                           [], [llvm_i32_ty,llvm_i32_ty,
 405                                            llvm_v64i32_ty,llvm_v32i32_ty],
 406                           [IntrWriteMem]>;
 407
 408 class Hexagon_V65_vv64iiiv1024v512_Intrinsic<string GCCIntSuffix>
 409  : Hexagon_Intrinsic<GCCIntSuffix,
 410                           [], [llvm_v512i1_ty,llvm_i32_ty,
 411                                            llvm_i32_ty,llvm_v32i32_ty,
 412                                            llvm_v16i32_ty],
 413                           [IntrWriteMem]>;
 414
 415 class Hexagon_V65_vv128iiiv2048v1024_Intrinsic<string GCCIntSuffix>
 416  : Hexagon_Intrinsic<GCCIntSuffix,
 417                           [], [llvm_v1024i1_ty,llvm_i32_ty,
 418                                            llvm_i32_ty,llvm_v64i32_ty,
 419                                            llvm_v32i32_ty],
 420                           [IntrWriteMem]>;
 421
 422 class Hexagon_V65_v2048_Intrinsic<string GCCIntSuffix>
 423  : Hexagon_Intrinsic<GCCIntSuffix,
 424                           [llvm_v64i32_ty], [],
 425                           [IntrNoMem]>;
 426
 427 //
 428 // BUILTIN_INFO(HEXAGON.V6_vscattermw,v_ftype_SISIVIVI,4)
 429 // tag : V6_vscattermw
 430 def int_hexagon_V6_vscattermw :
 431 Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermw">;
 432
 433 //
 434 // BUILTIN_INFO(HEXAGON.V6_vscattermw_128B,v_ftype_SISIVIVI,4)
 435 // tag : V6_vscattermw_128B
 436 def int_hexagon_V6_vscattermw_128B :
 437 Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermw_128B">;
 438
 439 //
 440 // BUILTIN_INFO(HEXAGON.V6_vscattermh,v_ftype_SISIVIVI,4)
 441 // tag : V6_vscattermh
 442 def int_hexagon_V6_vscattermh :
 443 Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermh">;
 444
 445 //
 446 // BUILTIN_INFO(HEXAGON.V6_vscattermh_128B,v_ftype_SISIVIVI,4)
 447 // tag : V6_vscattermh_128B
 448 def int_hexagon_V6_vscattermh_128B :
 449 Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermh_128B">;
 450
 451 //
 452 // BUILTIN_INFO(HEXAGON.V6_vscattermw_add,v_ftype_SISIVIVI,4)
 453 // tag : V6_vscattermw_add
 454 def int_hexagon_V6_vscattermw_add :
 455 Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermw_add">;
 456
 457 //
 458 // BUILTIN_INFO(HEXAGON.V6_vscattermw_add_128B,v_ftype_SISIVIVI,4)
 459 // tag : V6_vscattermw_add_128B
 460 def int_hexagon_V6_vscattermw_add_128B :
 461 Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermw_add_128B">;
 462
 463 //
 464 // BUILTIN_INFO(HEXAGON.V6_vscattermh_add,v_ftype_SISIVIVI,4)
 465 // tag : V6_vscattermh_add
 466 def int_hexagon_V6_vscattermh_add :
 467 Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermh_add">;
 468
 469 //
 470 // BUILTIN_INFO(HEXAGON.V6_vscattermh_add_128B,v_ftype_SISIVIVI,4)
 471 // tag : V6_vscattermh_add_128B
 472 def int_hexagon_V6_vscattermh_add_128B :
 473 Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermh_add_128B">;
 474
 475 //
 476 // BUILTIN_INFO(HEXAGON.V6_vscattermwq,v_ftype_QVSISIVIVI,5)
 477 // tag : V6_vscattermwq
 478 def int_hexagon_V6_vscattermwq :
 479 Hexagon_V65_vv64iiiv512v512_Intrinsic<"HEXAGON_V6_vscattermwq">;
 480
 481 //
 482 // BUILTIN_INFO(HEXAGON.V6_vscattermwq_128B,v_ftype_QVSISIVIVI,5)
 483 // tag : V6_vscattermwq_128B
 484 def int_hexagon_V6_vscattermwq_128B :
 485 Hexagon_V65_vv128iiiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermwq_128B">;
 486
 487 //
 488 // BUILTIN_INFO(HEXAGON.V6_vscattermhq,v_ftype_QVSISIVIVI,5)
 489 // tag : V6_vscattermhq
 490 def int_hexagon_V6_vscattermhq :
 491 Hexagon_V65_vv64iiiv512v512_Intrinsic<"HEXAGON_V6_vscattermhq">;
 492
 493 //
 494 // BUILTIN_INFO(HEXAGON.V6_vscattermhq_128B,v_ftype_QVSISIVIVI,5)
 495 // tag : V6_vscattermhq_128B
 496 def int_hexagon_V6_vscattermhq_128B :
 497 Hexagon_V65_vv128iiiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermhq_128B">;
 498
 499 //
 500 // BUILTIN_INFO(HEXAGON.V6_vscattermhw,v_ftype_SISIVDVI,4)
 501 // tag : V6_vscattermhw
 502 def int_hexagon_V6_vscattermhw :
 503 Hexagon_V65_viiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhw">;
 504
 505 //
 506 // BUILTIN_INFO(HEXAGON.V6_vscattermhw_128B,v_ftype_SISIVDVI,4)
 507 // tag : V6_vscattermhw_128B
 508 def int_hexagon_V6_vscattermhw_128B :
 509 Hexagon_V65_viiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhw_128B">;
 510
 511 //
 512 // BUILTIN_INFO(HEXAGON.V6_vscattermhwq,v_ftype_QVSISIVDVI,5)
 513 // tag : V6_vscattermhwq
 514 def int_hexagon_V6_vscattermhwq :
 515 Hexagon_V65_vv64iiiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhwq">;
 516
 517 //
 518 // BUILTIN_INFO(HEXAGON.V6_vscattermhwq_128B,v_ftype_QVSISIVDVI,5)
 519 // tag : V6_vscattermhwq_128B
 520 def int_hexagon_V6_vscattermhwq_128B :
 521 Hexagon_V65_vv128iiiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhwq_128B">;
 522
 523 //
 524 // BUILTIN_INFO(HEXAGON.V6_vscattermhw_add,v_ftype_SISIVDVI,4)
 525 // tag : V6_vscattermhw_add
 526 def int_hexagon_V6_vscattermhw_add :
 527 Hexagon_V65_viiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhw_add">;
 528
 529 //
 530 // BUILTIN_INFO(HEXAGON.V6_vscattermhw_add_128B,v_ftype_SISIVDVI,4)
 531 // tag : V6_vscattermhw_add_128B
 532 def int_hexagon_V6_vscattermhw_add_128B :
 533 Hexagon_V65_viiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhw_add_128B">;
 534
 535 // Auto-generated intrinsics
 536
 537 // tag : S2_vsatwh
 538 class Hexagon_i32_i64_Intrinsic<string GCCIntSuffix>
 539   : Hexagon_Intrinsic<GCCIntSuffix,
 540        [llvm_i32_ty], [llvm_i64_ty],
 541        [IntrNoMem]>;
 542
 543 // tag : V6_vrmpybusv
 544 class Hexagon_v16i32_v16i32v16i32_Intrinsic<string GCCIntSuffix>
 545   : Hexagon_Intrinsic<GCCIntSuffix,
 546        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty],
 547        [IntrNoMem]>;
 548
 549 // tag : V6_vrmpybusv
 550 class Hexagon_v32i32_v32i32v32i32_Intrinsic<string GCCIntSuffix>
 551   : Hexagon_Intrinsic<GCCIntSuffix,
 552        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty],
 553        [IntrNoMem]>;
 554
 555 // tag : V6_vaslw_acc
 556 class Hexagon_v16i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix>
 557   : Hexagon_Intrinsic<GCCIntSuffix,
 558        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
 559        [IntrNoMem]>;
 560
 561 // tag : V6_vaslw_acc
 562 class Hexagon_v32i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix>
 563   : Hexagon_Intrinsic<GCCIntSuffix,
 564        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
 565        [IntrNoMem]>;
 566
 567 // tag : V6_vmux
 568 class Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<string GCCIntSuffix>
 569   : Hexagon_Intrinsic<GCCIntSuffix,
 570        [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty],
 571        [IntrNoMem]>;
 572
 573 // tag : V6_vmux
 574 class Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<string GCCIntSuffix>
 575   : Hexagon_Intrinsic<GCCIntSuffix,
 576        [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty],
 577        [IntrNoMem]>;
 578
 579 // tag : S2_tableidxd_goodsyntax
 580 class Hexagon_i32_i32i32i32i32_Intrinsic<string GCCIntSuffix>
 581   : Hexagon_Intrinsic<GCCIntSuffix,
 582        [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],
 583        [IntrNoMem]>;
 584
 585 // tag : V6_vandnqrt_acc
 586 class Hexagon_v16i32_v16i32v512i1i32_Intrinsic<string GCCIntSuffix>
 587   : Hexagon_Intrinsic<GCCIntSuffix,
 588        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v512i1_ty,llvm_i32_ty],
 589        [IntrNoMem]>;
 590
 591 // tag : V6_vandnqrt_acc
 592 class Hexagon_v32i32_v32i32v1024i1i32_Intrinsic<string GCCIntSuffix>
 593   : Hexagon_Intrinsic<GCCIntSuffix,
 594        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v1024i1_ty,llvm_i32_ty],
 595        [IntrNoMem]>;
 596
 597 // tag : V6_vrmpybusi
 598 class Hexagon_v32i32_v32i32i32i32_Intrinsic<string GCCIntSuffix>
 599   : Hexagon_Intrinsic<GCCIntSuffix,
 600        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty],
 601        [IntrNoMem]>;
 602
 603 // tag : V6_vrmpybusi
 604 class Hexagon_v64i32_v64i32i32i32_Intrinsic<string GCCIntSuffix>
 605   : Hexagon_Intrinsic<GCCIntSuffix,
 606        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty],
 607        [IntrNoMem]>;
 608
 609 // tag : V6_vsubb_dv
 610 class Hexagon_v64i32_v64i32v64i32_Intrinsic<string GCCIntSuffix>
 611   : Hexagon_Intrinsic<GCCIntSuffix,
 612        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty],
 613        [IntrNoMem]>;
 614
 615 // tag : M2_mpysu_up
 616 class Hexagon_i32_i32i32_Intrinsic<string GCCIntSuffix>
 617   : Hexagon_Intrinsic<GCCIntSuffix,
 618        [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty],
 619        [IntrNoMem]>;
 620
 621 // tag : M2_mpyud_acc_ll_s0
 622 class Hexagon_i64_i64i32i32_Intrinsic<string GCCIntSuffix>
 623   : Hexagon_Intrinsic<GCCIntSuffix,
 624        [llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty,llvm_i32_ty],
 625        [IntrNoMem]>;
 626
 627 // tag : S2_lsr_i_r_nac
 628 class Hexagon_i32_i32i32i32_Intrinsic<string GCCIntSuffix>
 629   : Hexagon_Intrinsic<GCCIntSuffix,
 630        [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],
 631        [IntrNoMem]>;
 632
 633 // tag : M2_cmpysc_s0
 634 class Hexagon_i64_i32i32_Intrinsic<string GCCIntSuffix>
 635   : Hexagon_Intrinsic<GCCIntSuffix,
 636        [llvm_i64_ty], [llvm_i32_ty,llvm_i32_ty],
 637        [IntrNoMem]>;
 638
 639 // tag : V6_lo
 640 class Hexagon_v16i32_v32i32_Intrinsic<string GCCIntSuffix>
 641   : Hexagon_Intrinsic<GCCIntSuffix,
 642        [llvm_v16i32_ty], [llvm_v32i32_ty],
 643        [IntrNoMem]>;
 644
 645 // tag : V6_lo
 646 class Hexagon_v32i32_v64i32_Intrinsic<string GCCIntSuffix>
 647   : Hexagon_Intrinsic<GCCIntSuffix,
 648        [llvm_v32i32_ty], [llvm_v64i32_ty],
 649        [IntrNoMem]>;
 650
 651 // tag : S2_shuffoh
 652 class Hexagon_i64_i64i64_Intrinsic<string GCCIntSuffix>
 653   : Hexagon_Intrinsic<GCCIntSuffix,
 654        [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty],
 655        [IntrNoMem]>;
 656
 657 // tag : F2_sfmax
 658 class Hexagon_float_floatfloat_Intrinsic<string GCCIntSuffix>
 659   : Hexagon_Intrinsic<GCCIntSuffix,
 660        [llvm_float_ty], [llvm_float_ty,llvm_float_ty],
 661        [IntrNoMem, Throws]>;
 662
 663 // tag : A2_vabswsat
 664 class Hexagon_i64_i64_Intrinsic<string GCCIntSuffix>
 665   : Hexagon_Intrinsic<GCCIntSuffix,
 666        [llvm_i64_ty], [llvm_i64_ty],
 667        [IntrNoMem]>;
 668
 669 // tag :
 670 class Hexagon_v32i32_v32i32_Intrinsic<string GCCIntSuffix>
 671   : Hexagon_Intrinsic<GCCIntSuffix,
 672        [llvm_v32i32_ty], [llvm_v32i32_ty],
 673        [IntrNoMem]>;
 674
 675 // tag : V6_ldnp0
 676 class Hexagon_v16i32_i32i32_Intrinsic<string GCCIntSuffix>
 677   : Hexagon_Intrinsic<GCCIntSuffix,
 678        [llvm_v16i32_ty], [llvm_i32_ty,llvm_i32_ty],
 679        [IntrNoMem]>;
 680
 681 // tag : V6_ldnp0
 682 class Hexagon_v32i32_i32i32_Intrinsic<string GCCIntSuffix>
 683   : Hexagon_Intrinsic<GCCIntSuffix,
 684        [llvm_v32i32_ty], [llvm_i32_ty,llvm_i32_ty],
 685        [IntrNoMem]>;
 686
 687 // tag : V6_vdmpyhb
 688 class Hexagon_v16i32_v16i32i32_Intrinsic<string GCCIntSuffix>
 689   : Hexagon_Intrinsic<GCCIntSuffix,
 690        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i32_ty],
 691        [IntrNoMem]>;
 692
 693 // tag : V6_vdmpyhb
 694 class Hexagon_v32i32_v32i32i32_Intrinsic<string GCCIntSuffix>
 695   : Hexagon_Intrinsic<GCCIntSuffix,
 696        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
 697        [IntrNoMem]>;
 698
 699 // tag : A4_vcmphgti
 700 class Hexagon_i32_i64i32_Intrinsic<string GCCIntSuffix>
 701   : Hexagon_Intrinsic<GCCIntSuffix,
 702        [llvm_i32_ty], [llvm_i64_ty,llvm_i32_ty],
 703        [IntrNoMem]>;
 704
 705 // tag :
 706 class Hexagon_v32i32_v16i32i32_Intrinsic<string GCCIntSuffix>
 707   : Hexagon_Intrinsic<GCCIntSuffix,
 708        [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i32_ty],
 709        [IntrNoMem]>;
 710
 711 // tag : S6_rol_i_p_or
 712 class Hexagon_i64_i64i64i32_Intrinsic<string GCCIntSuffix>
 713   : Hexagon_Intrinsic<GCCIntSuffix,
 714        [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty],
 715        [IntrNoMem]>;
 716
 717 // tag : V6_vgtuh_and
 718 class Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<string GCCIntSuffix>
 719   : Hexagon_Intrinsic<GCCIntSuffix,
 720        [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty],
 721        [IntrNoMem]>;
 722
 723 // tag : V6_vgtuh_and
 724 class Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<string GCCIntSuffix>
 725   : Hexagon_Intrinsic<GCCIntSuffix,
 726        [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty],
 727        [IntrNoMem]>;
 728
 729 // tag : A2_abssat
 730 class Hexagon_i32_i32_Intrinsic<string GCCIntSuffix>
 731   : Hexagon_Intrinsic<GCCIntSuffix,
 732        [llvm_i32_ty], [llvm_i32_ty],
 733        [IntrNoMem]>;
 734
 735 // tag : A2_vcmpwgtu
 736 class Hexagon_i32_i64i64_Intrinsic<string GCCIntSuffix>
 737   : Hexagon_Intrinsic<GCCIntSuffix,
 738        [llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty],
 739        [IntrNoMem]>;
 740
 741 // tag : V6_vtmpybus_acc
 742 class Hexagon_v64i32_v64i32v64i32i32_Intrinsic<string GCCIntSuffix>
 743   : Hexagon_Intrinsic<GCCIntSuffix,
 744        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty],
 745        [IntrNoMem]>;
 746
 747 // tag : F2_conv_df2uw_chop
 748 class Hexagon_i32_double_Intrinsic<string GCCIntSuffix>
 749   : Hexagon_Intrinsic<GCCIntSuffix,
 750        [llvm_i32_ty], [llvm_double_ty],
 751        [IntrNoMem]>;
 752
 753 // tag : V6_pred_or
 754 class Hexagon_v512i1_v512i1v512i1_Intrinsic<string GCCIntSuffix>
 755   : Hexagon_Intrinsic<GCCIntSuffix,
 756        [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v512i1_ty],
 757        [IntrNoMem]>;
 758
 759 // tag : V6_pred_or
 760 class Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<string GCCIntSuffix>
 761   : Hexagon_Intrinsic<GCCIntSuffix,
 762        [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v1024i1_ty],
 763        [IntrNoMem]>;
 764
 765 // tag : S2_asr_i_p_rnd_goodsyntax
 766 class Hexagon_i64_i64i32_Intrinsic<string GCCIntSuffix>
 767   : Hexagon_Intrinsic<GCCIntSuffix,
 768        [llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty],
 769        [IntrNoMem]>;
 770
 771 // tag : F2_conv_w2df
 772 class Hexagon_double_i32_Intrinsic<string GCCIntSuffix>
 773   : Hexagon_Intrinsic<GCCIntSuffix,
 774        [llvm_double_ty], [llvm_i32_ty],
 775        [IntrNoMem]>;
 776
 777 // tag : V6_vunpackuh
 778 class Hexagon_v32i32_v16i32_Intrinsic<string GCCIntSuffix>
 779   : Hexagon_Intrinsic<GCCIntSuffix,
 780        [llvm_v32i32_ty], [llvm_v16i32_ty],
 781        [IntrNoMem]>;
 782
 783 // tag : V6_vunpackuh
 784 class Hexagon_v64i32_v32i32_Intrinsic<string GCCIntSuffix>
 785   : Hexagon_Intrinsic<GCCIntSuffix,
 786        [llvm_v64i32_ty], [llvm_v32i32_ty],
 787        [IntrNoMem]>;
 788
 789 // tag : V6_vadduhw_acc
 790 class Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<string GCCIntSuffix>
 791   : Hexagon_Intrinsic<GCCIntSuffix,
 792        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty],
 793        [IntrNoMem]>;
 794
 795 // tag : V6_vadduhw_acc
 796 class Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<string GCCIntSuffix>
 797   : Hexagon_Intrinsic<GCCIntSuffix,
 798        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty],
 799        [IntrNoMem]>;
 800
 801 // tag : M2_vdmacs_s0
 802 class Hexagon_i64_i64i64i64_Intrinsic<string GCCIntSuffix>
 803   : Hexagon_Intrinsic<GCCIntSuffix,
 804        [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i64_ty],
 805        [IntrNoMem]>;
 806
 807 // tag : V6_vrmpybub_rtt_acc
 808 class Hexagon_v32i32_v32i32v16i32i64_Intrinsic<string GCCIntSuffix>
 809   : Hexagon_Intrinsic<GCCIntSuffix,
 810        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i64_ty],
 811        [IntrNoMem]>;
 812
 813 // tag : V6_vrmpybub_rtt_acc
 814 class Hexagon_v64i32_v64i32v32i32i64_Intrinsic<string GCCIntSuffix>
 815   : Hexagon_Intrinsic<GCCIntSuffix,
 816        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i64_ty],
 817        [IntrNoMem]>;
 818
 819 // tag : V6_ldu0
 820 class Hexagon_v16i32_i32_Intrinsic<string GCCIntSuffix>
 821   : Hexagon_Intrinsic<GCCIntSuffix,
 822        [llvm_v16i32_ty], [llvm_i32_ty],
 823        [IntrNoMem]>;
 824
 825 // tag : V6_ldu0
 826 class Hexagon_v32i32_i32_Intrinsic<string GCCIntSuffix>
 827   : Hexagon_Intrinsic<GCCIntSuffix,
 828        [llvm_v32i32_ty], [llvm_i32_ty],
 829        [IntrNoMem]>;
 830
 831 // tag : S4_extract_rp
 832 class Hexagon_i32_i32i64_Intrinsic<string GCCIntSuffix>
 833   : Hexagon_Intrinsic<GCCIntSuffix,
 834        [llvm_i32_ty], [llvm_i32_ty,llvm_i64_ty],
 835        [IntrNoMem]>;
 836
 837 // tag : V6_vdmpyhsuisat
 838 class Hexagon_v16i32_v32i32i32_Intrinsic<string GCCIntSuffix>
 839   : Hexagon_Intrinsic<GCCIntSuffix,
 840        [llvm_v16i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
 841        [IntrNoMem]>;
 842
 843 // tag : V6_vdmpyhsuisat
 844 class Hexagon_v32i32_v64i32i32_Intrinsic<string GCCIntSuffix>
 845   : Hexagon_Intrinsic<GCCIntSuffix,
 846        [llvm_v32i32_ty], [llvm_v64i32_ty,llvm_i32_ty],
 847        [IntrNoMem]>;
 848
 849 // tag : A2_addsp
 850 class Hexagon_i64_i32i64_Intrinsic<string GCCIntSuffix>
 851   : Hexagon_Intrinsic<GCCIntSuffix,
 852        [llvm_i64_ty], [llvm_i32_ty,llvm_i64_ty],
 853        [IntrNoMem]>;
 854
 855 // tag : V6_extractw
 856 class Hexagon_i32_v16i32i32_Intrinsic<string GCCIntSuffix>
 857   : Hexagon_Intrinsic<GCCIntSuffix,
 858        [llvm_i32_ty], [llvm_v16i32_ty,llvm_i32_ty],
 859        [IntrNoMem]>;
 860
 861 // tag : V6_extractw
 862 class Hexagon_i32_v32i32i32_Intrinsic<string GCCIntSuffix>
 863   : Hexagon_Intrinsic<GCCIntSuffix,
 864        [llvm_i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
 865        [IntrNoMem]>;
 866
 867 // tag : V6_vlutvwhi
 868 class Hexagon_v32i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix>
 869   : Hexagon_Intrinsic<GCCIntSuffix,
 870        [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
 871        [IntrNoMem]>;
 872
 873 // tag : V6_vlutvwhi
 874 class Hexagon_v64i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix>
 875   : Hexagon_Intrinsic<GCCIntSuffix,
 876        [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
 877        [IntrNoMem]>;
 878
 879 // tag : V6_vgtuh
 880 class Hexagon_v512i1_v16i32v16i32_Intrinsic<string GCCIntSuffix>
 881   : Hexagon_Intrinsic<GCCIntSuffix,
 882        [llvm_v512i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty],
 883        [IntrNoMem]>;
 884
 885 // tag : V6_vgtuh
 886 class Hexagon_v1024i1_v32i32v32i32_Intrinsic<string GCCIntSuffix>
 887   : Hexagon_Intrinsic<GCCIntSuffix,
 888        [llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty],
 889        [IntrNoMem]>;
 890
 891 // tag : F2_sffma_lib
 892 class Hexagon_float_floatfloatfloat_Intrinsic<string GCCIntSuffix>
 893   : Hexagon_Intrinsic<GCCIntSuffix,
 894        [llvm_float_ty], [llvm_float_ty,llvm_float_ty,llvm_float_ty],
 895        [IntrNoMem, Throws]>;
 896
 897 // tag : F2_conv_ud2df
 898 class Hexagon_double_i64_Intrinsic<string GCCIntSuffix>
 899   : Hexagon_Intrinsic<GCCIntSuffix,
 900        [llvm_double_ty], [llvm_i64_ty],
 901        [IntrNoMem]>;
 902
 903 // tag : S2_vzxthw
 904 class Hexagon_i64_i32_Intrinsic<string GCCIntSuffix>
 905   : Hexagon_Intrinsic<GCCIntSuffix,
 906        [llvm_i64_ty], [llvm_i32_ty],
 907        [IntrNoMem]>;
 908
 909 // tag : V6_vtmpyhb
 910 class Hexagon_v64i32_v64i32i32_Intrinsic<string GCCIntSuffix>
 911   : Hexagon_Intrinsic<GCCIntSuffix,
 912        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty],
 913        [IntrNoMem]>;
 914
 915 // tag : V6_vshufoeh
 916 class Hexagon_v32i32_v16i32v16i32_Intrinsic<string GCCIntSuffix>
 917   : Hexagon_Intrinsic<GCCIntSuffix,
 918        [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty],
 919        [IntrNoMem]>;
 920
 921 // tag : V6_vshufoeh
 922 class Hexagon_v64i32_v32i32v32i32_Intrinsic<string GCCIntSuffix>
 923   : Hexagon_Intrinsic<GCCIntSuffix,
 924        [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty],
 925        [IntrNoMem]>;
 926
 927 // tag : V6_vlut4
 928 class Hexagon_v16i32_v16i32i64_Intrinsic<string GCCIntSuffix>
 929   : Hexagon_Intrinsic<GCCIntSuffix,
 930        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i64_ty],
 931        [IntrNoMem]>;
 932
 933 // tag : V6_vlut4
 934 class Hexagon_v32i32_v32i32i64_Intrinsic<string GCCIntSuffix>
 935   : Hexagon_Intrinsic<GCCIntSuffix,
 936        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i64_ty],
 937        [IntrNoMem]>;
 938
 939 // tag :
 940 class Hexagon_v16i32_v16i32_Intrinsic<string GCCIntSuffix>
 941   : Hexagon_Intrinsic<GCCIntSuffix,
 942        [llvm_v16i32_ty], [llvm_v16i32_ty],
 943        [IntrNoMem]>;
 944
 945 // tag : F2_conv_uw2sf
 946 class Hexagon_float_i32_Intrinsic<string GCCIntSuffix>
 947   : Hexagon_Intrinsic<GCCIntSuffix,
 948        [llvm_float_ty], [llvm_i32_ty],
 949        [IntrNoMem]>;
 950
 951 // tag : V6_vswap
 952 class Hexagon_v32i32_v512i1v16i32v16i32_Intrinsic<string GCCIntSuffix>
 953   : Hexagon_Intrinsic<GCCIntSuffix,
 954        [llvm_v32i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty],
 955        [IntrNoMem]>;
 956
 957 // tag : V6_vswap
 958 class Hexagon_v64i32_v1024i1v32i32v32i32_Intrinsic<string GCCIntSuffix>
 959   : Hexagon_Intrinsic<GCCIntSuffix,
 960        [llvm_v64i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty],
 961        [IntrNoMem]>;
 962
 963 // tag : V6_vandnqrt
 964 class Hexagon_v16i32_v512i1i32_Intrinsic<string GCCIntSuffix>
 965   : Hexagon_Intrinsic<GCCIntSuffix,
 966        [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_i32_ty],
 967        [IntrNoMem]>;
 968
 969 // tag : V6_vandnqrt
 970 class Hexagon_v32i32_v1024i1i32_Intrinsic<string GCCIntSuffix>
 971   : Hexagon_Intrinsic<GCCIntSuffix,
 972        [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_i32_ty],
 973        [IntrNoMem]>;
 974
 975 // tag : V6_vmpyub
 976 class Hexagon_v64i32_v32i32i32_Intrinsic<string GCCIntSuffix>
 977   : Hexagon_Intrinsic<GCCIntSuffix,
 978        [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
 979        [IntrNoMem]>;
 980
 981 // tag : A5_ACS
 982 class Hexagon_i64i32_i64i64i64_Intrinsic<string GCCIntSuffix>
 983   : Hexagon_Intrinsic<GCCIntSuffix,
 984        [llvm_i64_ty,llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i64_ty],
 985        [IntrNoMem]>;
 986
 987 // tag : V6_vunpackob
 988 class Hexagon_v32i32_v32i32v16i32_Intrinsic<string GCCIntSuffix>
 989   : Hexagon_Intrinsic<GCCIntSuffix,
 990        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty],
 991        [IntrNoMem]>;
 992
 993 // tag : V6_vunpackob
 994 class Hexagon_v64i32_v64i32v32i32_Intrinsic<string GCCIntSuffix>
 995   : Hexagon_Intrinsic<GCCIntSuffix,
 996        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty],
 997        [IntrNoMem]>;
 998
 999 // tag : V6_vmpyhsat_acc
1000 class Hexagon_v32i32_v32i32v16i32i32_Intrinsic<string GCCIntSuffix>
1001   : Hexagon_Intrinsic<GCCIntSuffix,
1002        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i32_ty],
1003        [IntrNoMem]>;
1004
1005 // tag : V6_vmpyhsat_acc
1006 class Hexagon_v64i32_v64i32v32i32i32_Intrinsic<string GCCIntSuffix>
1007   : Hexagon_Intrinsic<GCCIntSuffix,
1008        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i32_ty],
1009        [IntrNoMem]>;
1010
1011 // tag : V6_vaddcarrysat
1012 class Hexagon_v16i32_v16i32v16i32v512i1_Intrinsic<string GCCIntSuffix>
1013   : Hexagon_Intrinsic<GCCIntSuffix,
1014        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v512i1_ty],
1015        [IntrNoMem]>;
1016
1017 // tag : V6_vaddcarrysat
1018 class Hexagon_v32i32_v32i32v32i32v1024i1_Intrinsic<string GCCIntSuffix>
1019   : Hexagon_Intrinsic<GCCIntSuffix,
1020        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v1024i1_ty],
1021        [IntrNoMem]>;
1022
1023 // tag : V6_vlutvvb_oracc
1024 class Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<string GCCIntSuffix>
1025   : Hexagon_Intrinsic<GCCIntSuffix,
1026        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
1027        [IntrNoMem]>;
1028
1029 // tag : V6_vlutvvb_oracc
1030 class Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<string GCCIntSuffix>
1031   : Hexagon_Intrinsic<GCCIntSuffix,
1032        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
1033        [IntrNoMem]>;
1034
1035 // tag : V6_vrmpybub_rtt
1036 class Hexagon_v32i32_v16i32i64_Intrinsic<string GCCIntSuffix>
1037   : Hexagon_Intrinsic<GCCIntSuffix,
1038        [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i64_ty],
1039        [IntrNoMem]>;
1040
1041 // tag : V6_vrmpybub_rtt
1042 class Hexagon_v64i32_v32i32i64_Intrinsic<string GCCIntSuffix>
1043   : Hexagon_Intrinsic<GCCIntSuffix,
1044        [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i64_ty],
1045        [IntrNoMem]>;
1046
1047 // tag : A4_addp_c
1048 class Hexagon_i64i32_i64i64i32_Intrinsic<string GCCIntSuffix>
1049   : Hexagon_Intrinsic<GCCIntSuffix,
1050        [llvm_i64_ty,llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty],
1051        [IntrNoMem]>;
1052
1053 // tag : V6_vrsadubi_acc
1054 class Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<string GCCIntSuffix>
1055   : Hexagon_Intrinsic<GCCIntSuffix,
1056        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty],
1057        [IntrNoMem]>;
1058
1059 // tag : V6_vrsadubi_acc
1060 class Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<string GCCIntSuffix>
1061   : Hexagon_Intrinsic<GCCIntSuffix,
1062        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty],
1063        [IntrNoMem]>;
1064
1065 // tag : F2_conv_df2sf
1066 class Hexagon_float_double_Intrinsic<string GCCIntSuffix>
1067   : Hexagon_Intrinsic<GCCIntSuffix,
1068        [llvm_float_ty], [llvm_double_ty],
1069        [IntrNoMem]>;
1070
1071 // tag : V6_vandvqv
1072 class Hexagon_v16i32_v512i1v16i32_Intrinsic<string GCCIntSuffix>
1073   : Hexagon_Intrinsic<GCCIntSuffix,
1074        [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty],
1075        [IntrNoMem]>;
1076
1077 // tag : V6_vandvqv
1078 class Hexagon_v32i32_v1024i1v32i32_Intrinsic<string GCCIntSuffix>
1079   : Hexagon_Intrinsic<GCCIntSuffix,
1080        [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty],
1081        [IntrNoMem]>;
1082
1083 // tag : C2_vmux
1084 class Hexagon_i64_i32i64i64_Intrinsic<string GCCIntSuffix>
1085   : Hexagon_Intrinsic<GCCIntSuffix,
1086        [llvm_i64_ty], [llvm_i32_ty,llvm_i64_ty,llvm_i64_ty],
1087        [IntrNoMem]>;
1088
1089 // tag : F2_sfcmpeq
1090 class Hexagon_i32_floatfloat_Intrinsic<string GCCIntSuffix>
1091   : Hexagon_Intrinsic<GCCIntSuffix,
1092        [llvm_i32_ty], [llvm_float_ty,llvm_float_ty],
1093        [IntrNoMem, Throws]>;
1094
1095 // tag : V6_vmpahhsat
1096 class Hexagon_v16i32_v16i32v16i32i64_Intrinsic<string GCCIntSuffix>
1097   : Hexagon_Intrinsic<GCCIntSuffix,
1098        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i64_ty],
1099        [IntrNoMem]>;
1100
1101 // tag : V6_vmpahhsat
1102 class Hexagon_v32i32_v32i32v32i32i64_Intrinsic<string GCCIntSuffix>
1103   : Hexagon_Intrinsic<GCCIntSuffix,
1104        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i64_ty],
1105        [IntrNoMem]>;
1106
1107 // tag : V6_vandvrt
1108 class Hexagon_v512i1_v16i32i32_Intrinsic<string GCCIntSuffix>
1109   : Hexagon_Intrinsic<GCCIntSuffix,
1110        [llvm_v512i1_ty], [llvm_v16i32_ty,llvm_i32_ty],
1111        [IntrNoMem]>;
1112
1113 // tag : V6_vandvrt
1114 class Hexagon_v1024i1_v32i32i32_Intrinsic<string GCCIntSuffix>
1115   : Hexagon_Intrinsic<GCCIntSuffix,
1116        [llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_i32_ty],
1117        [IntrNoMem]>;
1118
1119 // tag : V6_vsubcarry
1120 class Hexagon_custom_v16i32v512i1_v16i32v16i32v512i1_Intrinsic
1121   : Hexagon_NonGCC_Intrinsic<
1122        [llvm_v16i32_ty,llvm_v512i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v512i1_ty],
1123        [IntrNoMem]>;
1124
1125 // tag : V6_vsubcarry
1126 class Hexagon_custom_v32i32v1024i1_v32i32v32i32v1024i1_Intrinsic_128B
1127   : Hexagon_NonGCC_Intrinsic<
1128        [llvm_v32i32_ty,llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v1024i1_ty],
1129        [IntrNoMem]>;
1130
1131 // tag : F2_sffixupr
1132 class Hexagon_float_float_Intrinsic<string GCCIntSuffix>
1133   : Hexagon_Intrinsic<GCCIntSuffix,
1134        [llvm_float_ty], [llvm_float_ty],
1135        [IntrNoMem, Throws]>;
1136
1137 // tag : V6_vandvrt_acc
1138 class Hexagon_v512i1_v512i1v16i32i32_Intrinsic<string GCCIntSuffix>
1139   : Hexagon_Intrinsic<GCCIntSuffix,
1140        [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_i32_ty],
1141        [IntrNoMem]>;
1142
1143 // tag : V6_vandvrt_acc
1144 class Hexagon_v1024i1_v1024i1v32i32i32_Intrinsic<string GCCIntSuffix>
1145   : Hexagon_Intrinsic<GCCIntSuffix,
1146        [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_i32_ty],
1147        [IntrNoMem]>;
1148
1149 // tag : F2_dfsub
1150 class Hexagon_double_doubledouble_Intrinsic<string GCCIntSuffix>
1151   : Hexagon_Intrinsic<GCCIntSuffix,
1152        [llvm_double_ty], [llvm_double_ty,llvm_double_ty],
1153        [IntrNoMem, Throws]>;
1154
1155 // tag : V6_vmpyowh_sacc
1156 class Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<string GCCIntSuffix>
1157   : Hexagon_Intrinsic<GCCIntSuffix,
1158        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty],
1159        [IntrNoMem]>;
1160
1161 // tag : V6_vmpyowh_sacc
1162 class Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<string GCCIntSuffix>
1163   : Hexagon_Intrinsic<GCCIntSuffix,
1164        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty],
1165        [IntrNoMem]>;
1166
1167 // tag : S2_insertp
1168 class Hexagon_i64_i64i64i32i32_Intrinsic<string GCCIntSuffix>
1169   : Hexagon_Intrinsic<GCCIntSuffix,
1170        [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty,llvm_i32_ty],
1171        [IntrNoMem]>;
1172
1173 // tag : F2_sfinvsqrta
1174 class Hexagon_floati32_float_Intrinsic<string GCCIntSuffix>
1175   : Hexagon_Intrinsic<GCCIntSuffix,
1176        [llvm_float_ty,llvm_i32_ty], [llvm_float_ty],
1177        [IntrNoMem, Throws]>;
1178
1179 // tag : V6_vtran2x2_map
1180 class Hexagon_v16i32v16i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix>
1181   : Hexagon_Intrinsic<GCCIntSuffix,
1182        [llvm_v16i32_ty,llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
1183        [IntrNoMem]>;
1184
1185 // tag : V6_vtran2x2_map
1186 class Hexagon_v32i32v32i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix>
1187   : Hexagon_Intrinsic<GCCIntSuffix,
1188        [llvm_v32i32_ty,llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
1189        [IntrNoMem]>;
1190
1191 // tag : V6_vlutvwh_oracc
1192 class Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<string GCCIntSuffix>
1193   : Hexagon_Intrinsic<GCCIntSuffix,
1194        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
1195        [IntrNoMem]>;
1196
1197 // tag : V6_vlutvwh_oracc
1198 class Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<string GCCIntSuffix>
1199   : Hexagon_Intrinsic<GCCIntSuffix,
1200        [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
1201        [IntrNoMem]>;
1202
1203 // tag : F2_dfcmpge
1204 class Hexagon_i32_doubledouble_Intrinsic<string GCCIntSuffix>
1205   : Hexagon_Intrinsic<GCCIntSuffix,
1206        [llvm_i32_ty], [llvm_double_ty,llvm_double_ty],
1207        [IntrNoMem, Throws]>;
1208
1209 // tag : F2_conv_df2d_chop
1210 class Hexagon_i64_double_Intrinsic<string GCCIntSuffix>
1211   : Hexagon_Intrinsic<GCCIntSuffix,
1212        [llvm_i64_ty], [llvm_double_ty],
1213        [IntrNoMem]>;
1214
1215 // tag : F2_conv_sf2w
1216 class Hexagon_i32_float_Intrinsic<string GCCIntSuffix>
1217   : Hexagon_Intrinsic<GCCIntSuffix,
1218        [llvm_i32_ty], [llvm_float_ty],
1219        [IntrNoMem]>;
1220
1221 // tag : F2_sfclass
1222 class Hexagon_i32_floati32_Intrinsic<string GCCIntSuffix>
1223   : Hexagon_Intrinsic<GCCIntSuffix,
1224        [llvm_i32_ty], [llvm_float_ty,llvm_i32_ty],
1225        [IntrNoMem, Throws]>;
1226
1227 // tag : F2_conv_sf2ud_chop
1228 class Hexagon_i64_float_Intrinsic<string GCCIntSuffix>
1229   : Hexagon_Intrinsic<GCCIntSuffix,
1230        [llvm_i64_ty], [llvm_float_ty],
1231        [IntrNoMem]>;
1232
1233 // tag : V6_pred_scalar2v2
1234 class Hexagon_v512i1_i32_Intrinsic<string GCCIntSuffix>
1235   : Hexagon_Intrinsic<GCCIntSuffix,
1236        [llvm_v512i1_ty], [llvm_i32_ty],
1237        [IntrNoMem]>;
1238
1239 // tag : V6_pred_scalar2v2
1240 class Hexagon_v1024i1_i32_Intrinsic<string GCCIntSuffix>
1241   : Hexagon_Intrinsic<GCCIntSuffix,
1242        [llvm_v1024i1_ty], [llvm_i32_ty],
1243        [IntrNoMem]>;
1244
1245 // tag : F2_sfrecipa
1246 class Hexagon_floati32_floatfloat_Intrinsic<string GCCIntSuffix>
1247   : Hexagon_Intrinsic<GCCIntSuffix,
1248        [llvm_float_ty,llvm_i32_ty], [llvm_float_ty,llvm_float_ty],
1249        [IntrNoMem, Throws]>;
1250
1251 // tag : V6_vprefixqh
1252 class Hexagon_v16i32_v512i1_Intrinsic<string GCCIntSuffix>
1253   : Hexagon_Intrinsic<GCCIntSuffix,
1254        [llvm_v16i32_ty], [llvm_v512i1_ty],
1255        [IntrNoMem]>;
1256
1257 // tag : V6_vprefixqh
1258 class Hexagon_v32i32_v1024i1_Intrinsic<string GCCIntSuffix>
1259   : Hexagon_Intrinsic<GCCIntSuffix,
1260        [llvm_v32i32_ty], [llvm_v1024i1_ty],
1261        [IntrNoMem]>;
1262
1263 // tag : V6_vdmpyhisat_acc
1264 class Hexagon_v16i32_v16i32v32i32i32_Intrinsic<string GCCIntSuffix>
1265   : Hexagon_Intrinsic<GCCIntSuffix,
1266        [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v32i32_ty,llvm_i32_ty],
1267        [IntrNoMem]>;
1268
1269 // tag : V6_vdmpyhisat_acc
1270 class Hexagon_v32i32_v32i32v64i32i32_Intrinsic<string GCCIntSuffix>
1271   : Hexagon_Intrinsic<GCCIntSuffix,
1272        [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v64i32_ty,llvm_i32_ty],
1273        [IntrNoMem]>;
1274
1275 // tag : F2_conv_ud2sf
1276 class Hexagon_float_i64_Intrinsic<string GCCIntSuffix>
1277   : Hexagon_Intrinsic<GCCIntSuffix,
1278        [llvm_float_ty], [llvm_i64_ty],
1279        [IntrNoMem]>;
1280
1281 // tag : F2_conv_sf2df
1282 class Hexagon_double_float_Intrinsic<string GCCIntSuffix>
1283   : Hexagon_Intrinsic<GCCIntSuffix,
1284        [llvm_double_ty], [llvm_float_ty],
1285        [IntrNoMem]>;
1286
1287 // tag : F2_sffma_sc
1288 class Hexagon_float_floatfloatfloati32_Intrinsic<string GCCIntSuffix>
1289   : Hexagon_Intrinsic<GCCIntSuffix,
1290        [llvm_float_ty], [llvm_float_ty,llvm_float_ty,llvm_float_ty,llvm_i32_ty],
1291        [IntrNoMem, Throws]>;
1292
1293 // tag : F2_dfclass
1294 class Hexagon_i32_doublei32_Intrinsic<string GCCIntSuffix>
1295   : Hexagon_Intrinsic<GCCIntSuffix,
1296        [llvm_i32_ty], [llvm_double_ty,llvm_i32_ty],
1297        [IntrNoMem, Throws]>;
1298
1299 // tag : V6_vd0
1300 class Hexagon_v16i32__Intrinsic<string GCCIntSuffix>
1301   : Hexagon_Intrinsic<GCCIntSuffix,
1302        [llvm_v16i32_ty], [],
1303        [IntrNoMem]>;
1304
1305 // tag : V6_vd0
1306 class Hexagon_v32i32__Intrinsic<string GCCIntSuffix>
1307   : Hexagon_Intrinsic<GCCIntSuffix,
1308        [llvm_v32i32_ty], [],
1309        [IntrNoMem]>;
1310
1311 // tag : V6_vdd0
1312 class Hexagon_v64i32__Intrinsic<string GCCIntSuffix>
1313   : Hexagon_Intrinsic<GCCIntSuffix,
1314        [llvm_v64i32_ty], [],
1315        [IntrNoMem]>;
1316
1317 // tag : S2_insert_rp
1318 class Hexagon_i32_i32i32i64_Intrinsic<string GCCIntSuffix>
1319   : Hexagon_Intrinsic<GCCIntSuffix,
1320        [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i64_ty],
1321        [IntrNoMem]>;
1322
1323 // tag : V6_vassignp
1324 class Hexagon_v64i32_v64i32_Intrinsic<string GCCIntSuffix>
1325   : Hexagon_Intrinsic<GCCIntSuffix,
1326        [llvm_v64i32_ty], [llvm_v64i32_ty],
1327        [IntrNoMem]>;
1328
1329 // tag : A6_vminub_RdP
1330 class Hexagon_i64i32_i64i64_Intrinsic<string GCCIntSuffix>
1331   : Hexagon_Intrinsic<GCCIntSuffix,
1332        [llvm_i64_ty,llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty],
1333        [IntrNoMem]>;
1334
1335 // tag : V6_pred_not
1336 class Hexagon_v512i1_v512i1_Intrinsic<string GCCIntSuffix>
1337   : Hexagon_Intrinsic<GCCIntSuffix,
1338        [llvm_v512i1_ty], [llvm_v512i1_ty],
1339        [IntrNoMem]>;
1340
1341 // tag : V6_pred_not
1342 class Hexagon_v1024i1_v1024i1_Intrinsic<string GCCIntSuffix>
1343   : Hexagon_Intrinsic<GCCIntSuffix,
1344        [llvm_v1024i1_ty], [llvm_v1024i1_ty],
1345        [IntrNoMem]>;
1346
1347 // V5 Scalar Instructions.
1348
1349 def int_hexagon_S2_asr_r_p_or :
1350 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_or">;
1351
1352 def int_hexagon_S2_vsatwh :
1353 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsatwh">;
1354
1355 def int_hexagon_S2_tableidxd_goodsyntax :
1356 Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxd_goodsyntax">;
1357
1358 def int_hexagon_M2_mpysu_up :
1359 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysu_up">;
1360
1361 def int_hexagon_M2_mpyud_acc_ll_s0 :
1362 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s0">;
1363
1364 def int_hexagon_M2_mpyud_acc_ll_s1 :
1365 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s1">;
1366
1367 def int_hexagon_M2_cmpysc_s1 :
1368 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpysc_s1">;
1369
1370 def int_hexagon_M2_cmpysc_s0 :
1371 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpysc_s0">;
1372
1373 def int_hexagon_M4_cmpyi_whc :
1374 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyi_whc">;
1375
1376 def int_hexagon_M2_mpy_sat_rnd_lh_s1 :
1377 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s1">;
1378
1379 def int_hexagon_M2_mpy_sat_rnd_lh_s0 :
1380 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s0">;
1381
1382 def int_hexagon_S2_tableidxb_goodsyntax :
1383 Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxb_goodsyntax">;
1384
1385 def int_hexagon_S2_shuffoh :
1386 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffoh">;
1387
1388 def int_hexagon_F2_sfmax :
1389 Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmax">;
1390
1391 def int_hexagon_A2_vabswsat :
1392 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabswsat">;
1393
1394 def int_hexagon_S2_asr_i_r :
1395 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r">;
1396
1397 def int_hexagon_S2_asr_i_p :
1398 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p">;
1399
1400 def int_hexagon_A4_combineri :
1401 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineri">;
1402
1403 def int_hexagon_M2_mpy_nac_sat_hl_s1 :
1404 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s1">;
1405
1406 def int_hexagon_M4_vpmpyh_acc :
1407 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M4_vpmpyh_acc">;
1408
1409 def int_hexagon_M2_vcmpy_s0_sat_i :
1410 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_i">;
1411
1412 def int_hexagon_A2_notp :
1413 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_notp">;
1414
1415 def int_hexagon_M2_mpy_hl_s1 :
1416 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hl_s1">;
1417
1418 def int_hexagon_M2_mpy_hl_s0 :
1419 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hl_s0">;
1420
1421 def int_hexagon_C4_or_and :
1422 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_and">;
1423
1424 def int_hexagon_M2_vmac2s_s0 :
1425 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2s_s0">;
1426
1427 def int_hexagon_M2_vmac2s_s1 :
1428 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2s_s1">;
1429
1430 def int_hexagon_S2_brevp :
1431 Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_brevp">;
1432
1433 def int_hexagon_M4_pmpyw_acc :
1434 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M4_pmpyw_acc">;
1435
1436 def int_hexagon_S2_cl1 :
1437 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_cl1">;
1438
1439 def int_hexagon_C4_cmplte :
1440 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplte">;
1441
1442 def int_hexagon_M2_mmpyul_s0 :
1443 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_s0">;
1444
1445 def int_hexagon_A2_vaddws :
1446 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddws">;
1447
1448 def int_hexagon_A2_maxup :
1449 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_maxup">;
1450
1451 def int_hexagon_A4_vcmphgti :
1452 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgti">;
1453
1454 def int_hexagon_S2_interleave :
1455 Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_interleave">;
1456
1457 def int_hexagon_M2_vrcmpyi_s0 :
1458 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyi_s0">;
1459
1460 def int_hexagon_A2_abssat :
1461 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_abssat">;
1462
1463 def int_hexagon_A2_vcmpwgtu :
1464 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpwgtu">;
1465
1466 def int_hexagon_C2_cmpgtu :
1467 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtu">;
1468
1469 def int_hexagon_C2_cmpgtp :
1470 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpgtp">;
1471
1472 def int_hexagon_A4_cmphgtui :
1473 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtui">;
1474
1475 def int_hexagon_C2_cmpgti :
1476 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgti">;
1477
1478 def int_hexagon_M2_mpyi :
1479 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyi">;
1480
1481 def int_hexagon_F2_conv_df2uw_chop :
1482 Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2uw_chop">;
1483
1484 def int_hexagon_A4_cmpheq :
1485 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpheq">;
1486
1487 def int_hexagon_M2_mpy_lh_s1 :
1488 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_lh_s1">;
1489
1490 def int_hexagon_M2_mpy_lh_s0 :
1491 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_lh_s0">;
1492
1493 def int_hexagon_S2_lsr_i_r_xacc :
1494 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_xacc">;
1495
1496 def int_hexagon_S2_vrcnegh :
1497 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vrcnegh">;
1498
1499 def int_hexagon_S2_extractup :
1500 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S2_extractup">;
1501
1502 def int_hexagon_S2_asr_i_p_rnd_goodsyntax :
1503 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_rnd_goodsyntax">;
1504
1505 def int_hexagon_S4_ntstbit_r :
1506 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_r">;
1507
1508 def int_hexagon_F2_conv_w2sf :
1509 Hexagon_float_i32_Intrinsic<"HEXAGON_F2_conv_w2sf">;
1510
1511 def int_hexagon_C2_not :
1512 Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_not">;
1513
1514 def int_hexagon_C2_tfrpr :
1515 Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_tfrpr">;
1516
1517 def int_hexagon_M2_mpy_ll_s1 :
1518 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_ll_s1">;
1519
1520 def int_hexagon_M2_mpy_ll_s0 :
1521 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_ll_s0">;
1522
1523 def int_hexagon_A4_cmpbgt :
1524 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgt">;
1525
1526 def int_hexagon_S2_asr_r_r_and :
1527 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_and">;
1528
1529 def int_hexagon_A4_rcmpneqi :
1530 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpneqi">;
1531
1532 def int_hexagon_S2_asl_i_r_nac :
1533 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_nac">;
1534
1535 def int_hexagon_M2_subacc :
1536 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_subacc">;
1537
1538 def int_hexagon_A2_orp :
1539 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_orp">;
1540
1541 def int_hexagon_M2_mpyu_up :
1542 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_up">;
1543
1544 def int_hexagon_M2_mpy_acc_sat_lh_s1 :
1545 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s1">;
1546
1547 def int_hexagon_S2_asr_i_vh :
1548 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vh">;
1549
1550 def int_hexagon_S2_asr_i_vw :
1551 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vw">;
1552
1553 def int_hexagon_A4_cmpbgtu :
1554 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgtu">;
1555
1556 def int_hexagon_A4_vcmpbeq_any :
1557 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A4_vcmpbeq_any">;
1558
1559 def int_hexagon_A4_cmpbgti :
1560 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgti">;
1561
1562 def int_hexagon_M2_mpyd_lh_s1 :
1563 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_lh_s1">;
1564
1565 def int_hexagon_S2_asl_r_p_nac :
1566 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_nac">;
1567
1568 def int_hexagon_S2_lsr_i_r_nac :
1569 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_nac">;
1570
1571 def int_hexagon_A2_addsp :
1572 Hexagon_i64_i32i64_Intrinsic<"HEXAGON_A2_addsp">;
1573
1574 def int_hexagon_S4_vxsubaddw :
1575 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddw">;
1576
1577 def int_hexagon_A4_vcmpheqi :
1578 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpheqi">;
1579
1580 def int_hexagon_S4_vxsubaddh :
1581 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddh">;
1582
1583 def int_hexagon_M4_pmpyw :
1584 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M4_pmpyw">;
1585
1586 def int_hexagon_S2_vsathb :
1587 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsathb">;
1588
1589 def int_hexagon_S2_asr_r_p_and :
1590 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_and">;
1591
1592 def int_hexagon_M2_mpyu_acc_lh_s1 :
1593 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s1">;
1594
1595 def int_hexagon_M2_mpyu_acc_lh_s0 :
1596 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s0">;
1597
1598 def int_hexagon_S2_lsl_r_p_acc :
1599 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_acc">;
1600
1601 def int_hexagon_A2_pxorf :
1602 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_A2_pxorf">;
1603
1604 def int_hexagon_C2_cmpgei :
1605 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgei">;
1606
1607 def int_hexagon_A2_vsubub :
1608 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubub">;
1609
1610 def int_hexagon_S2_asl_i_p :
1611 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_p">;
1612
1613 def int_hexagon_S2_asl_i_r :
1614 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_i_r">;
1615
1616 def int_hexagon_A4_vrminuw :
1617 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminuw">;
1618
1619 def int_hexagon_F2_sffma :
1620 Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffma">;
1621
1622 def int_hexagon_A2_absp :
1623 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_absp">;
1624
1625 def int_hexagon_C2_all8 :
1626 Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_all8">;
1627
1628 def int_hexagon_A4_vrminuh :
1629 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminuh">;
1630
1631 def int_hexagon_F2_sffma_lib :
1632 Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffma_lib">;
1633
1634 def int_hexagon_M4_vrmpyoh_s0 :
1635 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_s0">;
1636
1637 def int_hexagon_M4_vrmpyoh_s1 :
1638 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_s1">;
1639
1640 def int_hexagon_C2_bitsset :
1641 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsset">;
1642
1643 def int_hexagon_M2_mpysip :
1644 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysip">;
1645
1646 def int_hexagon_M2_mpysin :
1647 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysin">;
1648
1649 def int_hexagon_A4_boundscheck :
1650 Hexagon_i32_i32i64_Intrinsic<"HEXAGON_A4_boundscheck">;
1651
1652 def int_hexagon_M5_vrmpybuu :
1653 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vrmpybuu">;
1654
1655 def int_hexagon_C4_fastcorner9 :
1656 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_fastcorner9">;
1657
1658 def int_hexagon_M2_vrcmpys_s1rp :
1659 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_s1rp">;
1660
1661 def int_hexagon_A2_neg :
1662 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_neg">;
1663
1664 def int_hexagon_A2_subsat :
1665 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subsat">;
1666
1667 def int_hexagon_S2_asl_r_r :
1668 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_r_r">;
1669
1670 def int_hexagon_S2_asl_r_p :
1671 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_p">;
1672
1673 def int_hexagon_A2_vnavgh :
1674 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgh">;
1675
1676 def int_hexagon_M2_mpy_nac_sat_hl_s0 :
1677 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s0">;
1678
1679 def int_hexagon_F2_conv_ud2df :
1680 Hexagon_double_i64_Intrinsic<"HEXAGON_F2_conv_ud2df">;
1681
1682 def int_hexagon_A2_vnavgw :
1683 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgw">;
1684
1685 def int_hexagon_S2_asl_i_r_acc :
1686 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_acc">;
1687
1688 def int_hexagon_S4_subi_lsr_ri :
1689 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_lsr_ri">;
1690
1691 def int_hexagon_S2_vzxthw :
1692 Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vzxthw">;
1693
1694 def int_hexagon_F2_sfadd :
1695 Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfadd">;
1696
1697 def int_hexagon_A2_sub :
1698 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_sub">;
1699
1700 def int_hexagon_M2_vmac2su_s0 :
1701 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2su_s0">;
1702
1703 def int_hexagon_M2_vmac2su_s1 :
1704 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2su_s1">;
1705
1706 def int_hexagon_M2_dpmpyss_s0 :
1707 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_s0">;
1708
1709 def int_hexagon_S2_insert :
1710 Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_insert">;
1711
1712 def int_hexagon_S2_packhl :
1713 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_S2_packhl">;
1714
1715 def int_hexagon_A4_vcmpwgti :
1716 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgti">;
1717
1718 def int_hexagon_A2_vavguwr :
1719 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguwr">;
1720
1721 def int_hexagon_S2_asl_r_r_and :
1722 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_and">;
1723
1724 def int_hexagon_A2_svsubhs :
1725 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubhs">;
1726
1727 def int_hexagon_A2_addh_l16_hl :
1728 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_hl">;
1729
1730 def int_hexagon_M4_and_and :
1731 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_and">;
1732
1733 def int_hexagon_F2_conv_d2df :
1734 Hexagon_double_i64_Intrinsic<"HEXAGON_F2_conv_d2df">;
1735
1736 def int_hexagon_C2_cmpgtui :
1737 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtui">;
1738
1739 def int_hexagon_A2_vconj :
1740 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vconj">;
1741
1742 def int_hexagon_S2_lsr_r_vw :
1743 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_vw">;
1744
1745 def int_hexagon_S2_lsr_r_vh :
1746 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_vh">;
1747
1748 def int_hexagon_A2_subh_l16_hl :
1749 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_hl">;
1750
1751 def int_hexagon_S4_vxsubaddhr :
1752 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddhr">;
1753
1754 def int_hexagon_S2_clbp :
1755 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_clbp">;
1756
1757 def int_hexagon_S2_deinterleave :
1758 Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_deinterleave">;
1759
1760 def int_hexagon_C2_any8 :
1761 Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_any8">;
1762
1763 def int_hexagon_S2_togglebit_r :
1764 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_r">;
1765
1766 def int_hexagon_S2_togglebit_i :
1767 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_i">;
1768
1769 def int_hexagon_F2_conv_uw2sf :
1770 Hexagon_float_i32_Intrinsic<"HEXAGON_F2_conv_uw2sf">;
1771
1772 def int_hexagon_S2_vsathb_nopack :
1773 Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsathb_nopack">;
1774
1775 def int_hexagon_M2_cmacs_s0 :
1776 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacs_s0">;
1777
1778 def int_hexagon_M2_cmacs_s1 :
1779 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacs_s1">;
1780
1781 def int_hexagon_M2_mpy_sat_hh_s0 :
1782 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s0">;
1783
1784 def int_hexagon_M2_mpy_sat_hh_s1 :
1785 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s1">;
1786
1787 def int_hexagon_M2_mmacuhs_s1 :
1788 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_s1">;
1789
1790 def int_hexagon_M2_mmacuhs_s0 :
1791 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_s0">;
1792
1793 def int_hexagon_S2_clrbit_r :
1794 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_clrbit_r">;
1795
1796 def int_hexagon_C4_or_andn :
1797 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_andn">;
1798
1799 def int_hexagon_S2_asl_r_r_nac :
1800 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_nac">;
1801
1802 def int_hexagon_S2_asl_i_p_acc :
1803 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_acc">;
1804
1805 def int_hexagon_A4_vcmpwgtui :
1806 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgtui">;
1807
1808 def int_hexagon_M4_vrmpyoh_acc_s0 :
1809 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s0">;
1810
1811 def int_hexagon_M4_vrmpyoh_acc_s1 :
1812 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s1">;
1813
1814 def int_hexagon_A4_vrmaxh :
1815 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxh">;
1816
1817 def int_hexagon_A2_vcmpbeq :
1818 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpbeq">;
1819
1820 def int_hexagon_A2_vcmphgt :
1821 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmphgt">;
1822
1823 def int_hexagon_A2_vnavgwcr :
1824 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgwcr">;
1825
1826 def int_hexagon_M2_vrcmacr_s0c :
1827 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmacr_s0c">;
1828
1829 def int_hexagon_A2_vavgwcr :
1830 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgwcr">;
1831
1832 def int_hexagon_S2_asl_i_p_xacc :
1833 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_xacc">;
1834
1835 def int_hexagon_A4_vrmaxw :
1836 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxw">;
1837
1838 def int_hexagon_A2_vnavghr :
1839 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavghr">;
1840
1841 def int_hexagon_M4_cmpyi_wh :
1842 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyi_wh">;
1843
1844 def int_hexagon_A2_tfrsi :
1845 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfrsi">;
1846
1847 def int_hexagon_S2_asr_i_r_acc :
1848 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_acc">;
1849
1850 def int_hexagon_A2_svnavgh :
1851 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svnavgh">;
1852
1853 def int_hexagon_S2_lsr_i_r :
1854 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r">;
1855
1856 def int_hexagon_M2_vmac2 :
1857 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2">;
1858
1859 def int_hexagon_A4_vcmphgtui :
1860 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgtui">;
1861
1862 def int_hexagon_A2_svavgh :
1863 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svavgh">;
1864
1865 def int_hexagon_M4_vrmpyeh_acc_s0 :
1866 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s0">;
1867
1868 def int_hexagon_M4_vrmpyeh_acc_s1 :
1869 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s1">;
1870
1871 def int_hexagon_S2_lsr_i_p :
1872 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p">;
1873
1874 def int_hexagon_A2_combine_hl :
1875 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_hl">;
1876
1877 def int_hexagon_M2_mpy_up :
1878 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up">;
1879
1880 def int_hexagon_A2_combine_hh :
1881 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_hh">;
1882
1883 def int_hexagon_A2_negsat :
1884 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_negsat">;
1885
1886 def int_hexagon_M2_mpyd_hl_s0 :
1887 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hl_s0">;
1888
1889 def int_hexagon_M2_mpyd_hl_s1 :
1890 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hl_s1">;
1891
1892 def int_hexagon_A4_bitsplit :
1893 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_bitsplit">;
1894
1895 def int_hexagon_A2_vabshsat :
1896 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabshsat">;
1897
1898 def int_hexagon_M2_mpyui :
1899 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyui">;
1900
1901 def int_hexagon_A2_addh_l16_sat_ll :
1902 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_sat_ll">;
1903
1904 def int_hexagon_S2_lsl_r_r_and :
1905 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_and">;
1906
1907 def int_hexagon_M2_mmpyul_rs0 :
1908 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_rs0">;
1909
1910 def int_hexagon_S2_asr_i_r_rnd_goodsyntax :
1911 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd_goodsyntax">;
1912
1913 def int_hexagon_S2_lsr_r_p_nac :
1914 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_nac">;
1915
1916 def int_hexagon_C2_cmplt :
1917 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmplt">;
1918
1919 def int_hexagon_M2_cmacr_s0 :
1920 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacr_s0">;
1921
1922 def int_hexagon_M4_or_and :
1923 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_and">;
1924
1925 def int_hexagon_M4_mpyrr_addi :
1926 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyrr_addi">;
1927
1928 def int_hexagon_S4_or_andi :
1929 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andi">;
1930
1931 def int_hexagon_M2_mpy_sat_hl_s0 :
1932 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s0">;
1933
1934 def int_hexagon_M2_mpy_sat_hl_s1 :
1935 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s1">;
1936
1937 def int_hexagon_M4_mpyrr_addr :
1938 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyrr_addr">;
1939
1940 def int_hexagon_M2_mmachs_rs0 :
1941 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_rs0">;
1942
1943 def int_hexagon_M2_mmachs_rs1 :
1944 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_rs1">;
1945
1946 def int_hexagon_M2_vrcmpyr_s0c :
1947 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyr_s0c">;
1948
1949 def int_hexagon_M2_mpy_acc_sat_hl_s0 :
1950 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s0">;
1951
1952 def int_hexagon_M2_mpyd_acc_ll_s1 :
1953 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s1">;
1954
1955 def int_hexagon_F2_sffixupn :
1956 Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sffixupn">;
1957
1958 def int_hexagon_M2_mpyd_acc_lh_s0 :
1959 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s0">;
1960
1961 def int_hexagon_M2_mpyd_acc_lh_s1 :
1962 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s1">;
1963
1964 def int_hexagon_M2_mpy_rnd_hh_s0 :
1965 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s0">;
1966
1967 def int_hexagon_M2_mpy_rnd_hh_s1 :
1968 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s1">;
1969
1970 def int_hexagon_A2_vadduhs :
1971 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vadduhs">;
1972
1973 def int_hexagon_A2_vsubuhs :
1974 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubuhs">;
1975
1976 def int_hexagon_A2_subh_h16_hl :
1977 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_hl">;
1978
1979 def int_hexagon_A2_subh_h16_hh :
1980 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_hh">;
1981
1982 def int_hexagon_A2_xorp :
1983 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_xorp">;
1984
1985 def int_hexagon_A4_tfrpcp :
1986 Hexagon_i64_i64_Intrinsic<"HEXAGON_A4_tfrpcp">;
1987
1988 def int_hexagon_A2_addh_h16_lh :
1989 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_lh">;
1990
1991 def int_hexagon_A2_addh_h16_sat_hl :
1992 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_hl">;
1993
1994 def int_hexagon_A2_addh_h16_ll :
1995 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_ll">;
1996
1997 def int_hexagon_A2_addh_h16_sat_hh :
1998 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_hh">;
1999
2000 def int_hexagon_A2_zxtb :
2001 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_zxtb">;
2002
2003 def int_hexagon_A2_zxth :
2004 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_zxth">;
2005
2006 def int_hexagon_A2_vnavgwr :
2007 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgwr">;
2008
2009 def int_hexagon_M4_or_xor :
2010 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_xor">;
2011
2012 def int_hexagon_M2_mpyud_acc_hh_s0 :
2013 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s0">;
2014
2015 def int_hexagon_M2_mpyud_acc_hh_s1 :
2016 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s1">;
2017
2018 def int_hexagon_M5_vmacbsu :
2019 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M5_vmacbsu">;
2020
2021 def int_hexagon_M2_dpmpyuu_acc_s0 :
2022 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_acc_s0">;
2023
2024 def int_hexagon_M2_mpy_rnd_hl_s0 :
2025 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s0">;
2026
2027 def int_hexagon_M2_mpy_rnd_hl_s1 :
2028 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s1">;
2029
2030 def int_hexagon_F2_sffms_lib :
2031 Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffms_lib">;
2032
2033 def int_hexagon_C4_cmpneqi :
2034 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpneqi">;
2035
2036 def int_hexagon_M4_and_xor :
2037 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_xor">;
2038
2039 def int_hexagon_A2_sat :
2040 Hexagon_i32_i64_Intrinsic<"HEXAGON_A2_sat">;
2041
2042 def int_hexagon_M2_mpyd_nac_lh_s1 :
2043 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s1">;
2044
2045 def int_hexagon_M2_mpyd_nac_lh_s0 :
2046 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s0">;
2047
2048 def int_hexagon_A2_addsat :
2049 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addsat">;
2050
2051 def int_hexagon_A2_svavghs :
2052 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svavghs">;
2053
2054 def int_hexagon_A2_vrsadub_acc :
2055 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_A2_vrsadub_acc">;
2056
2057 def int_hexagon_C2_bitsclri :
2058 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsclri">;
2059
2060 def int_hexagon_A2_subh_h16_sat_hh :
2061 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_hh">;
2062
2063 def int_hexagon_A2_subh_h16_sat_hl :
2064 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_hl">;
2065
2066 def int_hexagon_M2_mmaculs_rs0 :
2067 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_rs0">;
2068
2069 def int_hexagon_M2_mmaculs_rs1 :
2070 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_rs1">;
2071
2072 def int_hexagon_M2_vradduh :
2073 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vradduh">;
2074
2075 def int_hexagon_A4_addp_c :
2076 Hexagon_i64i32_i64i64i32_Intrinsic<"HEXAGON_A4_addp_c">;
2077
2078 def int_hexagon_C2_xor :
2079 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_xor">;
2080
2081 def int_hexagon_S2_lsl_r_r_acc :
2082 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_acc">;
2083
2084 def int_hexagon_M2_mmpyh_rs1 :
2085 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_rs1">;
2086
2087 def int_hexagon_M2_mmpyh_rs0 :
2088 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_rs0">;
2089
2090 def int_hexagon_F2_conv_df2ud_chop :
2091 Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2ud_chop">;
2092
2093 def int_hexagon_C4_or_or :
2094 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_or">;
2095
2096 def int_hexagon_S4_vxaddsubhr :
2097 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubhr">;
2098
2099 def int_hexagon_S2_vsathub :
2100 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsathub">;
2101
2102 def int_hexagon_F2_conv_df2sf :
2103 Hexagon_float_double_Intrinsic<"HEXAGON_F2_conv_df2sf">;
2104
2105 def int_hexagon_M2_hmmpyh_rs1 :
2106 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyh_rs1">;
2107
2108 def int_hexagon_M2_hmmpyh_s1 :
2109 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyh_s1">;
2110
2111 def int_hexagon_A2_vavgwr :
2112 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgwr">;
2113
2114 def int_hexagon_S2_tableidxh_goodsyntax :
2115 Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxh_goodsyntax">;
2116
2117 def int_hexagon_A2_sxth :
2118 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sxth">;
2119
2120 def int_hexagon_A2_sxtb :
2121 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sxtb">;
2122
2123 def int_hexagon_C4_or_orn :
2124 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_orn">;
2125
2126 def int_hexagon_M2_vrcmaci_s0c :
2127 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmaci_s0c">;
2128
2129 def int_hexagon_A2_sxtw :
2130 Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_sxtw">;
2131
2132 def int_hexagon_M2_vabsdiffh :
2133 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vabsdiffh">;
2134
2135 def int_hexagon_M2_mpy_acc_lh_s1 :
2136 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s1">;
2137
2138 def int_hexagon_M2_mpy_acc_lh_s0 :
2139 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s0">;
2140
2141 def int_hexagon_M2_hmmpyl_s1 :
2142 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyl_s1">;
2143
2144 def int_hexagon_S2_cl1p :
2145 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_cl1p">;
2146
2147 def int_hexagon_M2_vabsdiffw :
2148 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vabsdiffw">;
2149
2150 def int_hexagon_A4_andnp :
2151 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A4_andnp">;
2152
2153 def int_hexagon_C2_vmux :
2154 Hexagon_i64_i32i64i64_Intrinsic<"HEXAGON_C2_vmux">;
2155
2156 def int_hexagon_S2_parityp :
2157 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_S2_parityp">;
2158
2159 def int_hexagon_S2_lsr_i_p_and :
2160 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_and">;
2161
2162 def int_hexagon_S2_asr_i_r_or :
2163 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_or">;
2164
2165 def int_hexagon_M2_mpyu_nac_ll_s0 :
2166 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s0">;
2167
2168 def int_hexagon_M2_mpyu_nac_ll_s1 :
2169 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s1">;
2170
2171 def int_hexagon_F2_sfcmpeq :
2172 Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpeq">;
2173
2174 def int_hexagon_A2_vaddb_map :
2175 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddb_map">;
2176
2177 def int_hexagon_S2_lsr_r_r_nac :
2178 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_nac">;
2179
2180 def int_hexagon_A2_vcmpheq :
2181 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpheq">;
2182
2183 def int_hexagon_S2_clbnorm :
2184 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_clbnorm">;
2185
2186 def int_hexagon_M2_cnacsc_s1 :
2187 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacsc_s1">;
2188
2189 def int_hexagon_M2_cnacsc_s0 :
2190 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacsc_s0">;
2191
2192 def int_hexagon_S4_subaddi :
2193 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subaddi">;
2194
2195 def int_hexagon_M2_mpyud_nac_hl_s1 :
2196 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s1">;
2197
2198 def int_hexagon_M2_mpyud_nac_hl_s0 :
2199 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s0">;
2200
2201 def int_hexagon_S5_vasrhrnd_goodsyntax :
2202 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S5_vasrhrnd_goodsyntax">;
2203
2204 def int_hexagon_S2_tstbit_r :
2205 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_r">;
2206
2207 def int_hexagon_S4_vrcrotate :
2208 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate">;
2209
2210 def int_hexagon_M2_mmachs_s1 :
2211 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_s1">;
2212
2213 def int_hexagon_M2_mmachs_s0 :
2214 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_s0">;
2215
2216 def int_hexagon_S2_tstbit_i :
2217 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_i">;
2218
2219 def int_hexagon_M2_mpy_up_s1 :
2220 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up_s1">;
2221
2222 def int_hexagon_S2_extractu_rp :
2223 Hexagon_i32_i32i64_Intrinsic<"HEXAGON_S2_extractu_rp">;
2224
2225 def int_hexagon_M2_mmpyuh_rs0 :
2226 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_rs0">;
2227
2228 def int_hexagon_S2_lsr_i_vw :
2229 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vw">;
2230
2231 def int_hexagon_M2_mpy_rnd_ll_s0 :
2232 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s0">;
2233
2234 def int_hexagon_M2_mpy_rnd_ll_s1 :
2235 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s1">;
2236
2237 def int_hexagon_M4_or_or :
2238 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_or">;
2239
2240 def int_hexagon_M2_mpyu_hh_s1 :
2241 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hh_s1">;
2242
2243 def int_hexagon_M2_mpyu_hh_s0 :
2244 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hh_s0">;
2245
2246 def int_hexagon_S2_asl_r_p_acc :
2247 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_acc">;
2248
2249 def int_hexagon_M2_mpyu_nac_lh_s0 :
2250 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s0">;
2251
2252 def int_hexagon_M2_mpyu_nac_lh_s1 :
2253 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s1">;
2254
2255 def int_hexagon_M2_mpy_sat_ll_s0 :
2256 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s0">;
2257
2258 def int_hexagon_M2_mpy_sat_ll_s1 :
2259 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s1">;
2260
2261 def int_hexagon_F2_conv_w2df :
2262 Hexagon_double_i32_Intrinsic<"HEXAGON_F2_conv_w2df">;
2263
2264 def int_hexagon_A2_subh_l16_sat_hl :
2265 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_sat_hl">;
2266
2267 def int_hexagon_C2_cmpeqi :
2268 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpeqi">;
2269
2270 def int_hexagon_S2_asl_i_r_and :
2271 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_and">;
2272
2273 def int_hexagon_S2_vcnegh :
2274 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_vcnegh">;
2275
2276 def int_hexagon_A4_vcmpweqi :
2277 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpweqi">;
2278
2279 def int_hexagon_M2_vdmpyrs_s0 :
2280 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vdmpyrs_s0">;
2281
2282 def int_hexagon_M2_vdmpyrs_s1 :
2283 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vdmpyrs_s1">;
2284
2285 def int_hexagon_M4_xor_xacc :
2286 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_xor_xacc">;
2287
2288 def int_hexagon_M2_vdmpys_s1 :
2289 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vdmpys_s1">;
2290
2291 def int_hexagon_M2_vdmpys_s0 :
2292 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vdmpys_s0">;
2293
2294 def int_hexagon_A2_vavgubr :
2295 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgubr">;
2296
2297 def int_hexagon_M2_mpyu_hl_s1 :
2298 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hl_s1">;
2299
2300 def int_hexagon_M2_mpyu_hl_s0 :
2301 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hl_s0">;
2302
2303 def int_hexagon_S2_asl_r_r_acc :
2304 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_acc">;
2305
2306 def int_hexagon_S2_cl0p :
2307 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_cl0p">;
2308
2309 def int_hexagon_S2_valignib :
2310 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_valignib">;
2311
2312 def int_hexagon_F2_sffixupd :
2313 Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sffixupd">;
2314
2315 def int_hexagon_M2_mpy_sat_rnd_hl_s1 :
2316 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s1">;
2317
2318 def int_hexagon_M2_mpy_sat_rnd_hl_s0 :
2319 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s0">;
2320
2321 def int_hexagon_M2_cmacsc_s0 :
2322 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacsc_s0">;
2323
2324 def int_hexagon_M2_cmacsc_s1 :
2325 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacsc_s1">;
2326
2327 def int_hexagon_S2_ct1 :
2328 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_ct1">;
2329
2330 def int_hexagon_S2_ct0 :
2331 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_ct0">;
2332
2333 def int_hexagon_M2_dpmpyuu_nac_s0 :
2334 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_nac_s0">;
2335
2336 def int_hexagon_M2_mmpyul_rs1 :
2337 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_rs1">;
2338
2339 def int_hexagon_S4_ntstbit_i :
2340 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_i">;
2341
2342 def int_hexagon_F2_sffixupr :
2343 Hexagon_float_float_Intrinsic<"HEXAGON_F2_sffixupr">;
2344
2345 def int_hexagon_S2_asr_r_p_xor :
2346 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_xor">;
2347
2348 def int_hexagon_M2_mpyud_acc_hl_s0 :
2349 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s0">;
2350
2351 def int_hexagon_M2_mpyud_acc_hl_s1 :
2352 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s1">;
2353
2354 def int_hexagon_A2_vcmphgtu :
2355 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmphgtu">;
2356
2357 def int_hexagon_C2_andn :
2358 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_andn">;
2359
2360 def int_hexagon_M2_vmpy2s_s0pack :
2361 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s0pack">;
2362
2363 def int_hexagon_S4_addaddi :
2364 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addaddi">;
2365
2366 def int_hexagon_M2_mpyd_acc_ll_s0 :
2367 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s0">;
2368
2369 def int_hexagon_M2_mpy_acc_sat_hl_s1 :
2370 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s1">;
2371
2372 def int_hexagon_A4_rcmpeqi :
2373 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpeqi">;
2374
2375 def int_hexagon_M4_xor_and :
2376 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_and">;
2377
2378 def int_hexagon_S2_asl_i_p_and :
2379 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_and">;
2380
2381 def int_hexagon_M2_mmpyuh_rs1 :
2382 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_rs1">;
2383
2384 def int_hexagon_S2_asr_r_r_or :
2385 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_or">;
2386
2387 def int_hexagon_A4_round_ri :
2388 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri">;
2389
2390 def int_hexagon_A2_max :
2391 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_max">;
2392
2393 def int_hexagon_A4_round_rr :
2394 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_rr">;
2395
2396 def int_hexagon_A4_combineii :
2397 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineii">;
2398
2399 def int_hexagon_A4_combineir :
2400 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineir">;
2401
2402 def int_hexagon_C4_and_orn :
2403 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_orn">;
2404
2405 def int_hexagon_M5_vmacbuu :
2406 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M5_vmacbuu">;
2407
2408 def int_hexagon_A4_rcmpeq :
2409 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpeq">;
2410
2411 def int_hexagon_M4_cmpyr_whc :
2412 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyr_whc">;
2413
2414 def int_hexagon_S2_lsr_i_r_acc :
2415 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_acc">;
2416
2417 def int_hexagon_S2_vzxtbh :
2418 Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vzxtbh">;
2419
2420 def int_hexagon_M2_mmacuhs_rs1 :
2421 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_rs1">;
2422
2423 def int_hexagon_S2_asr_r_r_sat :
2424 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_sat">;
2425
2426 def int_hexagon_A2_combinew :
2427 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combinew">;
2428
2429 def int_hexagon_M2_mpy_acc_ll_s1 :
2430 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s1">;
2431
2432 def int_hexagon_M2_mpy_acc_ll_s0 :
2433 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s0">;
2434
2435 def int_hexagon_M2_cmpyi_s0 :
2436 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpyi_s0">;
2437
2438 def int_hexagon_S2_asl_r_p_or :
2439 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_or">;
2440
2441 def int_hexagon_S4_ori_asl_ri :
2442 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_asl_ri">;
2443
2444 def int_hexagon_C4_nbitsset :
2445 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsset">;
2446
2447 def int_hexagon_M2_mpyu_acc_hh_s1 :
2448 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s1">;
2449
2450 def int_hexagon_M2_mpyu_acc_hh_s0 :
2451 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s0">;
2452
2453 def int_hexagon_M2_mpyu_ll_s1 :
2454 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_ll_s1">;
2455
2456 def int_hexagon_M2_mpyu_ll_s0 :
2457 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_ll_s0">;
2458
2459 def int_hexagon_A2_addh_l16_ll :
2460 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_ll">;
2461
2462 def int_hexagon_S2_lsr_r_r_and :
2463 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_and">;
2464
2465 def int_hexagon_A4_modwrapu :
2466 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_modwrapu">;
2467
2468 def int_hexagon_A4_rcmpneq :
2469 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpneq">;
2470
2471 def int_hexagon_M2_mpyd_acc_hh_s0 :
2472 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s0">;
2473
2474 def int_hexagon_M2_mpyd_acc_hh_s1 :
2475 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s1">;
2476
2477 def int_hexagon_F2_sfimm_p :
2478 Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_p">;
2479
2480 def int_hexagon_F2_sfimm_n :
2481 Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_n">;
2482
2483 def int_hexagon_M4_cmpyr_wh :
2484 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyr_wh">;
2485
2486 def int_hexagon_S2_lsl_r_p_and :
2487 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_and">;
2488
2489 def int_hexagon_A2_vavgub :
2490 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgub">;
2491
2492 def int_hexagon_F2_conv_d2sf :
2493 Hexagon_float_i64_Intrinsic<"HEXAGON_F2_conv_d2sf">;
2494
2495 def int_hexagon_A2_vavguh :
2496 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguh">;
2497
2498 def int_hexagon_A4_cmpbeqi :
2499 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbeqi">;
2500
2501 def int_hexagon_F2_sfcmpuo :
2502 Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpuo">;
2503
2504 def int_hexagon_A2_vavguw :
2505 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguw">;
2506
2507 def int_hexagon_S2_asr_i_p_nac :
2508 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_nac">;
2509
2510 def int_hexagon_S2_vsatwh_nopack :
2511 Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsatwh_nopack">;
2512
2513 def int_hexagon_M2_mpyd_hh_s0 :
2514 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hh_s0">;
2515
2516 def int_hexagon_M2_mpyd_hh_s1 :
2517 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hh_s1">;
2518
2519 def int_hexagon_S2_lsl_r_p_or :
2520 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_or">;
2521
2522 def int_hexagon_A2_minu :
2523 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_minu">;
2524
2525 def int_hexagon_M2_mpy_sat_lh_s1 :
2526 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s1">;
2527
2528 def int_hexagon_M4_or_andn :
2529 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_andn">;
2530
2531 def int_hexagon_A2_minp :
2532 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_minp">;
2533
2534 def int_hexagon_S4_or_andix :
2535 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andix">;
2536
2537 def int_hexagon_M2_mpy_rnd_lh_s0 :
2538 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s0">;
2539
2540 def int_hexagon_M2_mpy_rnd_lh_s1 :
2541 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s1">;
2542
2543 def int_hexagon_M2_mmpyuh_s0 :
2544 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_s0">;
2545
2546 def int_hexagon_M2_mmpyuh_s1 :
2547 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_s1">;
2548
2549 def int_hexagon_M2_mpy_acc_sat_lh_s0 :
2550 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s0">;
2551
2552 def int_hexagon_F2_sfcmpge :
2553 Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpge">;
2554
2555 def int_hexagon_F2_sfmin :
2556 Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmin">;
2557
2558 def int_hexagon_F2_sfcmpgt :
2559 Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpgt">;
2560
2561 def int_hexagon_M4_vpmpyh :
2562 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M4_vpmpyh">;
2563
2564 def int_hexagon_M2_mmacuhs_rs0 :
2565 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_rs0">;
2566
2567 def int_hexagon_M2_mpyd_rnd_lh_s1 :
2568 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s1">;
2569
2570 def int_hexagon_M2_mpyd_rnd_lh_s0 :
2571 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s0">;
2572
2573 def int_hexagon_A2_roundsat :
2574 Hexagon_i32_i64_Intrinsic<"HEXAGON_A2_roundsat">;
2575
2576 def int_hexagon_S2_ct1p :
2577 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_ct1p">;
2578
2579 def int_hexagon_S4_extract_rp :
2580 Hexagon_i32_i32i64_Intrinsic<"HEXAGON_S4_extract_rp">;
2581
2582 def int_hexagon_S2_lsl_r_r_or :
2583 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_or">;
2584
2585 def int_hexagon_C4_cmplteui :
2586 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplteui">;
2587
2588 def int_hexagon_S4_addi_lsr_ri :
2589 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_lsr_ri">;
2590
2591 def int_hexagon_A4_tfrcpp :
2592 Hexagon_i64_i64_Intrinsic<"HEXAGON_A4_tfrcpp">;
2593
2594 def int_hexagon_S2_asr_i_svw_trun :
2595 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S2_asr_i_svw_trun">;
2596
2597 def int_hexagon_A4_cmphgti :
2598 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgti">;
2599
2600 def int_hexagon_A4_vrminh :
2601 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminh">;
2602
2603 def int_hexagon_A4_vrminw :
2604 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminw">;
2605
2606 def int_hexagon_A4_cmphgtu :
2607 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtu">;
2608
2609 def int_hexagon_S2_insertp_rp :
2610 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_S2_insertp_rp">;
2611
2612 def int_hexagon_A2_vnavghcr :
2613 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavghcr">;
2614
2615 def int_hexagon_S4_subi_asl_ri :
2616 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_asl_ri">;
2617
2618 def int_hexagon_S2_lsl_r_vh :
2619 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_vh">;
2620
2621 def int_hexagon_M2_mpy_hh_s0 :
2622 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hh_s0">;
2623
2624 def int_hexagon_A2_vsubws :
2625 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubws">;
2626
2627 def int_hexagon_A2_sath :
2628 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sath">;
2629
2630 def int_hexagon_S2_asl_r_p_xor :
2631 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_xor">;
2632
2633 def int_hexagon_A2_satb :
2634 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satb">;
2635
2636 def int_hexagon_C2_cmpltu :
2637 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpltu">;
2638
2639 def int_hexagon_S2_insertp :
2640 Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S2_insertp">;
2641
2642 def int_hexagon_M2_mpyd_rnd_ll_s1 :
2643 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s1">;
2644
2645 def int_hexagon_M2_mpyd_rnd_ll_s0 :
2646 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s0">;
2647
2648 def int_hexagon_S2_lsr_i_p_nac :
2649 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_nac">;
2650
2651 def int_hexagon_S2_extractup_rp :
2652 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_extractup_rp">;
2653
2654 def int_hexagon_S4_vxaddsubw :
2655 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubw">;
2656
2657 def int_hexagon_S4_vxaddsubh :
2658 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubh">;
2659
2660 def int_hexagon_A2_asrh :
2661 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_asrh">;
2662
2663 def int_hexagon_S4_extractp_rp :
2664 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_extractp_rp">;
2665
2666 def int_hexagon_S2_lsr_r_r_acc :
2667 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_acc">;
2668
2669 def int_hexagon_M2_mpyd_nac_ll_s1 :
2670 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s1">;
2671
2672 def int_hexagon_M2_mpyd_nac_ll_s0 :
2673 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s0">;
2674
2675 def int_hexagon_C2_or :
2676 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_or">;
2677
2678 def int_hexagon_M2_mmpyul_s1 :
2679 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_s1">;
2680
2681 def int_hexagon_M2_vrcmacr_s0 :
2682 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmacr_s0">;
2683
2684 def int_hexagon_A2_xor :
2685 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_xor">;
2686
2687 def int_hexagon_A2_add :
2688 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_add">;
2689
2690 def int_hexagon_A2_vsububs :
2691 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsububs">;
2692
2693 def int_hexagon_M2_vmpy2s_s1 :
2694 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s1">;
2695
2696 def int_hexagon_M2_vmpy2s_s0 :
2697 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s0">;
2698
2699 def int_hexagon_A2_vraddub_acc :
2700 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_A2_vraddub_acc">;
2701
2702 def int_hexagon_F2_sfinvsqrta :
2703 Hexagon_floati32_float_Intrinsic<"HEXAGON_F2_sfinvsqrta">;
2704
2705 def int_hexagon_S2_ct0p :
2706 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_ct0p">;
2707
2708 def int_hexagon_A2_svaddh :
2709 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svaddh">;
2710
2711 def int_hexagon_S2_vcrotate :
2712 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_vcrotate">;
2713
2714 def int_hexagon_A2_aslh :
2715 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_aslh">;
2716
2717 def int_hexagon_A2_subh_h16_lh :
2718 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_lh">;
2719
2720 def int_hexagon_A2_subh_h16_ll :
2721 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_ll">;
2722
2723 def int_hexagon_M2_hmmpyl_rs1 :
2724 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyl_rs1">;
2725
2726 def int_hexagon_S2_asr_r_p :
2727 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_p">;
2728
2729 def int_hexagon_S2_vsplatrh :
2730 Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsplatrh">;
2731
2732 def int_hexagon_S2_asr_r_r :
2733 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_r_r">;
2734
2735 def int_hexagon_A2_addh_h16_hl :
2736 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_hl">;
2737
2738 def int_hexagon_S2_vsplatrb :
2739 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_vsplatrb">;
2740
2741 def int_hexagon_A2_addh_h16_hh :
2742 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_hh">;
2743
2744 def int_hexagon_M2_cmpyr_s0 :
2745 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpyr_s0">;
2746
2747 def int_hexagon_M2_dpmpyss_rnd_s0 :
2748 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_rnd_s0">;
2749
2750 def int_hexagon_C2_muxri :
2751 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxri">;
2752
2753 def int_hexagon_M2_vmac2es_s0 :
2754 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es_s0">;
2755
2756 def int_hexagon_M2_vmac2es_s1 :
2757 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es_s1">;
2758
2759 def int_hexagon_C2_pxfer_map :
2760 Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_pxfer_map">;
2761
2762 def int_hexagon_M2_mpyu_lh_s1 :
2763 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_lh_s1">;
2764
2765 def int_hexagon_M2_mpyu_lh_s0 :
2766 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_lh_s0">;
2767
2768 def int_hexagon_S2_asl_i_r_or :
2769 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_or">;
2770
2771 def int_hexagon_M2_mpyd_acc_hl_s0 :
2772 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s0">;
2773
2774 def int_hexagon_M2_mpyd_acc_hl_s1 :
2775 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s1">;
2776
2777 def int_hexagon_S2_asr_r_p_nac :
2778 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_nac">;
2779
2780 def int_hexagon_A2_vaddw :
2781 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddw">;
2782
2783 def int_hexagon_S2_asr_i_r_and :
2784 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_and">;
2785
2786 def int_hexagon_A2_vaddh :
2787 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddh">;
2788
2789 def int_hexagon_M2_mpy_nac_sat_lh_s1 :
2790 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s1">;
2791
2792 def int_hexagon_M2_mpy_nac_sat_lh_s0 :
2793 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s0">;
2794
2795 def int_hexagon_C2_cmpeqp :
2796 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpeqp">;
2797
2798 def int_hexagon_M4_mpyri_addi :
2799 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addi">;
2800
2801 def int_hexagon_A2_not :
2802 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_not">;
2803
2804 def int_hexagon_S4_andi_lsr_ri :
2805 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_lsr_ri">;
2806
2807 def int_hexagon_M2_macsip :
2808 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsip">;
2809
2810 def int_hexagon_A2_tfrcrr :
2811 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfrcrr">;
2812
2813 def int_hexagon_M2_macsin :
2814 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsin">;
2815
2816 def int_hexagon_C2_orn :
2817 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_orn">;
2818
2819 def int_hexagon_M4_and_andn :
2820 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_andn">;
2821
2822 def int_hexagon_F2_sfmpy :
2823 Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmpy">;
2824
2825 def int_hexagon_M2_mpyud_nac_hh_s1 :
2826 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s1">;
2827
2828 def int_hexagon_M2_mpyud_nac_hh_s0 :
2829 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s0">;
2830
2831 def int_hexagon_S2_lsr_r_p_acc :
2832 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_acc">;
2833
2834 def int_hexagon_S2_asr_r_vw :
2835 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_vw">;
2836
2837 def int_hexagon_M4_and_or :
2838 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_or">;
2839
2840 def int_hexagon_S2_asr_r_vh :
2841 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_vh">;
2842
2843 def int_hexagon_C2_mask :
2844 Hexagon_i64_i32_Intrinsic<"HEXAGON_C2_mask">;
2845
2846 def int_hexagon_M2_mpy_nac_hh_s0 :
2847 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s0">;
2848
2849 def int_hexagon_M2_mpy_nac_hh_s1 :
2850 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s1">;
2851
2852 def int_hexagon_M2_mpy_up_s1_sat :
2853 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up_s1_sat">;
2854
2855 def int_hexagon_A4_vcmpbgt :
2856 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A4_vcmpbgt">;
2857
2858 def int_hexagon_M5_vrmacbsu :
2859 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vrmacbsu">;
2860
2861 def int_hexagon_S2_tableidxw_goodsyntax :
2862 Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxw_goodsyntax">;
2863
2864 def int_hexagon_A2_vrsadub :
2865 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vrsadub">;
2866
2867 def int_hexagon_A2_tfrrcr :
2868 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfrrcr">;
2869
2870 def int_hexagon_M2_vrcmpys_acc_s1 :
2871 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_acc_s1">;
2872
2873 def int_hexagon_F2_dfcmpge :
2874 Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpge">;
2875
2876 def int_hexagon_M2_accii :
2877 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_accii">;
2878
2879 def int_hexagon_A5_vaddhubs :
2880 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A5_vaddhubs">;
2881
2882 def int_hexagon_A2_vmaxw :
2883 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxw">;
2884
2885 def int_hexagon_A2_vmaxb :
2886 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxb">;
2887
2888 def int_hexagon_A2_vmaxh :
2889 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxh">;
2890
2891 def int_hexagon_S2_vsxthw :
2892 Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsxthw">;
2893
2894 def int_hexagon_S4_andi_asl_ri :
2895 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_asl_ri">;
2896
2897 def int_hexagon_S2_asl_i_p_nac :
2898 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_nac">;
2899
2900 def int_hexagon_S2_lsl_r_p_xor :
2901 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_xor">;
2902
2903 def int_hexagon_C2_cmpgt :
2904 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgt">;
2905
2906 def int_hexagon_F2_conv_df2d_chop :
2907 Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2d_chop">;
2908
2909 def int_hexagon_M2_mpyu_nac_hl_s0 :
2910 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s0">;
2911
2912 def int_hexagon_M2_mpyu_nac_hl_s1 :
2913 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s1">;
2914
2915 def int_hexagon_F2_conv_sf2w :
2916 Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2w">;
2917
2918 def int_hexagon_S2_lsr_r_p_or :
2919 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_or">;
2920
2921 def int_hexagon_F2_sfclass :
2922 Hexagon_i32_floati32_Intrinsic<"HEXAGON_F2_sfclass">;
2923
2924 def int_hexagon_M2_mpyud_acc_lh_s0 :
2925 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s0">;
2926
2927 def int_hexagon_M4_xor_andn :
2928 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_andn">;
2929
2930 def int_hexagon_S2_addasl_rrri :
2931 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_addasl_rrri">;
2932
2933 def int_hexagon_M5_vdmpybsu :
2934 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vdmpybsu">;
2935
2936 def int_hexagon_M2_mpyu_nac_hh_s0 :
2937 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s0">;
2938
2939 def int_hexagon_M2_mpyu_nac_hh_s1 :
2940 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s1">;
2941
2942 def int_hexagon_A2_addi :
2943 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addi">;
2944
2945 def int_hexagon_A2_addp :
2946 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_addp">;
2947
2948 def int_hexagon_M2_vmpy2s_s1pack :
2949 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s1pack">;
2950
2951 def int_hexagon_S4_clbpnorm :
2952 Hexagon_i32_i64_Intrinsic<"HEXAGON_S4_clbpnorm">;
2953
2954 def int_hexagon_A4_round_rr_sat :
2955 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_rr_sat">;
2956
2957 def int_hexagon_M2_nacci :
2958 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_nacci">;
2959
2960 def int_hexagon_S2_shuffeh :
2961 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffeh">;
2962
2963 def int_hexagon_S2_lsr_i_r_and :
2964 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_and">;
2965
2966 def int_hexagon_M2_mpy_sat_rnd_hh_s1 :
2967 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s1">;
2968
2969 def int_hexagon_M2_mpy_sat_rnd_hh_s0 :
2970 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s0">;
2971
2972 def int_hexagon_F2_conv_sf2uw :
2973 Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2uw">;
2974
2975 def int_hexagon_A2_vsubh :
2976 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubh">;
2977
2978 def int_hexagon_F2_conv_sf2ud :
2979 Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2ud">;
2980
2981 def int_hexagon_A2_vsubw :
2982 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubw">;
2983
2984 def int_hexagon_A2_vcmpwgt :
2985 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpwgt">;
2986
2987 def int_hexagon_M4_xor_or :
2988 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_or">;
2989
2990 def int_hexagon_F2_conv_sf2uw_chop :
2991 Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2uw_chop">;
2992
2993 def int_hexagon_S2_asl_r_vw :
2994 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_vw">;
2995
2996 def int_hexagon_S2_vsatwuh_nopack :
2997 Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsatwuh_nopack">;
2998
2999 def int_hexagon_S2_asl_r_vh :
3000 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_vh">;
3001
3002 def int_hexagon_A2_svsubuhs :
3003 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubuhs">;
3004
3005 def int_hexagon_M5_vmpybsu :
3006 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M5_vmpybsu">;
3007
3008 def int_hexagon_A2_subh_l16_sat_ll :
3009 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_sat_ll">;
3010
3011 def int_hexagon_C4_and_and :
3012 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_and">;
3013
3014 def int_hexagon_M2_mpyu_acc_hl_s1 :
3015 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s1">;
3016
3017 def int_hexagon_M2_mpyu_acc_hl_s0 :
3018 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s0">;
3019
3020 def int_hexagon_S2_lsr_r_p :
3021 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p">;
3022
3023 def int_hexagon_S2_lsr_r_r :
3024 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r">;
3025
3026 def int_hexagon_A4_subp_c :
3027 Hexagon_i64i32_i64i64i32_Intrinsic<"HEXAGON_A4_subp_c">;
3028
3029 def int_hexagon_A2_vsubhs :
3030 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubhs">;
3031
3032 def int_hexagon_C2_vitpack :
3033 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_vitpack">;
3034
3035 def int_hexagon_A2_vavguhr :
3036 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguhr">;
3037
3038 def int_hexagon_S2_vsplicerb :
3039 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vsplicerb">;
3040
3041 def int_hexagon_C4_nbitsclr :
3042 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsclr">;
3043
3044 def int_hexagon_A2_vcmpbgtu :
3045 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpbgtu">;
3046
3047 def int_hexagon_M2_cmpys_s1 :
3048 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpys_s1">;
3049
3050 def int_hexagon_M2_cmpys_s0 :
3051 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpys_s0">;
3052
3053 def int_hexagon_F2_dfcmpuo :
3054 Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpuo">;
3055
3056 def int_hexagon_S2_shuffob :
3057 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffob">;
3058
3059 def int_hexagon_C2_and :
3060 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_and">;
3061
3062 def int_hexagon_S5_popcountp :
3063 Hexagon_i32_i64_Intrinsic<"HEXAGON_S5_popcountp">;
3064
3065 def int_hexagon_S4_extractp :
3066 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_extractp">;
3067
3068 def int_hexagon_S2_cl0 :
3069 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_cl0">;
3070
3071 def int_hexagon_A4_vcmpbgti :
3072 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbgti">;
3073
3074 def int_hexagon_M2_mmacls_s1 :
3075 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_s1">;
3076
3077 def int_hexagon_M2_mmacls_s0 :
3078 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_s0">;
3079
3080 def int_hexagon_C4_cmpneq :
3081 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpneq">;
3082
3083 def int_hexagon_M2_vmac2es :
3084 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es">;
3085
3086 def int_hexagon_M2_vdmacs_s0 :
3087 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vdmacs_s0">;
3088
3089 def int_hexagon_M2_vdmacs_s1 :
3090 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vdmacs_s1">;
3091
3092 def int_hexagon_M2_mpyud_ll_s0 :
3093 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_ll_s0">;
3094
3095 def int_hexagon_M2_mpyud_ll_s1 :
3096 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_ll_s1">;
3097
3098 def int_hexagon_S2_clb :
3099 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_clb">;
3100
3101 def int_hexagon_M2_mpy_nac_ll_s0 :
3102 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s0">;
3103
3104 def int_hexagon_M2_mpy_nac_ll_s1 :
3105 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s1">;
3106
3107 def int_hexagon_M2_mpyd_nac_hl_s1 :
3108 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s1">;
3109
3110 def int_hexagon_M2_mpyd_nac_hl_s0 :
3111 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s0">;
3112
3113 def int_hexagon_M2_maci :
3114 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_maci">;
3115
3116 def int_hexagon_A2_vmaxuh :
3117 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxuh">;
3118
3119 def int_hexagon_A4_bitspliti :
3120 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_bitspliti">;
3121
3122 def int_hexagon_A2_vmaxub :
3123 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxub">;
3124
3125 def int_hexagon_M2_mpyud_hh_s0 :
3126 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hh_s0">;
3127
3128 def int_hexagon_M2_mpyud_hh_s1 :
3129 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hh_s1">;
3130
3131 def int_hexagon_M2_vrmac_s0 :
3132 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrmac_s0">;
3133
3134 def int_hexagon_M2_mpy_sat_lh_s0 :
3135 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s0">;
3136
3137 def int_hexagon_S2_asl_r_r_sat :
3138 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_sat">;
3139
3140 def int_hexagon_F2_conv_sf2d :
3141 Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2d">;
3142
3143 def int_hexagon_S2_asr_r_r_nac :
3144 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_nac">;
3145
3146 def int_hexagon_F2_dfimm_n :
3147 Hexagon_double_i32_Intrinsic<"HEXAGON_F2_dfimm_n">;
3148
3149 def int_hexagon_A4_cmphgt :
3150 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgt">;
3151
3152 def int_hexagon_F2_dfimm_p :
3153 Hexagon_double_i32_Intrinsic<"HEXAGON_F2_dfimm_p">;
3154
3155 def int_hexagon_M2_mpyud_acc_lh_s1 :
3156 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s1">;
3157
3158 def int_hexagon_M2_vcmpy_s1_sat_r :
3159 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_r">;
3160
3161 def int_hexagon_M4_mpyri_addr_u2 :
3162 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addr_u2">;
3163
3164 def int_hexagon_M2_vcmpy_s1_sat_i :
3165 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_i">;
3166
3167 def int_hexagon_S2_lsl_r_p_nac :
3168 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_nac">;
3169
3170 def int_hexagon_M5_vrmacbuu :
3171 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vrmacbuu">;
3172
3173 def int_hexagon_S5_asrhub_rnd_sat_goodsyntax :
3174 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S5_asrhub_rnd_sat_goodsyntax">;
3175
3176 def int_hexagon_S2_vspliceib :
3177 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vspliceib">;
3178
3179 def int_hexagon_M2_dpmpyss_acc_s0 :
3180 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_acc_s0">;
3181
3182 def int_hexagon_M2_cnacs_s1 :
3183 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacs_s1">;
3184
3185 def int_hexagon_M2_cnacs_s0 :
3186 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacs_s0">;
3187
3188 def int_hexagon_A2_maxu :
3189 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_maxu">;
3190
3191 def int_hexagon_A2_maxp :
3192 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_maxp">;
3193
3194 def int_hexagon_A2_andir :
3195 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_andir">;
3196
3197 def int_hexagon_F2_sfrecipa :
3198 Hexagon_floati32_floatfloat_Intrinsic<"HEXAGON_F2_sfrecipa">;
3199
3200 def int_hexagon_A2_combineii :
3201 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combineii">;
3202
3203 def int_hexagon_A4_orn :
3204 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_orn">;
3205
3206 def int_hexagon_A4_cmpbgtui :
3207 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgtui">;
3208
3209 def int_hexagon_S2_lsr_r_r_or :
3210 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_or">;
3211
3212 def int_hexagon_A4_vcmpbeqi :
3213 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbeqi">;
3214
3215 def int_hexagon_S2_lsl_r_r :
3216 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r">;
3217
3218 def int_hexagon_S2_lsl_r_p :
3219 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p">;
3220
3221 def int_hexagon_A2_or :
3222 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_or">;
3223
3224 def int_hexagon_F2_dfcmpeq :
3225 Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpeq">;
3226
3227 def int_hexagon_C2_cmpeq :
3228 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpeq">;
3229
3230 def int_hexagon_A2_tfrp :
3231 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_tfrp">;
3232
3233 def int_hexagon_C4_and_andn :
3234 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_andn">;
3235
3236 def int_hexagon_S2_vsathub_nopack :
3237 Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsathub_nopack">;
3238
3239 def int_hexagon_A2_satuh :
3240 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satuh">;
3241
3242 def int_hexagon_A2_satub :
3243 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satub">;
3244
3245 def int_hexagon_M2_vrcmpys_s1 :
3246 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_s1">;
3247
3248 def int_hexagon_S4_or_ori :
3249 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_ori">;
3250
3251 def int_hexagon_C4_fastcorner9_not :
3252 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_fastcorner9_not">;
3253
3254 def int_hexagon_A2_tfrih :
3255 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfrih">;
3256
3257 def int_hexagon_A2_tfril :
3258 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfril">;
3259
3260 def int_hexagon_M4_mpyri_addr :
3261 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addr">;
3262
3263 def int_hexagon_S2_vtrunehb :
3264 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vtrunehb">;
3265
3266 def int_hexagon_A2_vabsw :
3267 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabsw">;
3268
3269 def int_hexagon_A2_vabsh :
3270 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabsh">;
3271
3272 def int_hexagon_F2_sfsub :
3273 Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfsub">;
3274
3275 def int_hexagon_C2_muxii :
3276 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxii">;
3277
3278 def int_hexagon_C2_muxir :
3279 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxir">;
3280
3281 def int_hexagon_A2_swiz :
3282 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_swiz">;
3283
3284 def int_hexagon_S2_asr_i_p_and :
3285 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_and">;
3286
3287 def int_hexagon_M2_cmpyrsc_s0 :
3288 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrsc_s0">;
3289
3290 def int_hexagon_M2_cmpyrsc_s1 :
3291 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrsc_s1">;
3292
3293 def int_hexagon_A2_vraddub :
3294 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vraddub">;
3295
3296 def int_hexagon_A4_tlbmatch :
3297 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_tlbmatch">;
3298
3299 def int_hexagon_F2_conv_df2w_chop :
3300 Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2w_chop">;
3301
3302 def int_hexagon_A2_and :
3303 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_and">;
3304
3305 def int_hexagon_S2_lsr_r_p_and :
3306 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_and">;
3307
3308 def int_hexagon_M2_mpy_nac_sat_ll_s1 :
3309 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s1">;
3310
3311 def int_hexagon_M2_mpy_nac_sat_ll_s0 :
3312 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s0">;
3313
3314 def int_hexagon_S4_extract :
3315 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_extract">;
3316
3317 def int_hexagon_A2_vcmpweq :
3318 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpweq">;
3319
3320 def int_hexagon_M2_acci :
3321 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_acci">;
3322
3323 def int_hexagon_S2_lsr_i_p_acc :
3324 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_acc">;
3325
3326 def int_hexagon_S2_lsr_i_p_or :
3327 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_or">;
3328
3329 def int_hexagon_F2_conv_ud2sf :
3330 Hexagon_float_i64_Intrinsic<"HEXAGON_F2_conv_ud2sf">;
3331
3332 def int_hexagon_A2_tfr :
3333 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfr">;
3334
3335 def int_hexagon_S2_asr_i_p_or :
3336 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_or">;
3337
3338 def int_hexagon_A2_subri :
3339 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subri">;
3340
3341 def int_hexagon_A4_vrmaxuw :
3342 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxuw">;
3343
3344 def int_hexagon_M5_vmpybuu :
3345 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M5_vmpybuu">;
3346
3347 def int_hexagon_A4_vrmaxuh :
3348 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxuh">;
3349
3350 def int_hexagon_S2_asl_i_vw :
3351 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_vw">;
3352
3353 def int_hexagon_A2_vavgw :
3354 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgw">;
3355
3356 def int_hexagon_S2_brev :
3357 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_brev">;
3358
3359 def int_hexagon_A2_vavgh :
3360 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgh">;
3361
3362 def int_hexagon_S2_clrbit_i :
3363 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_clrbit_i">;
3364
3365 def int_hexagon_S2_asl_i_vh :
3366 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_vh">;
3367
3368 def int_hexagon_S2_lsr_i_r_or :
3369 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_or">;
3370
3371 def int_hexagon_S2_lsl_r_r_nac :
3372 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_nac">;
3373
3374 def int_hexagon_M2_mmpyl_rs1 :
3375 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_rs1">;
3376
3377 def int_hexagon_M2_mpyud_hl_s1 :
3378 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hl_s1">;
3379
3380 def int_hexagon_M2_mmpyl_s0 :
3381 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_s0">;
3382
3383 def int_hexagon_M2_mmpyl_s1 :
3384 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_s1">;
3385
3386 def int_hexagon_M2_naccii :
3387 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_naccii">;
3388
3389 def int_hexagon_S2_vrndpackwhs :
3390 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vrndpackwhs">;
3391
3392 def int_hexagon_S2_vtrunewh :
3393 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_vtrunewh">;
3394
3395 def int_hexagon_M2_dpmpyss_nac_s0 :
3396 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_nac_s0">;
3397
3398 def int_hexagon_M2_mpyd_ll_s0 :
3399 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_ll_s0">;
3400
3401 def int_hexagon_M2_mpyd_ll_s1 :
3402 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_ll_s1">;
3403
3404 def int_hexagon_M4_mac_up_s1_sat :
3405 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mac_up_s1_sat">;
3406
3407 def int_hexagon_S4_vrcrotate_acc :
3408 Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate_acc">;
3409
3410 def int_hexagon_F2_conv_uw2df :
3411 Hexagon_double_i32_Intrinsic<"HEXAGON_F2_conv_uw2df">;
3412
3413 def int_hexagon_A2_vaddubs :
3414 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddubs">;
3415
3416 def int_hexagon_S2_asr_r_r_acc :
3417 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_acc">;
3418
3419 def int_hexagon_A2_orir :
3420 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_orir">;
3421
3422 def int_hexagon_A2_andp :
3423 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_andp">;
3424
3425 def int_hexagon_S2_lfsp :
3426 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_lfsp">;
3427
3428 def int_hexagon_A2_min :
3429 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_min">;
3430
3431 def int_hexagon_M2_mpysmi :
3432 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysmi">;
3433
3434 def int_hexagon_M2_vcmpy_s0_sat_r :
3435 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_r">;
3436
3437 def int_hexagon_M2_mpyu_acc_ll_s1 :
3438 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s1">;
3439
3440 def int_hexagon_M2_mpyu_acc_ll_s0 :
3441 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s0">;
3442
3443 def int_hexagon_S2_asr_r_svw_trun :
3444 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S2_asr_r_svw_trun">;
3445
3446 def int_hexagon_M2_mmpyh_s0 :
3447 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_s0">;
3448
3449 def int_hexagon_M2_mmpyh_s1 :
3450 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_s1">;
3451
3452 def int_hexagon_F2_conv_sf2df :
3453 Hexagon_double_float_Intrinsic<"HEXAGON_F2_conv_sf2df">;
3454
3455 def int_hexagon_S2_vtrunohb :
3456 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vtrunohb">;
3457
3458 def int_hexagon_F2_conv_sf2d_chop :
3459 Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2d_chop">;
3460
3461 def int_hexagon_M2_mpyd_lh_s0 :
3462 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_lh_s0">;
3463
3464 def int_hexagon_F2_conv_df2w :
3465 Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2w">;
3466
3467 def int_hexagon_S5_asrhub_sat :
3468 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S5_asrhub_sat">;
3469
3470 def int_hexagon_S2_asl_i_r_xacc :
3471 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_xacc">;
3472
3473 def int_hexagon_F2_conv_df2d :
3474 Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2d">;
3475
3476 def int_hexagon_M2_mmaculs_s1 :
3477 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_s1">;
3478
3479 def int_hexagon_M2_mmaculs_s0 :
3480 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_s0">;
3481
3482 def int_hexagon_A2_svadduhs :
3483 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svadduhs">;
3484
3485 def int_hexagon_F2_conv_sf2w_chop :
3486 Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2w_chop">;
3487
3488 def int_hexagon_S2_svsathub :
3489 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_svsathub">;
3490
3491 def int_hexagon_M2_mpyd_rnd_hl_s1 :
3492 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s1">;
3493
3494 def int_hexagon_M2_mpyd_rnd_hl_s0 :
3495 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s0">;
3496
3497 def int_hexagon_S2_setbit_r :
3498 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_setbit_r">;
3499
3500 def int_hexagon_A2_vavghr :
3501 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavghr">;
3502
3503 def int_hexagon_F2_sffma_sc :
3504 Hexagon_float_floatfloatfloati32_Intrinsic<"HEXAGON_F2_sffma_sc">;
3505
3506 def int_hexagon_F2_dfclass :
3507 Hexagon_i32_doublei32_Intrinsic<"HEXAGON_F2_dfclass">;
3508
3509 def int_hexagon_F2_conv_df2ud :
3510 Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2ud">;
3511
3512 def int_hexagon_F2_conv_df2uw :
3513 Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2uw">;
3514
3515 def int_hexagon_M2_cmpyrs_s0 :
3516 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrs_s0">;
3517
3518 def int_hexagon_M2_cmpyrs_s1 :
3519 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrs_s1">;
3520
3521 def int_hexagon_C4_cmpltei :
3522 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpltei">;
3523
3524 def int_hexagon_C4_cmplteu :
3525 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplteu">;
3526
3527 def int_hexagon_A2_vsubb_map :
3528 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubb_map">;
3529
3530 def int_hexagon_A2_subh_l16_ll :
3531 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_ll">;
3532
3533 def int_hexagon_S2_asr_i_r_rnd :
3534 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd">;
3535
3536 def int_hexagon_M2_vrmpy_s0 :
3537 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrmpy_s0">;
3538
3539 def int_hexagon_M2_mpyd_rnd_hh_s1 :
3540 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s1">;
3541
3542 def int_hexagon_M2_mpyd_rnd_hh_s0 :
3543 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s0">;
3544
3545 def int_hexagon_A2_minup :
3546 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_minup">;
3547
3548 def int_hexagon_S2_valignrb :
3549 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_valignrb">;
3550
3551 def int_hexagon_S2_asr_r_p_acc :
3552 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_acc">;
3553
3554 def int_hexagon_M2_mmpyl_rs0 :
3555 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_rs0">;
3556
3557 def int_hexagon_M2_vrcmaci_s0 :
3558 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmaci_s0">;
3559
3560 def int_hexagon_A2_vaddub :
3561 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddub">;
3562
3563 def int_hexagon_A2_combine_lh :
3564 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_lh">;
3565
3566 def int_hexagon_M5_vdmacbsu :
3567 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vdmacbsu">;
3568
3569 def int_hexagon_A2_combine_ll :
3570 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_ll">;
3571
3572 def int_hexagon_M2_mpyud_hl_s0 :
3573 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hl_s0">;
3574
3575 def int_hexagon_M2_vrcmpyi_s0c :
3576 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyi_s0c">;
3577
3578 def int_hexagon_S2_asr_i_p_rnd :
3579 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_rnd">;
3580
3581 def int_hexagon_A2_addpsat :
3582 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_addpsat">;
3583
3584 def int_hexagon_A2_svaddhs :
3585 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svaddhs">;
3586
3587 def int_hexagon_S4_ori_lsr_ri :
3588 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_lsr_ri">;
3589
3590 def int_hexagon_M2_mpy_sat_rnd_ll_s1 :
3591 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s1">;
3592
3593 def int_hexagon_M2_mpy_sat_rnd_ll_s0 :
3594 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s0">;
3595
3596 def int_hexagon_A2_vminw :
3597 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminw">;
3598
3599 def int_hexagon_A2_vminh :
3600 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminh">;
3601
3602 def int_hexagon_M2_vrcmpyr_s0 :
3603 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyr_s0">;
3604
3605 def int_hexagon_A2_vminb :
3606 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminb">;
3607
3608 def int_hexagon_M2_vcmac_s0_sat_i :
3609 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_i">;
3610
3611 def int_hexagon_M2_mpyud_lh_s0 :
3612 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_lh_s0">;
3613
3614 def int_hexagon_M2_mpyud_lh_s1 :
3615 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_lh_s1">;
3616
3617 def int_hexagon_S2_asl_r_r_or :
3618 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_or">;
3619
3620 def int_hexagon_S4_lsli :
3621 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_lsli">;
3622
3623 def int_hexagon_S2_lsl_r_vw :
3624 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_vw">;
3625
3626 def int_hexagon_M2_mpy_hh_s1 :
3627 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hh_s1">;
3628
3629 def int_hexagon_M4_vrmpyeh_s0 :
3630 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_s0">;
3631
3632 def int_hexagon_M4_vrmpyeh_s1 :
3633 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_s1">;
3634
3635 def int_hexagon_M2_mpy_nac_lh_s0 :
3636 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s0">;
3637
3638 def int_hexagon_M2_mpy_nac_lh_s1 :
3639 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s1">;
3640
3641 def int_hexagon_M2_vraddh :
3642 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vraddh">;
3643
3644 def int_hexagon_C2_tfrrp :
3645 Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_tfrrp">;
3646
3647 def int_hexagon_M2_mpy_acc_sat_ll_s0 :
3648 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s0">;
3649
3650 def int_hexagon_M2_mpy_acc_sat_ll_s1 :
3651 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s1">;
3652
3653 def int_hexagon_S2_vtrunowh :
3654 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_vtrunowh">;
3655
3656 def int_hexagon_A2_abs :
3657 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_abs">;
3658
3659 def int_hexagon_A4_cmpbeq :
3660 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbeq">;
3661
3662 def int_hexagon_A2_negp :
3663 Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_negp">;
3664
3665 def int_hexagon_S2_asl_i_r_sat :
3666 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_sat">;
3667
3668 def int_hexagon_A2_addh_l16_sat_hl :
3669 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_sat_hl">;
3670
3671 def int_hexagon_S2_vsatwuh :
3672 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsatwuh">;
3673
3674 def int_hexagon_F2_dfcmpgt :
3675 Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpgt">;
3676
3677 def int_hexagon_S2_svsathb :
3678 Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_svsathb">;
3679
3680 def int_hexagon_C2_cmpgtup :
3681 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpgtup">;
3682
3683 def int_hexagon_A4_cround_ri :
3684 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cround_ri">;
3685
3686 def int_hexagon_S4_clbpaddi :
3687 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S4_clbpaddi">;
3688
3689 def int_hexagon_A4_cround_rr :
3690 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cround_rr">;
3691
3692 def int_hexagon_C2_mux :
3693 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_mux">;
3694
3695 def int_hexagon_M2_dpmpyuu_s0 :
3696 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_s0">;
3697
3698 def int_hexagon_S2_shuffeb :
3699 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffeb">;
3700
3701 def int_hexagon_A2_vminuw :
3702 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminuw">;
3703
3704 def int_hexagon_A2_vaddhs :
3705 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddhs">;
3706
3707 def int_hexagon_S2_insert_rp :
3708 Hexagon_i32_i32i32i64_Intrinsic<"HEXAGON_S2_insert_rp">;
3709
3710 def int_hexagon_A2_vminuh :
3711 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminuh">;
3712
3713 def int_hexagon_A2_vminub :
3714 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminub">;
3715
3716 def int_hexagon_S2_extractu :
3717 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_extractu">;
3718
3719 def int_hexagon_A2_svsubh :
3720 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubh">;
3721
3722 def int_hexagon_S4_clbaddi :
3723 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_clbaddi">;
3724
3725 def int_hexagon_F2_sffms :
3726 Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffms">;
3727
3728 def int_hexagon_S2_vsxtbh :
3729 Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsxtbh">;
3730
3731 def int_hexagon_M2_mpyud_nac_ll_s1 :
3732 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s1">;
3733
3734 def int_hexagon_M2_mpyud_nac_ll_s0 :
3735 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s0">;
3736
3737 def int_hexagon_A2_subp :
3738 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_subp">;
3739
3740 def int_hexagon_M2_vmpy2es_s1 :
3741 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vmpy2es_s1">;
3742
3743 def int_hexagon_M2_vmpy2es_s0 :
3744 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vmpy2es_s0">;
3745
3746 def int_hexagon_S4_parity :
3747 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_parity">;
3748
3749 def int_hexagon_M2_mpy_acc_hh_s1 :
3750 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s1">;
3751
3752 def int_hexagon_M2_mpy_acc_hh_s0 :
3753 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s0">;
3754
3755 def int_hexagon_S4_addi_asl_ri :
3756 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_asl_ri">;
3757
3758 def int_hexagon_M2_mpyd_nac_hh_s1 :
3759 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s1">;
3760
3761 def int_hexagon_M2_mpyd_nac_hh_s0 :
3762 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s0">;
3763
3764 def int_hexagon_S2_asr_i_r_nac :
3765 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_nac">;
3766
3767 def int_hexagon_A4_cmpheqi :
3768 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpheqi">;
3769
3770 def int_hexagon_S2_lsr_r_p_xor :
3771 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_xor">;
3772
3773 def int_hexagon_M2_mpy_acc_hl_s1 :
3774 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s1">;
3775
3776 def int_hexagon_M2_mpy_acc_hl_s0 :
3777 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s0">;
3778
3779 def int_hexagon_F2_conv_sf2ud_chop :
3780 Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2ud_chop">;
3781
3782 def int_hexagon_C2_cmpgeui :
3783 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgeui">;
3784
3785 def int_hexagon_M2_mpy_acc_sat_hh_s0 :
3786 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s0">;
3787
3788 def int_hexagon_M2_mpy_acc_sat_hh_s1 :
3789 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s1">;
3790
3791 def int_hexagon_S2_asl_r_p_and :
3792 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_and">;
3793
3794 def int_hexagon_A2_addh_h16_sat_lh :
3795 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_lh">;
3796
3797 def int_hexagon_A2_addh_h16_sat_ll :
3798 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_ll">;
3799
3800 def int_hexagon_M4_nac_up_s1_sat :
3801 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_nac_up_s1_sat">;
3802
3803 def int_hexagon_M2_mpyud_nac_lh_s1 :
3804 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s1">;
3805
3806 def int_hexagon_M2_mpyud_nac_lh_s0 :
3807 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s0">;
3808
3809 def int_hexagon_A4_round_ri_sat :
3810 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri_sat">;
3811
3812 def int_hexagon_M2_mpy_nac_hl_s0 :
3813 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s0">;
3814
3815 def int_hexagon_M2_mpy_nac_hl_s1 :
3816 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s1">;
3817
3818 def int_hexagon_A2_vavghcr :
3819 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavghcr">;
3820
3821 def int_hexagon_M2_mmacls_rs0 :
3822 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_rs0">;
3823
3824 def int_hexagon_M2_mmacls_rs1 :
3825 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_rs1">;
3826
3827 def int_hexagon_M2_cmaci_s0 :
3828 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmaci_s0">;
3829
3830 def int_hexagon_S2_setbit_i :
3831 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_setbit_i">;
3832
3833 def int_hexagon_S2_asl_i_p_or :
3834 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_or">;
3835
3836 def int_hexagon_A4_andn :
3837 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_andn">;
3838
3839 def int_hexagon_M5_vrmpybsu :
3840 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vrmpybsu">;
3841
3842 def int_hexagon_S2_vrndpackwh :
3843 Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vrndpackwh">;
3844
3845 def int_hexagon_M2_vcmac_s0_sat_r :
3846 Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_r">;
3847
3848 def int_hexagon_A2_vmaxuw :
3849 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxuw">;
3850
3851 def int_hexagon_C2_bitsclr :
3852 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsclr">;
3853
3854 def int_hexagon_M2_xor_xacc :
3855 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_xor_xacc">;
3856
3857 def int_hexagon_A4_vcmpbgtui :
3858 Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbgtui">;
3859
3860 def int_hexagon_A4_ornp :
3861 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A4_ornp">;
3862
3863 def int_hexagon_A2_tfrpi :
3864 Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_tfrpi">;
3865
3866 def int_hexagon_C4_and_or :
3867 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_or">;
3868
3869 def int_hexagon_M2_mpy_nac_sat_hh_s1 :
3870 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s1">;
3871
3872 def int_hexagon_M2_mpy_nac_sat_hh_s0 :
3873 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s0">;
3874
3875 def int_hexagon_A2_subh_h16_sat_ll :
3876 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_ll">;
3877
3878 def int_hexagon_A2_subh_h16_sat_lh :
3879 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_lh">;
3880
3881 def int_hexagon_M2_vmpy2su_s1 :
3882 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2su_s1">;
3883
3884 def int_hexagon_M2_vmpy2su_s0 :
3885 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2su_s0">;
3886
3887 def int_hexagon_S2_asr_i_p_acc :
3888 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_acc">;
3889
3890 def int_hexagon_C4_nbitsclri :
3891 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsclri">;
3892
3893 def int_hexagon_S2_lsr_i_vh :
3894 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vh">;
3895
3896 def int_hexagon_S2_lsr_i_p_xacc :
3897 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_xacc">;
3898
3899 // V55 Scalar Instructions.
3900
3901 def int_hexagon_A5_ACS :
3902 Hexagon_i64i32_i64i64i64_Intrinsic<"HEXAGON_A5_ACS">;
3903
3904 // V60 Scalar Instructions.
3905
3906 def int_hexagon_S6_rol_i_p_and :
3907 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_and">;
3908
3909 def int_hexagon_S6_rol_i_r_xacc :
3910 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_xacc">;
3911
3912 def int_hexagon_S6_rol_i_r_and :
3913 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_and">;
3914
3915 def int_hexagon_S6_rol_i_r_acc :
3916 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_acc">;
3917
3918 def int_hexagon_S6_rol_i_p_xacc :
3919 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_xacc">;
3920
3921 def int_hexagon_S6_rol_i_p :
3922 Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S6_rol_i_p">;
3923
3924 def int_hexagon_S6_rol_i_p_nac :
3925 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_nac">;
3926
3927 def int_hexagon_S6_rol_i_p_acc :
3928 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_acc">;
3929
3930 def int_hexagon_S6_rol_i_r_or :
3931 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_or">;
3932
3933 def int_hexagon_S6_rol_i_r :
3934 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S6_rol_i_r">;
3935
3936 def int_hexagon_S6_rol_i_r_nac :
3937 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_nac">;
3938
3939 def int_hexagon_S6_rol_i_p_or :
3940 Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_or">;
3941
3942 // V62 Scalar Instructions.
3943
3944 def int_hexagon_S6_vtrunehb_ppp :
3945 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S6_vtrunehb_ppp">;
3946
3947 def int_hexagon_V6_ldntnt0 :
3948 Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_ldntnt0">;
3949
3950 def int_hexagon_M6_vabsdiffub :
3951 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M6_vabsdiffub">;
3952
3953 def int_hexagon_S6_vtrunohb_ppp :
3954 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S6_vtrunohb_ppp">;
3955
3956 def int_hexagon_M6_vabsdiffb :
3957 Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M6_vabsdiffb">;
3958
3959 def int_hexagon_A6_vminub_RdP :
3960 Hexagon_i64i32_i64i64_Intrinsic<"HEXAGON_A6_vminub_RdP">;
3961
3962 def int_hexagon_S6_vsplatrbp :
3963 Hexagon_i64_i32_Intrinsic<"HEXAGON_S6_vsplatrbp">;
3964
3965 // V65 Scalar Instructions.
3966
3967 def int_hexagon_A6_vcmpbeq_notany :
3968 Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A6_vcmpbeq_notany">;
3969
3970 // V66 Scalar Instructions.
3971
3972 def int_hexagon_F2_dfsub :
3973 Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfsub">;
3974
3975 def int_hexagon_F2_dfadd :
3976 Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfadd">;
3977
3978 def int_hexagon_M2_mnaci :
3979 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mnaci">;
3980
3981 def int_hexagon_S2_mask :
3982 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_mask">;
3983
3984 // V60 HVX Instructions.
3985
3986 def int_hexagon_V6_veqb_or :
3987 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_or">;
3988
3989 def int_hexagon_V6_veqb_or_128B :
3990 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_or_128B">;
3991
3992 def int_hexagon_V6_vminub :
3993 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminub">;
3994
3995 def int_hexagon_V6_vminub_128B :
3996 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminub_128B">;
3997
3998 def int_hexagon_V6_vaslw_acc :
3999 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vaslw_acc">;
4000
4001 def int_hexagon_V6_vaslw_acc_128B :
4002 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vaslw_acc_128B">;
4003
4004 def int_hexagon_V6_vmpyhvsrs :
4005 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhvsrs">;
4006
4007 def int_hexagon_V6_vmpyhvsrs_128B :
4008 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhvsrs_128B">;
4009
4010 def int_hexagon_V6_vsathub :
4011 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsathub">;
4012
4013 def int_hexagon_V6_vsathub_128B :
4014 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsathub_128B">;
4015
4016 def int_hexagon_V6_vaddh_dv :
4017 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddh_dv">;
4018
4019 def int_hexagon_V6_vaddh_dv_128B :
4020 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddh_dv_128B">;
4021
4022 def int_hexagon_V6_vrmpybusi :
4023 Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi">;
4024
4025 def int_hexagon_V6_vrmpybusi_128B :
4026 Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_128B">;
4027
4028 def int_hexagon_V6_vshufoh :
4029 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoh">;
4030
4031 def int_hexagon_V6_vshufoh_128B :
4032 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoh_128B">;
4033
4034 def int_hexagon_V6_vasrwv :
4035 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vasrwv">;
4036
4037 def int_hexagon_V6_vasrwv_128B :
4038 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vasrwv_128B">;
4039
4040 def int_hexagon_V6_vdmpyhsuisat :
4041 Hexagon_v16i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat">;
4042
4043 def int_hexagon_V6_vdmpyhsuisat_128B :
4044 Hexagon_v32i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_128B">;
4045
4046 def int_hexagon_V6_vrsadubi_acc :
4047 Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_acc">;
4048
4049 def int_hexagon_V6_vrsadubi_acc_128B :
4050 Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_acc_128B">;
4051
4052 def int_hexagon_V6_vnavgw :
4053 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgw">;
4054
4055 def int_hexagon_V6_vnavgw_128B :
4056 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgw_128B">;
4057
4058 def int_hexagon_V6_vnavgh :
4059 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgh">;
4060
4061 def int_hexagon_V6_vnavgh_128B :
4062 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgh_128B">;
4063
4064 def int_hexagon_V6_vavgub :
4065 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgub">;
4066
4067 def int_hexagon_V6_vavgub_128B :
4068 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgub_128B">;
4069
4070 def int_hexagon_V6_vsubb :
4071 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubb">;
4072
4073 def int_hexagon_V6_vsubb_128B :
4074 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubb_128B">;
4075
4076 def int_hexagon_V6_vgtw_and :
4077 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw_and">;
4078
4079 def int_hexagon_V6_vgtw_and_128B :
4080 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_and_128B">;
4081
4082 def int_hexagon_V6_vavgubrnd :
4083 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgubrnd">;
4084
4085 def int_hexagon_V6_vavgubrnd_128B :
4086 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgubrnd_128B">;
4087
4088 def int_hexagon_V6_vrmpybusv :
4089 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybusv">;
4090
4091 def int_hexagon_V6_vrmpybusv_128B :
4092 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybusv_128B">;
4093
4094 def int_hexagon_V6_vsubbnq :
4095 Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbnq">;
4096
4097 def int_hexagon_V6_vsubbnq_128B :
4098 Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbnq_128B">;
4099
4100 def int_hexagon_V6_vroundhb :
4101 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundhb">;
4102
4103 def int_hexagon_V6_vroundhb_128B :
4104 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundhb_128B">;
4105
4106 def int_hexagon_V6_vadduhsat_dv :
4107 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhsat_dv">;
4108
4109 def int_hexagon_V6_vadduhsat_dv_128B :
4110 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vadduhsat_dv_128B">;
4111
4112 def int_hexagon_V6_vsububsat :
4113 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsububsat">;
4114
4115 def int_hexagon_V6_vsububsat_128B :
4116 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububsat_128B">;
4117
4118 def int_hexagon_V6_vmpabus_acc :
4119 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpabus_acc">;
4120
4121 def int_hexagon_V6_vmpabus_acc_128B :
4122 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpabus_acc_128B">;
4123
4124 def int_hexagon_V6_vmux :
4125 Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vmux">;
4126
4127 def int_hexagon_V6_vmux_128B :
4128 Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vmux_128B">;
4129
4130 def int_hexagon_V6_vmpyhus :
4131 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhus">;
4132
4133 def int_hexagon_V6_vmpyhus_128B :
4134 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhus_128B">;
4135
4136 def int_hexagon_V6_vpackeb :
4137 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackeb">;
4138
4139 def int_hexagon_V6_vpackeb_128B :
4140 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackeb_128B">;
4141
4142 def int_hexagon_V6_vsubhnq :
4143 Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhnq">;
4144
4145 def int_hexagon_V6_vsubhnq_128B :
4146 Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhnq_128B">;
4147
4148 def int_hexagon_V6_vavghrnd :
4149 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavghrnd">;
4150
4151 def int_hexagon_V6_vavghrnd_128B :
4152 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavghrnd_128B">;
4153
4154 def int_hexagon_V6_vtran2x2_map :
4155 Hexagon_v16i32v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vtran2x2_map">;
4156
4157 def int_hexagon_V6_vtran2x2_map_128B :
4158 Hexagon_v32i32v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtran2x2_map_128B">;
4159
4160 def int_hexagon_V6_vdelta :
4161 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdelta">;
4162
4163 def int_hexagon_V6_vdelta_128B :
4164 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdelta_128B">;
4165
4166 def int_hexagon_V6_vgtuh_and :
4167 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh_and">;
4168
4169 def int_hexagon_V6_vgtuh_and_128B :
4170 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_and_128B">;
4171
4172 def int_hexagon_V6_vtmpyhb :
4173 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb">;
4174
4175 def int_hexagon_V6_vtmpyhb_128B :
4176 Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_128B">;
4177
4178 def int_hexagon_V6_vpackob :
4179 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackob">;
4180
4181 def int_hexagon_V6_vpackob_128B :
4182 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackob_128B">;
4183
4184 def int_hexagon_V6_vmaxh :
4185 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxh">;
4186
4187 def int_hexagon_V6_vmaxh_128B :
4188 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxh_128B">;
4189
4190 def int_hexagon_V6_vtmpybus_acc :
4191 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_acc">;
4192
4193 def int_hexagon_V6_vtmpybus_acc_128B :
4194 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_acc_128B">;
4195
4196 def int_hexagon_V6_vsubuhsat :
4197 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuhsat">;
4198
4199 def int_hexagon_V6_vsubuhsat_128B :
4200 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhsat_128B">;
4201
4202 def int_hexagon_V6_vasrw_acc :
4203 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrw_acc">;
4204
4205 def int_hexagon_V6_vasrw_acc_128B :
4206 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrw_acc_128B">;
4207
4208 def int_hexagon_V6_pred_or :
4209 Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_pred_or">;
4210
4211 def int_hexagon_V6_pred_or_128B :
4212 Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_pred_or_128B">;
4213
4214 def int_hexagon_V6_vrmpyub_acc :
4215 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_acc">;
4216
4217 def int_hexagon_V6_vrmpyub_acc_128B :
4218 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_acc_128B">;
4219
4220 def int_hexagon_V6_lo :
4221 Hexagon_v16i32_v32i32_Intrinsic<"HEXAGON_V6_lo">;
4222
4223 def int_hexagon_V6_lo_128B :
4224 Hexagon_v32i32_v64i32_Intrinsic<"HEXAGON_V6_lo_128B">;
4225
4226 def int_hexagon_V6_vsubb_dv :
4227 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubb_dv">;
4228
4229 def int_hexagon_V6_vsubb_dv_128B :
4230 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubb_dv_128B">;
4231
4232 def int_hexagon_V6_vsubhsat_dv :
4233 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhsat_dv">;
4234
4235 def int_hexagon_V6_vsubhsat_dv_128B :
4236 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubhsat_dv_128B">;
4237
4238 def int_hexagon_V6_vmpyiwh :
4239 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh">;
4240
4241 def int_hexagon_V6_vmpyiwh_128B :
4242 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_128B">;
4243
4244 def int_hexagon_V6_vmpyiwb :
4245 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb">;
4246
4247 def int_hexagon_V6_vmpyiwb_128B :
4248 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_128B">;
4249
4250 def int_hexagon_V6_ldu0 :
4251 Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_ldu0">;
4252
4253 def int_hexagon_V6_ldu0_128B :
4254 Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_ldu0_128B">;
4255
4256 def int_hexagon_V6_vgtuh_xor :
4257 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh_xor">;
4258
4259 def int_hexagon_V6_vgtuh_xor_128B :
4260 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_xor_128B">;
4261
4262 def int_hexagon_V6_vgth_or :
4263 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth_or">;
4264
4265 def int_hexagon_V6_vgth_or_128B :
4266 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_or_128B">;
4267
4268 def int_hexagon_V6_vavgh :
4269 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgh">;
4270
4271 def int_hexagon_V6_vavgh_128B :
4272 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgh_128B">;
4273
4274 def int_hexagon_V6_vlalignb :
4275 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlalignb">;
4276
4277 def int_hexagon_V6_vlalignb_128B :
4278 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlalignb_128B">;
4279
4280 def int_hexagon_V6_vsh :
4281 Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vsh">;
4282
4283 def int_hexagon_V6_vsh_128B :
4284 Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vsh_128B">;
4285
4286 def int_hexagon_V6_pred_and_n :
4287 Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_pred_and_n">;
4288
4289 def int_hexagon_V6_pred_and_n_128B :
4290 Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_pred_and_n_128B">;
4291
4292 def int_hexagon_V6_vsb :
4293 Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vsb">;
4294
4295 def int_hexagon_V6_vsb_128B :
4296 Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vsb_128B">;
4297
4298 def int_hexagon_V6_vroundwuh :
4299 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundwuh">;
4300
4301 def int_hexagon_V6_vroundwuh_128B :
4302 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundwuh_128B">;
4303
4304 def int_hexagon_V6_vasrhv :
4305 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vasrhv">;
4306
4307 def int_hexagon_V6_vasrhv_128B :
4308 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vasrhv_128B">;
4309
4310 def int_hexagon_V6_vshuffh :
4311 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vshuffh">;
4312
4313 def int_hexagon_V6_vshuffh_128B :
4314 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vshuffh_128B">;
4315
4316 def int_hexagon_V6_vaddhsat_dv :
4317 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhsat_dv">;
4318
4319 def int_hexagon_V6_vaddhsat_dv_128B :
4320 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddhsat_dv_128B">;
4321
4322 def int_hexagon_V6_vnavgub :
4323 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgub">;
4324
4325 def int_hexagon_V6_vnavgub_128B :
4326 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgub_128B">;
4327
4328 def int_hexagon_V6_vrmpybv :
4329 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybv">;
4330
4331 def int_hexagon_V6_vrmpybv_128B :
4332 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybv_128B">;
4333
4334 def int_hexagon_V6_vnormamth :
4335 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnormamth">;
4336
4337 def int_hexagon_V6_vnormamth_128B :
4338 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnormamth_128B">;
4339
4340 def int_hexagon_V6_vdmpyhb :
4341 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb">;
4342
4343 def int_hexagon_V6_vdmpyhb_128B :
4344 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_128B">;
4345
4346 def int_hexagon_V6_vavguh :
4347 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguh">;
4348
4349 def int_hexagon_V6_vavguh_128B :
4350 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguh_128B">;
4351
4352 def int_hexagon_V6_vlsrwv :
4353 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vlsrwv">;
4354
4355 def int_hexagon_V6_vlsrwv_128B :
4356 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vlsrwv_128B">;
4357
4358 def int_hexagon_V6_vlsrhv :
4359 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vlsrhv">;
4360
4361 def int_hexagon_V6_vlsrhv_128B :
4362 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vlsrhv_128B">;
4363
4364 def int_hexagon_V6_vdmpyhisat :
4365 Hexagon_v16i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat">;
4366
4367 def int_hexagon_V6_vdmpyhisat_128B :
4368 Hexagon_v32i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_128B">;
4369
4370 def int_hexagon_V6_vdmpyhvsat :
4371 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat">;
4372
4373 def int_hexagon_V6_vdmpyhvsat_128B :
4374 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_128B">;
4375
4376 def int_hexagon_V6_vaddw :
4377 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddw">;
4378
4379 def int_hexagon_V6_vaddw_128B :
4380 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddw_128B">;
4381
4382 def int_hexagon_V6_vzh :
4383 Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vzh">;
4384
4385 def int_hexagon_V6_vzh_128B :
4386 Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vzh_128B">;
4387
4388 def int_hexagon_V6_vaddh :
4389 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddh">;
4390
4391 def int_hexagon_V6_vaddh_128B :
4392 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddh_128B">;
4393
4394 def int_hexagon_V6_vmaxub :
4395 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxub">;
4396
4397 def int_hexagon_V6_vmaxub_128B :
4398 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxub_128B">;
4399
4400 def int_hexagon_V6_vmpyhv_acc :
4401 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhv_acc">;
4402
4403 def int_hexagon_V6_vmpyhv_acc_128B :
4404 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhv_acc_128B">;
4405
4406 def int_hexagon_V6_vadduhsat :
4407 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhsat">;
4408
4409 def int_hexagon_V6_vadduhsat_128B :
4410 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhsat_128B">;
4411
4412 def int_hexagon_V6_vshufoeh :
4413 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoeh">;
4414
4415 def int_hexagon_V6_vshufoeh_128B :
4416 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoeh_128B">;
4417
4418 def int_hexagon_V6_vmpyuhv_acc :
4419 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhv_acc">;
4420
4421 def int_hexagon_V6_vmpyuhv_acc_128B :
4422 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhv_acc_128B">;
4423
4424 def int_hexagon_V6_veqh :
4425 Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh">;
4426
4427 def int_hexagon_V6_veqh_128B :
4428 Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_128B">;
4429
4430 def int_hexagon_V6_vmpabuuv :
4431 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpabuuv">;
4432
4433 def int_hexagon_V6_vmpabuuv_128B :
4434 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vmpabuuv_128B">;
4435
4436 def int_hexagon_V6_vasrwhsat :
4437 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwhsat">;
4438
4439 def int_hexagon_V6_vasrwhsat_128B :
4440 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwhsat_128B">;
4441
4442 def int_hexagon_V6_vminuh :
4443 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminuh">;
4444
4445 def int_hexagon_V6_vminuh_128B :
4446 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminuh_128B">;
4447
4448 def int_hexagon_V6_vror :
4449 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vror">;
4450
4451 def int_hexagon_V6_vror_128B :
4452 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vror_128B">;
4453
4454 def int_hexagon_V6_vmpyowh_rnd_sacc :
4455 Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc">;
4456
4457 def int_hexagon_V6_vmpyowh_rnd_sacc_128B :
4458 Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc_128B">;
4459
4460 def int_hexagon_V6_vmaxuh :
4461 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxuh">;
4462
4463 def int_hexagon_V6_vmaxuh_128B :
4464 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxuh_128B">;
4465
4466 def int_hexagon_V6_vabsh_sat :
4467 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsh_sat">;
4468
4469 def int_hexagon_V6_vabsh_sat_128B :
4470 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsh_sat_128B">;
4471
4472 def int_hexagon_V6_pred_or_n :
4473 Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_pred_or_n">;
4474
4475 def int_hexagon_V6_pred_or_n_128B :
4476 Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_pred_or_n_128B">;
4477
4478 def int_hexagon_V6_vdealb :
4479 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vdealb">;
4480
4481 def int_hexagon_V6_vdealb_128B :
4482 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vdealb_128B">;
4483
4484 def int_hexagon_V6_vmpybusv :
4485 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybusv">;
4486
4487 def int_hexagon_V6_vmpybusv_128B :
4488 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybusv_128B">;
4489
4490 def int_hexagon_V6_vzb :
4491 Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vzb">;
4492
4493 def int_hexagon_V6_vzb_128B :
4494 Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vzb_128B">;
4495
4496 def int_hexagon_V6_vdmpybus_dv :
4497 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv">;
4498
4499 def int_hexagon_V6_vdmpybus_dv_128B :
4500 Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_128B">;
4501
4502 def int_hexagon_V6_vaddbq :
4503 Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbq">;
4504
4505 def int_hexagon_V6_vaddbq_128B :
4506 Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbq_128B">;
4507
4508 def int_hexagon_V6_vaddb :
4509 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddb">;
4510
4511 def int_hexagon_V6_vaddb_128B :
4512 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddb_128B">;
4513
4514 def int_hexagon_V6_vaddwq :
4515 Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwq">;
4516
4517 def int_hexagon_V6_vaddwq_128B :
4518 Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwq_128B">;
4519
4520 def int_hexagon_V6_vasrhubrndsat :
4521 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhubrndsat">;
4522
4523 def int_hexagon_V6_vasrhubrndsat_128B :
4524 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhubrndsat_128B">;
4525
4526 def int_hexagon_V6_vasrhubsat :
4527 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhubsat">;
4528
4529 def int_hexagon_V6_vasrhubsat_128B :
4530 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhubsat_128B">;
4531
4532 def int_hexagon_V6_vshufoeb :
4533 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoeb">;
4534
4535 def int_hexagon_V6_vshufoeb_128B :
4536 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoeb_128B">;
4537
4538 def int_hexagon_V6_vpackhub_sat :
4539 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackhub_sat">;
4540
4541 def int_hexagon_V6_vpackhub_sat_128B :
4542 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackhub_sat_128B">;
4543
4544 def int_hexagon_V6_vmpyiwh_acc :
4545 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_acc">;
4546
4547 def int_hexagon_V6_vmpyiwh_acc_128B :
4548 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_acc_128B">;
4549
4550 def int_hexagon_V6_vtmpyb :
4551 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyb">;
4552
4553 def int_hexagon_V6_vtmpyb_128B :
4554 Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_128B">;
4555
4556 def int_hexagon_V6_vmpabusv :
4557 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpabusv">;
4558
4559 def int_hexagon_V6_vmpabusv_128B :
4560 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vmpabusv_128B">;
4561
4562 def int_hexagon_V6_pred_and :
4563 Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_pred_and">;
4564
4565 def int_hexagon_V6_pred_and_128B :
4566 Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_pred_and_128B">;
4567
4568 def int_hexagon_V6_vsubwnq :
4569 Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwnq">;
4570
4571 def int_hexagon_V6_vsubwnq_128B :
4572 Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwnq_128B">;
4573
4574 def int_hexagon_V6_vpackwuh_sat :
4575 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackwuh_sat">;
4576
4577 def int_hexagon_V6_vpackwuh_sat_128B :
4578 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackwuh_sat_128B">;
4579
4580 def int_hexagon_V6_vswap :
4581 Hexagon_v32i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vswap">;
4582
4583 def int_hexagon_V6_vswap_128B :
4584 Hexagon_v64i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vswap_128B">;
4585
4586 def int_hexagon_V6_vrmpyubv_acc :
4587 Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpyubv_acc">;
4588
4589 def int_hexagon_V6_vrmpyubv_acc_128B :
4590 Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpyubv_acc_128B">;
4591
4592 def int_hexagon_V6_vgtb_and :
4593 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb_and">;
4594
4595 def int_hexagon_V6_vgtb_and_128B :
4596 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_and_128B">;
4597
4598 def int_hexagon_V6_vaslw :
4599 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vaslw">;
4600
4601 def int_hexagon_V6_vaslw_128B :
4602 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vaslw_128B">;
4603
4604 def int_hexagon_V6_vpackhb_sat :
4605 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackhb_sat">;
4606
4607 def int_hexagon_V6_vpackhb_sat_128B :
4608 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackhb_sat_128B">;
4609
4610 def int_hexagon_V6_vmpyih_acc :
4611 Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyih_acc">;
4612
4613 def int_hexagon_V6_vmpyih_acc_128B :
4614 Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyih_acc_128B">;
4615
4616 def int_hexagon_V6_vshuffvdd :
4617 Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vshuffvdd">;
4618
4619 def int_hexagon_V6_vshuffvdd_128B :
4620 Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vshuffvdd_128B">;
4621
4622 def int_hexagon_V6_vaddb_dv :
4623 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddb_dv">;
4624
4625 def int_hexagon_V6_vaddb_dv_128B :
4626 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddb_dv_128B">;
4627
4628 def int_hexagon_V6_vunpackub :
4629 Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackub">;
4630
4631 def int_hexagon_V6_vunpackub_128B :
4632 Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackub_128B">;
4633
4634 def int_hexagon_V6_vgtuw :
4635 Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw">;
4636
4637 def int_hexagon_V6_vgtuw_128B :
4638 Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_128B">;
4639
4640 def int_hexagon_V6_vlutvwh :
4641 Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh">;
4642
4643 def int_hexagon_V6_vlutvwh_128B :
4644 Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_128B">;
4645
4646 def int_hexagon_V6_vgtub :
4647 Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub">;
4648
4649 def int_hexagon_V6_vgtub_128B :
4650 Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_128B">;
4651
4652 def int_hexagon_V6_vmpyowh :
4653 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh">;
4654
4655 def int_hexagon_V6_vmpyowh_128B :
4656 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_128B">;
4657
4658 def int_hexagon_V6_vmpyieoh :
4659 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyieoh">;
4660
4661 def int_hexagon_V6_vmpyieoh_128B :
4662 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyieoh_128B">;
4663
4664 def int_hexagon_V6_extractw :
4665 Hexagon_i32_v16i32i32_Intrinsic<"HEXAGON_V6_extractw">;
4666
4667 def int_hexagon_V6_extractw_128B :
4668 Hexagon_i32_v32i32i32_Intrinsic<"HEXAGON_V6_extractw_128B">;
4669
4670 def int_hexagon_V6_vavgwrnd :
4671 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgwrnd">;
4672
4673 def int_hexagon_V6_vavgwrnd_128B :
4674 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgwrnd_128B">;
4675
4676 def int_hexagon_V6_vdmpyhsat_acc :
4677 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_acc">;
4678
4679 def int_hexagon_V6_vdmpyhsat_acc_128B :
4680 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_acc_128B">;
4681
4682 def int_hexagon_V6_vgtub_xor :
4683 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub_xor">;
4684
4685 def int_hexagon_V6_vgtub_xor_128B :
4686 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_xor_128B">;
4687
4688 def int_hexagon_V6_vmpyub :
4689 Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyub">;
4690
4691 def int_hexagon_V6_vmpyub_128B :
4692 Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyub_128B">;
4693
4694 def int_hexagon_V6_vmpyuh :
4695 Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuh">;
4696
4697 def int_hexagon_V6_vmpyuh_128B :
4698 Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_128B">;
4699
4700 def int_hexagon_V6_vunpackob :
4701 Hexagon_v32i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vunpackob">;
4702
4703 def int_hexagon_V6_vunpackob_128B :
4704 Hexagon_v64i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vunpackob_128B">;
4705
4706 def int_hexagon_V6_vmpahb :
4707 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpahb">;
4708
4709 def int_hexagon_V6_vmpahb_128B :
4710 Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpahb_128B">;
4711
4712 def int_hexagon_V6_veqw_or :
4713 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw_or">;
4714
4715 def int_hexagon_V6_veqw_or_128B :
4716 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_or_128B">;
4717
4718 def int_hexagon_V6_vandqrt :
4719 Hexagon_v16i32_v512i1i32_Intrinsic<"HEXAGON_V6_vandqrt">;
4720
4721 def int_hexagon_V6_vandqrt_128B :
4722 Hexagon_v32i32_v1024i1i32_Intrinsic<"HEXAGON_V6_vandqrt_128B">;
4723
4724 def int_hexagon_V6_vxor :
4725 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vxor">;
4726
4727 def int_hexagon_V6_vxor_128B :
4728 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vxor_128B">;
4729
4730 def int_hexagon_V6_vasrwhrndsat :
4731 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwhrndsat">;
4732
4733 def int_hexagon_V6_vasrwhrndsat_128B :
4734 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwhrndsat_128B">;
4735
4736 def int_hexagon_V6_vmpyhsat_acc :
4737 Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhsat_acc">;
4738
4739 def int_hexagon_V6_vmpyhsat_acc_128B :
4740 Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhsat_acc_128B">;
4741
4742 def int_hexagon_V6_vrmpybus_acc :
4743 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_acc">;
4744
4745 def int_hexagon_V6_vrmpybus_acc_128B :
4746 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_acc_128B">;
4747
4748 def int_hexagon_V6_vsubhw :
4749 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhw">;
4750
4751 def int_hexagon_V6_vsubhw_128B :
4752 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhw_128B">;
4753
4754 def int_hexagon_V6_vdealb4w :
4755 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdealb4w">;
4756
4757 def int_hexagon_V6_vdealb4w_128B :
4758 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdealb4w_128B">;
4759
4760 def int_hexagon_V6_vmpyowh_sacc :
4761 Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_sacc">;
4762
4763 def int_hexagon_V6_vmpyowh_sacc_128B :
4764 Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_sacc_128B">;
4765
4766 def int_hexagon_V6_vmpybv :
4767 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybv">;
4768
4769 def int_hexagon_V6_vmpybv_128B :
4770 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybv_128B">;
4771
4772 def int_hexagon_V6_vabsdiffh :
4773 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffh">;
4774
4775 def int_hexagon_V6_vabsdiffh_128B :
4776 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffh_128B">;
4777
4778 def int_hexagon_V6_vshuffob :
4779 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshuffob">;
4780
4781 def int_hexagon_V6_vshuffob_128B :
4782 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshuffob_128B">;
4783
4784 def int_hexagon_V6_vmpyub_acc :
4785 Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyub_acc">;
4786
4787 def int_hexagon_V6_vmpyub_acc_128B :
4788 Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyub_acc_128B">;
4789
4790 def int_hexagon_V6_vnormamtw :
4791 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnormamtw">;
4792
4793 def int_hexagon_V6_vnormamtw_128B :
4794 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnormamtw_128B">;
4795
4796 def int_hexagon_V6_vunpackuh :
4797 Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackuh">;
4798
4799 def int_hexagon_V6_vunpackuh_128B :
4800 Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackuh_128B">;
4801
4802 def int_hexagon_V6_vgtuh_or :
4803 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh_or">;
4804
4805 def int_hexagon_V6_vgtuh_or_128B :
4806 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_or_128B">;
4807
4808 def int_hexagon_V6_vmpyiewuh_acc :
4809 Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc">;
4810
4811 def int_hexagon_V6_vmpyiewuh_acc_128B :
4812 Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc_128B">;
4813
4814 def int_hexagon_V6_vunpackoh :
4815 Hexagon_v32i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vunpackoh">;
4816
4817 def int_hexagon_V6_vunpackoh_128B :
4818 Hexagon_v64i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vunpackoh_128B">;
4819
4820 def int_hexagon_V6_vdmpyhsat :
4821 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat">;
4822
4823 def int_hexagon_V6_vdmpyhsat_128B :
4824 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_128B">;
4825
4826 def int_hexagon_V6_vmpyubv :
4827 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyubv">;
4828
4829 def int_hexagon_V6_vmpyubv_128B :
4830 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyubv_128B">;
4831
4832 def int_hexagon_V6_vmpyhss :
4833 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhss">;
4834
4835 def int_hexagon_V6_vmpyhss_128B :
4836 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhss_128B">;
4837
4838 def int_hexagon_V6_hi :
4839 Hexagon_v16i32_v32i32_Intrinsic<"HEXAGON_V6_hi">;
4840
4841 def int_hexagon_V6_hi_128B :
4842 Hexagon_v32i32_v64i32_Intrinsic<"HEXAGON_V6_hi_128B">;
4843
4844 def int_hexagon_V6_vasrwuhsat :
4845 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwuhsat">;
4846
4847 def int_hexagon_V6_vasrwuhsat_128B :
4848 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwuhsat_128B">;
4849
4850 def int_hexagon_V6_veqw :
4851 Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw">;
4852
4853 def int_hexagon_V6_veqw_128B :
4854 Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_128B">;
4855
4856 def int_hexagon_V6_vdsaduh :
4857 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdsaduh">;
4858
4859 def int_hexagon_V6_vdsaduh_128B :
4860 Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_128B">;
4861
4862 def int_hexagon_V6_vsubw :
4863 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubw">;
4864
4865 def int_hexagon_V6_vsubw_128B :
4866 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubw_128B">;
4867
4868 def int_hexagon_V6_vsubw_dv :
4869 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubw_dv">;
4870
4871 def int_hexagon_V6_vsubw_dv_128B :
4872 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubw_dv_128B">;
4873
4874 def int_hexagon_V6_veqb_and :
4875 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_and">;
4876
4877 def int_hexagon_V6_veqb_and_128B :
4878 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_and_128B">;
4879
4880 def int_hexagon_V6_vmpyih :
4881 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyih">;
4882
4883 def int_hexagon_V6_vmpyih_128B :
4884 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyih_128B">;
4885
4886 def int_hexagon_V6_vtmpyb_acc :
4887 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_acc">;
4888
4889 def int_hexagon_V6_vtmpyb_acc_128B :
4890 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_acc_128B">;
4891
4892 def int_hexagon_V6_vrmpybus :
4893 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vrmpybus">;
4894
4895 def int_hexagon_V6_vrmpybus_128B :
4896 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_128B">;
4897
4898 def int_hexagon_V6_vmpybus_acc :
4899 Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpybus_acc">;
4900
4901 def int_hexagon_V6_vmpybus_acc_128B :
4902 Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpybus_acc_128B">;
4903
4904 def int_hexagon_V6_vgth_xor :
4905 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth_xor">;
4906
4907 def int_hexagon_V6_vgth_xor_128B :
4908 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_xor_128B">;
4909
4910 def int_hexagon_V6_vsubhsat :
4911 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhsat">;
4912
4913 def int_hexagon_V6_vsubhsat_128B :
4914 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhsat_128B">;
4915
4916 def int_hexagon_V6_vrmpyubi_acc :
4917 Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_acc">;
4918
4919 def int_hexagon_V6_vrmpyubi_acc_128B :
4920 Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_acc_128B">;
4921
4922 def int_hexagon_V6_vabsw :
4923 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsw">;
4924
4925 def int_hexagon_V6_vabsw_128B :
4926 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsw_128B">;
4927
4928 def int_hexagon_V6_vaddwsat_dv :
4929 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwsat_dv">;
4930
4931 def int_hexagon_V6_vaddwsat_dv_128B :
4932 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddwsat_dv_128B">;
4933
4934 def int_hexagon_V6_vlsrw :
4935 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrw">;
4936
4937 def int_hexagon_V6_vlsrw_128B :
4938 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrw_128B">;
4939
4940 def int_hexagon_V6_vabsh :
4941 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsh">;
4942
4943 def int_hexagon_V6_vabsh_128B :
4944 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsh_128B">;
4945
4946 def int_hexagon_V6_vlsrh :
4947 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrh">;
4948
4949 def int_hexagon_V6_vlsrh_128B :
4950 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrh_128B">;
4951
4952 def int_hexagon_V6_valignb :
4953 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_valignb">;
4954
4955 def int_hexagon_V6_valignb_128B :
4956 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_valignb_128B">;
4957
4958 def int_hexagon_V6_vsubhq :
4959 Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhq">;
4960
4961 def int_hexagon_V6_vsubhq_128B :
4962 Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhq_128B">;
4963
4964 def int_hexagon_V6_vpackoh :
4965 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackoh">;
4966
4967 def int_hexagon_V6_vpackoh_128B :
4968 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackoh_128B">;
4969
4970 def int_hexagon_V6_vdmpybus_acc :
4971 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_acc">;
4972
4973 def int_hexagon_V6_vdmpybus_acc_128B :
4974 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_acc_128B">;
4975
4976 def int_hexagon_V6_vdmpyhvsat_acc :
4977 Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc">;
4978
4979 def int_hexagon_V6_vdmpyhvsat_acc_128B :
4980 Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc_128B">;
4981
4982 def int_hexagon_V6_vrmpybv_acc :
4983 Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybv_acc">;
4984
4985 def int_hexagon_V6_vrmpybv_acc_128B :
4986 Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybv_acc_128B">;
4987
4988 def int_hexagon_V6_vaddhsat :
4989 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhsat">;
4990
4991 def int_hexagon_V6_vaddhsat_128B :
4992 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhsat_128B">;
4993
4994 def int_hexagon_V6_vcombine :
4995 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcombine">;
4996
4997 def int_hexagon_V6_vcombine_128B :
4998 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcombine_128B">;
4999
5000 def int_hexagon_V6_vandqrt_acc :
5001 Hexagon_v16i32_v16i32v512i1i32_Intrinsic<"HEXAGON_V6_vandqrt_acc">;
5002
5003 def int_hexagon_V6_vandqrt_acc_128B :
5004 Hexagon_v32i32_v32i32v1024i1i32_Intrinsic<"HEXAGON_V6_vandqrt_acc_128B">;
5005
5006 def int_hexagon_V6_vaslhv :
5007 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaslhv">;
5008
5009 def int_hexagon_V6_vaslhv_128B :
5010 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaslhv_128B">;
5011
5012 def int_hexagon_V6_vinsertwr :
5013 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vinsertwr">;
5014
5015 def int_hexagon_V6_vinsertwr_128B :
5016 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vinsertwr_128B">;
5017
5018 def int_hexagon_V6_vsubh_dv :
5019 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubh_dv">;
5020
5021 def int_hexagon_V6_vsubh_dv_128B :
5022 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubh_dv_128B">;
5023
5024 def int_hexagon_V6_vshuffb :
5025 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vshuffb">;
5026
5027 def int_hexagon_V6_vshuffb_128B :
5028 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vshuffb_128B">;
5029
5030 def int_hexagon_V6_vand :
5031 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vand">;
5032
5033 def int_hexagon_V6_vand_128B :
5034 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vand_128B">;
5035
5036 def int_hexagon_V6_vmpyhv :
5037 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhv">;
5038
5039 def int_hexagon_V6_vmpyhv_128B :
5040 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhv_128B">;
5041
5042 def int_hexagon_V6_vdmpyhsuisat_acc :
5043 Hexagon_v16i32_v16i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc">;
5044
5045 def int_hexagon_V6_vdmpyhsuisat_acc_128B :
5046 Hexagon_v32i32_v32i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc_128B">;
5047
5048 def int_hexagon_V6_vsububsat_dv :
5049 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububsat_dv">;
5050
5051 def int_hexagon_V6_vsububsat_dv_128B :
5052 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsububsat_dv_128B">;
5053
5054 def int_hexagon_V6_vgtb_xor :
5055 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb_xor">;
5056
5057 def int_hexagon_V6_vgtb_xor_128B :
5058 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_xor_128B">;
5059
5060 def int_hexagon_V6_vdsaduh_acc :
5061 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_acc">;
5062
5063 def int_hexagon_V6_vdsaduh_acc_128B :
5064 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_acc_128B">;
5065
5066 def int_hexagon_V6_vrmpyub :
5067 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vrmpyub">;
5068
5069 def int_hexagon_V6_vrmpyub_128B :
5070 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_128B">;
5071
5072 def int_hexagon_V6_vmpyuh_acc :
5073 Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_acc">;
5074
5075 def int_hexagon_V6_vmpyuh_acc_128B :
5076 Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_acc_128B">;
5077
5078 def int_hexagon_V6_vcl0h :
5079 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcl0h">;
5080
5081 def int_hexagon_V6_vcl0h_128B :
5082 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcl0h_128B">;
5083
5084 def int_hexagon_V6_vmpyhus_acc :
5085 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhus_acc">;
5086
5087 def int_hexagon_V6_vmpyhus_acc_128B :
5088 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhus_acc_128B">;
5089
5090 def int_hexagon_V6_vmpybv_acc :
5091 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybv_acc">;
5092
5093 def int_hexagon_V6_vmpybv_acc_128B :
5094 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybv_acc_128B">;
5095
5096 def int_hexagon_V6_vrsadubi :
5097 Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi">;
5098
5099 def int_hexagon_V6_vrsadubi_128B :
5100 Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_128B">;
5101
5102 def int_hexagon_V6_vdmpyhb_dv_acc :
5103 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc">;
5104
5105 def int_hexagon_V6_vdmpyhb_dv_acc_128B :
5106 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc_128B">;
5107
5108 def int_hexagon_V6_vshufeh :
5109 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufeh">;
5110
5111 def int_hexagon_V6_vshufeh_128B :
5112 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufeh_128B">;
5113
5114 def int_hexagon_V6_vmpyewuh :
5115 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyewuh">;
5116
5117 def int_hexagon_V6_vmpyewuh_128B :
5118 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyewuh_128B">;
5119
5120 def int_hexagon_V6_vmpyhsrs :
5121 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhsrs">;
5122
5123 def int_hexagon_V6_vmpyhsrs_128B :
5124 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhsrs_128B">;
5125
5126 def int_hexagon_V6_vdmpybus_dv_acc :
5127 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_acc">;
5128
5129 def int_hexagon_V6_vdmpybus_dv_acc_128B :
5130 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_acc_128B">;
5131
5132 def int_hexagon_V6_vaddubh :
5133 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubh">;
5134
5135 def int_hexagon_V6_vaddubh_128B :
5136 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubh_128B">;
5137
5138 def int_hexagon_V6_vasrwh :
5139 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwh">;
5140
5141 def int_hexagon_V6_vasrwh_128B :
5142 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwh_128B">;
5143
5144 def int_hexagon_V6_ld0 :
5145 Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_ld0">;
5146
5147 def int_hexagon_V6_ld0_128B :
5148 Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_ld0_128B">;
5149
5150 def int_hexagon_V6_vpopcounth :
5151 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vpopcounth">;
5152
5153 def int_hexagon_V6_vpopcounth_128B :
5154 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vpopcounth_128B">;
5155
5156 def int_hexagon_V6_ldnt0 :
5157 Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_ldnt0">;
5158
5159 def int_hexagon_V6_ldnt0_128B :
5160 Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_ldnt0_128B">;
5161
5162 def int_hexagon_V6_vgth_and :
5163 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth_and">;
5164
5165 def int_hexagon_V6_vgth_and_128B :
5166 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_and_128B">;
5167
5168 def int_hexagon_V6_vaddubsat_dv :
5169 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubsat_dv">;
5170
5171 def int_hexagon_V6_vaddubsat_dv_128B :
5172 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddubsat_dv_128B">;
5173
5174 def int_hexagon_V6_vpackeh :
5175 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackeh">;
5176
5177 def int_hexagon_V6_vpackeh_128B :
5178 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackeh_128B">;
5179
5180 def int_hexagon_V6_vmpyh :
5181 Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyh">;
5182
5183 def int_hexagon_V6_vmpyh_128B :
5184 Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyh_128B">;
5185
5186 def int_hexagon_V6_vminh :
5187 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminh">;
5188
5189 def int_hexagon_V6_vminh_128B :
5190 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminh_128B">;
5191
5192 def int_hexagon_V6_pred_scalar2 :
5193 Hexagon_v512i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2">;
5194
5195 def int_hexagon_V6_pred_scalar2_128B :
5196 Hexagon_v1024i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2_128B">;
5197
5198 def int_hexagon_V6_vdealh :
5199 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vdealh">;
5200
5201 def int_hexagon_V6_vdealh_128B :
5202 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vdealh_128B">;
5203
5204 def int_hexagon_V6_vpackwh_sat :
5205 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackwh_sat">;
5206
5207 def int_hexagon_V6_vpackwh_sat_128B :
5208 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackwh_sat_128B">;
5209
5210 def int_hexagon_V6_vaslh :
5211 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vaslh">;
5212
5213 def int_hexagon_V6_vaslh_128B :
5214 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vaslh_128B">;
5215
5216 def int_hexagon_V6_vgtuw_and :
5217 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw_and">;
5218
5219 def int_hexagon_V6_vgtuw_and_128B :
5220 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_and_128B">;
5221
5222 def int_hexagon_V6_vor :
5223 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vor">;
5224
5225 def int_hexagon_V6_vor_128B :
5226 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vor_128B">;
5227
5228 def int_hexagon_V6_vlutvvb :
5229 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb">;
5230
5231 def int_hexagon_V6_vlutvvb_128B :
5232 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_128B">;
5233
5234 def int_hexagon_V6_vmpyiowh :
5235 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiowh">;
5236
5237 def int_hexagon_V6_vmpyiowh_128B :
5238 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiowh_128B">;
5239
5240 def int_hexagon_V6_vlutvvb_oracc :
5241 Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracc">;
5242
5243 def int_hexagon_V6_vlutvvb_oracc_128B :
5244 Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracc_128B">;
5245
5246 def int_hexagon_V6_vandvrt :
5247 Hexagon_v512i1_v16i32i32_Intrinsic<"HEXAGON_V6_vandvrt">;
5248
5249 def int_hexagon_V6_vandvrt_128B :
5250 Hexagon_v1024i1_v32i32i32_Intrinsic<"HEXAGON_V6_vandvrt_128B">;
5251
5252 def int_hexagon_V6_veqh_xor :
5253 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_xor">;
5254
5255 def int_hexagon_V6_veqh_xor_128B :
5256 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_xor_128B">;
5257
5258 def int_hexagon_V6_vadduhw :
5259 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhw">;
5260
5261 def int_hexagon_V6_vadduhw_128B :
5262 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhw_128B">;
5263
5264 def int_hexagon_V6_vcl0w :
5265 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcl0w">;
5266
5267 def int_hexagon_V6_vcl0w_128B :
5268 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcl0w_128B">;
5269
5270 def int_hexagon_V6_vmpyihb :
5271 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyihb">;
5272
5273 def int_hexagon_V6_vmpyihb_128B :
5274 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_128B">;
5275
5276 def int_hexagon_V6_vtmpybus :
5277 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpybus">;
5278
5279 def int_hexagon_V6_vtmpybus_128B :
5280 Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_128B">;
5281
5282 def int_hexagon_V6_vd0 :
5283 Hexagon_v16i32__Intrinsic<"HEXAGON_V6_vd0">;
5284
5285 def int_hexagon_V6_vd0_128B :
5286 Hexagon_v32i32__Intrinsic<"HEXAGON_V6_vd0_128B">;
5287
5288 def int_hexagon_V6_veqh_or :
5289 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_or">;
5290
5291 def int_hexagon_V6_veqh_or_128B :
5292 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_or_128B">;
5293
5294 def int_hexagon_V6_vgtw_or :
5295 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw_or">;
5296
5297 def int_hexagon_V6_vgtw_or_128B :
5298 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_or_128B">;
5299
5300 def int_hexagon_V6_vdmpybus :
5301 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpybus">;
5302
5303 def int_hexagon_V6_vdmpybus_128B :
5304 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_128B">;
5305
5306 def int_hexagon_V6_vgtub_or :
5307 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub_or">;
5308
5309 def int_hexagon_V6_vgtub_or_128B :
5310 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_or_128B">;
5311
5312 def int_hexagon_V6_vmpybus :
5313 Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpybus">;
5314
5315 def int_hexagon_V6_vmpybus_128B :
5316 Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpybus_128B">;
5317
5318 def int_hexagon_V6_vdmpyhb_acc :
5319 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_acc">;
5320
5321 def int_hexagon_V6_vdmpyhb_acc_128B :
5322 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_acc_128B">;
5323
5324 def int_hexagon_V6_vandvrt_acc :
5325 Hexagon_v512i1_v512i1v16i32i32_Intrinsic<"HEXAGON_V6_vandvrt_acc">;
5326
5327 def int_hexagon_V6_vandvrt_acc_128B :
5328 Hexagon_v1024i1_v1024i1v32i32i32_Intrinsic<"HEXAGON_V6_vandvrt_acc_128B">;
5329
5330 def int_hexagon_V6_vassign :
5331 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vassign">;
5332
5333 def int_hexagon_V6_vassign_128B :
5334 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vassign_128B">;
5335
5336 def int_hexagon_V6_vaddwnq :
5337 Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwnq">;
5338
5339 def int_hexagon_V6_vaddwnq_128B :
5340 Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwnq_128B">;
5341
5342 def int_hexagon_V6_vgtub_and :
5343 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub_and">;
5344
5345 def int_hexagon_V6_vgtub_and_128B :
5346 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_and_128B">;
5347
5348 def int_hexagon_V6_vdmpyhb_dv :
5349 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv">;
5350
5351 def int_hexagon_V6_vdmpyhb_dv_128B :
5352 Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_128B">;
5353
5354 def int_hexagon_V6_vunpackb :
5355 Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackb">;
5356
5357 def int_hexagon_V6_vunpackb_128B :
5358 Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackb_128B">;
5359
5360 def int_hexagon_V6_vunpackh :
5361 Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackh">;
5362
5363 def int_hexagon_V6_vunpackh_128B :
5364 Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackh_128B">;
5365
5366 def int_hexagon_V6_vmpahb_acc :
5367 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpahb_acc">;
5368
5369 def int_hexagon_V6_vmpahb_acc_128B :
5370 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpahb_acc_128B">;
5371
5372 def int_hexagon_V6_vaddbnq :
5373 Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbnq">;
5374
5375 def int_hexagon_V6_vaddbnq_128B :
5376 Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbnq_128B">;
5377
5378 def int_hexagon_V6_vlalignbi :
5379 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlalignbi">;
5380
5381 def int_hexagon_V6_vlalignbi_128B :
5382 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlalignbi_128B">;
5383
5384 def int_hexagon_V6_vsatwh :
5385 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatwh">;
5386
5387 def int_hexagon_V6_vsatwh_128B :
5388 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatwh_128B">;
5389
5390 def int_hexagon_V6_vgtuh :
5391 Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh">;
5392
5393 def int_hexagon_V6_vgtuh_128B :
5394 Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_128B">;
5395
5396 def int_hexagon_V6_vmpyihb_acc :
5397 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_acc">;
5398
5399 def int_hexagon_V6_vmpyihb_acc_128B :
5400 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_acc_128B">;
5401
5402 def int_hexagon_V6_vrmpybusv_acc :
5403 Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybusv_acc">;
5404
5405 def int_hexagon_V6_vrmpybusv_acc_128B :
5406 Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybusv_acc_128B">;
5407
5408 def int_hexagon_V6_vrdelta :
5409 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrdelta">;
5410
5411 def int_hexagon_V6_vrdelta_128B :
5412 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrdelta_128B">;
5413
5414 def int_hexagon_V6_vroundwh :
5415 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundwh">;
5416
5417 def int_hexagon_V6_vroundwh_128B :
5418 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundwh_128B">;
5419
5420 def int_hexagon_V6_vaddw_dv :
5421 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddw_dv">;
5422
5423 def int_hexagon_V6_vaddw_dv_128B :
5424 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddw_dv_128B">;
5425
5426 def int_hexagon_V6_vmpyiwb_acc :
5427 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_acc">;
5428
5429 def int_hexagon_V6_vmpyiwb_acc_128B :
5430 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_acc_128B">;
5431
5432 def int_hexagon_V6_vsubbq :
5433 Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbq">;
5434
5435 def int_hexagon_V6_vsubbq_128B :
5436 Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbq_128B">;
5437
5438 def int_hexagon_V6_veqh_and :
5439 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_and">;
5440
5441 def int_hexagon_V6_veqh_and_128B :
5442 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_and_128B">;
5443
5444 def int_hexagon_V6_valignbi :
5445 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_valignbi">;
5446
5447 def int_hexagon_V6_valignbi_128B :
5448 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_valignbi_128B">;
5449
5450 def int_hexagon_V6_vaddwsat :
5451 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwsat">;
5452
5453 def int_hexagon_V6_vaddwsat_128B :
5454 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwsat_128B">;
5455
5456 def int_hexagon_V6_veqw_and :
5457 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw_and">;
5458
5459 def int_hexagon_V6_veqw_and_128B :
5460 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_and_128B">;
5461
5462 def int_hexagon_V6_vabsdiffub :
5463 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffub">;
5464
5465 def int_hexagon_V6_vabsdiffub_128B :
5466 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffub_128B">;
5467
5468 def int_hexagon_V6_vshuffeb :
5469 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshuffeb">;
5470
5471 def int_hexagon_V6_vshuffeb_128B :
5472 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshuffeb_128B">;
5473
5474 def int_hexagon_V6_vabsdiffuh :
5475 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffuh">;
5476
5477 def int_hexagon_V6_vabsdiffuh_128B :
5478 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffuh_128B">;
5479
5480 def int_hexagon_V6_veqw_xor :
5481 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw_xor">;
5482
5483 def int_hexagon_V6_veqw_xor_128B :
5484 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_xor_128B">;
5485
5486 def int_hexagon_V6_vgth :
5487 Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth">;
5488
5489 def int_hexagon_V6_vgth_128B :
5490 Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_128B">;
5491
5492 def int_hexagon_V6_vgtuw_xor :
5493 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw_xor">;
5494
5495 def int_hexagon_V6_vgtuw_xor_128B :
5496 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_xor_128B">;
5497
5498 def int_hexagon_V6_vgtb :
5499 Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb">;
5500
5501 def int_hexagon_V6_vgtb_128B :
5502 Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_128B">;
5503
5504 def int_hexagon_V6_vgtw :
5505 Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw">;
5506
5507 def int_hexagon_V6_vgtw_128B :
5508 Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_128B">;
5509
5510 def int_hexagon_V6_vsubwq :
5511 Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwq">;
5512
5513 def int_hexagon_V6_vsubwq_128B :
5514 Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwq_128B">;
5515
5516 def int_hexagon_V6_vnot :
5517 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnot">;
5518
5519 def int_hexagon_V6_vnot_128B :
5520 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnot_128B">;
5521
5522 def int_hexagon_V6_vgtb_or :
5523 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb_or">;
5524
5525 def int_hexagon_V6_vgtb_or_128B :
5526 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_or_128B">;
5527
5528 def int_hexagon_V6_vgtuw_or :
5529 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw_or">;
5530
5531 def int_hexagon_V6_vgtuw_or_128B :
5532 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_or_128B">;
5533
5534 def int_hexagon_V6_vaddubsat :
5535 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubsat">;
5536
5537 def int_hexagon_V6_vaddubsat_128B :
5538 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubsat_128B">;
5539
5540 def int_hexagon_V6_vmaxw :
5541 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxw">;
5542
5543 def int_hexagon_V6_vmaxw_128B :
5544 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxw_128B">;
5545
5546 def int_hexagon_V6_vaslwv :
5547 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaslwv">;
5548
5549 def int_hexagon_V6_vaslwv_128B :
5550 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaslwv_128B">;
5551
5552 def int_hexagon_V6_vabsw_sat :
5553 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsw_sat">;
5554
5555 def int_hexagon_V6_vabsw_sat_128B :
5556 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsw_sat_128B">;
5557
5558 def int_hexagon_V6_vsubwsat_dv :
5559 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwsat_dv">;
5560
5561 def int_hexagon_V6_vsubwsat_dv_128B :
5562 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubwsat_dv_128B">;
5563
5564 def int_hexagon_V6_vroundhub :
5565 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundhub">;
5566
5567 def int_hexagon_V6_vroundhub_128B :
5568 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundhub_128B">;
5569
5570 def int_hexagon_V6_vdmpyhisat_acc :
5571 Hexagon_v16i32_v16i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc">;
5572
5573 def int_hexagon_V6_vdmpyhisat_acc_128B :
5574 Hexagon_v32i32_v32i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc_128B">;
5575
5576 def int_hexagon_V6_vmpabus :
5577 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpabus">;
5578
5579 def int_hexagon_V6_vmpabus_128B :
5580 Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpabus_128B">;
5581
5582 def int_hexagon_V6_vassignp :
5583 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vassignp">;
5584
5585 def int_hexagon_V6_vassignp_128B :
5586 Hexagon_v64i32_v64i32_Intrinsic<"HEXAGON_V6_vassignp_128B">;
5587
5588 def int_hexagon_V6_veqb :
5589 Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb">;
5590
5591 def int_hexagon_V6_veqb_128B :
5592 Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_128B">;
5593
5594 def int_hexagon_V6_vsububh :
5595 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsububh">;
5596
5597 def int_hexagon_V6_vsububh_128B :
5598 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububh_128B">;
5599
5600 def int_hexagon_V6_lvsplatw :
5601 Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplatw">;
5602
5603 def int_hexagon_V6_lvsplatw_128B :
5604 Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplatw_128B">;
5605
5606 def int_hexagon_V6_vaddhnq :
5607 Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhnq">;
5608
5609 def int_hexagon_V6_vaddhnq_128B :
5610 Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhnq_128B">;
5611
5612 def int_hexagon_V6_vdmpyhsusat :
5613 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat">;
5614
5615 def int_hexagon_V6_vdmpyhsusat_128B :
5616 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_128B">;
5617
5618 def int_hexagon_V6_pred_not :
5619 Hexagon_v512i1_v512i1_Intrinsic<"HEXAGON_V6_pred_not">;
5620
5621 def int_hexagon_V6_pred_not_128B :
5622 Hexagon_v1024i1_v1024i1_Intrinsic<"HEXAGON_V6_pred_not_128B">;
5623
5624 def int_hexagon_V6_vlutvwh_oracc :
5625 Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracc">;
5626
5627 def int_hexagon_V6_vlutvwh_oracc_128B :
5628 Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracc_128B">;
5629
5630 def int_hexagon_V6_vmpyiewh_acc :
5631 Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewh_acc">;
5632
5633 def int_hexagon_V6_vmpyiewh_acc_128B :
5634 Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewh_acc_128B">;
5635
5636 def int_hexagon_V6_vdealvdd :
5637 Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdealvdd">;
5638
5639 def int_hexagon_V6_vdealvdd_128B :
5640 Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdealvdd_128B">;
5641
5642 def int_hexagon_V6_vavgw :
5643 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgw">;
5644
5645 def int_hexagon_V6_vavgw_128B :
5646 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgw_128B">;
5647
5648 def int_hexagon_V6_vdmpyhsusat_acc :
5649 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_acc">;
5650
5651 def int_hexagon_V6_vdmpyhsusat_acc_128B :
5652 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_acc_128B">;
5653
5654 def int_hexagon_V6_vgtw_xor :
5655 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw_xor">;
5656
5657 def int_hexagon_V6_vgtw_xor_128B :
5658 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_xor_128B">;
5659
5660 def int_hexagon_V6_vtmpyhb_acc :
5661 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_acc">;
5662
5663 def int_hexagon_V6_vtmpyhb_acc_128B :
5664 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_acc_128B">;
5665
5666 def int_hexagon_V6_vaddhw :
5667 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhw">;
5668
5669 def int_hexagon_V6_vaddhw_128B :
5670 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhw_128B">;
5671
5672 def int_hexagon_V6_vaddhq :
5673 Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhq">;
5674
5675 def int_hexagon_V6_vaddhq_128B :
5676 Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhq_128B">;
5677
5678 def int_hexagon_V6_vrmpyubv :
5679 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpyubv">;
5680
5681 def int_hexagon_V6_vrmpyubv_128B :
5682 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpyubv_128B">;
5683
5684 def int_hexagon_V6_vsubh :
5685 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubh">;
5686
5687 def int_hexagon_V6_vsubh_128B :
5688 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubh_128B">;
5689
5690 def int_hexagon_V6_vrmpyubi :
5691 Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi">;
5692
5693 def int_hexagon_V6_vrmpyubi_128B :
5694 Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_128B">;
5695
5696 def int_hexagon_V6_vminw :
5697 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminw">;
5698
5699 def int_hexagon_V6_vminw_128B :
5700 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminw_128B">;
5701
5702 def int_hexagon_V6_vmpyubv_acc :
5703 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyubv_acc">;
5704
5705 def int_hexagon_V6_vmpyubv_acc_128B :
5706 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyubv_acc_128B">;
5707
5708 def int_hexagon_V6_pred_xor :
5709 Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_pred_xor">;
5710
5711 def int_hexagon_V6_pred_xor_128B :
5712 Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_pred_xor_128B">;
5713
5714 def int_hexagon_V6_veqb_xor :
5715 Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_xor">;
5716
5717 def int_hexagon_V6_veqb_xor_128B :
5718 Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_xor_128B">;
5719
5720 def int_hexagon_V6_vmpyiewuh :
5721 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewuh">;
5722
5723 def int_hexagon_V6_vmpyiewuh_128B :
5724 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_128B">;
5725
5726 def int_hexagon_V6_vmpybusv_acc :
5727 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybusv_acc">;
5728
5729 def int_hexagon_V6_vmpybusv_acc_128B :
5730 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybusv_acc_128B">;
5731
5732 def int_hexagon_V6_vavguhrnd :
5733 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguhrnd">;
5734
5735 def int_hexagon_V6_vavguhrnd_128B :
5736 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguhrnd_128B">;
5737
5738 def int_hexagon_V6_vmpyowh_rnd :
5739 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd">;
5740
5741 def int_hexagon_V6_vmpyowh_rnd_128B :
5742 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_128B">;
5743
5744 def int_hexagon_V6_vsubwsat :
5745 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwsat">;
5746
5747 def int_hexagon_V6_vsubwsat_128B :
5748 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwsat_128B">;
5749
5750 def int_hexagon_V6_vsubuhw :
5751 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuhw">;
5752
5753 def int_hexagon_V6_vsubuhw_128B :
5754 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhw_128B">;
5755
5756 def int_hexagon_V6_vrmpybusi_acc :
5757 Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_acc">;
5758
5759 def int_hexagon_V6_vrmpybusi_acc_128B :
5760 Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_acc_128B">;
5761
5762 def int_hexagon_V6_vasrw :
5763 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vasrw">;
5764
5765 def int_hexagon_V6_vasrw_128B :
5766 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vasrw_128B">;
5767
5768 def int_hexagon_V6_vasrh :
5769 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vasrh">;
5770
5771 def int_hexagon_V6_vasrh_128B :
5772 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vasrh_128B">;
5773
5774 def int_hexagon_V6_vmpyuhv :
5775 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhv">;
5776
5777 def int_hexagon_V6_vmpyuhv_128B :
5778 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhv_128B">;
5779
5780 def int_hexagon_V6_vasrhbrndsat :
5781 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhbrndsat">;
5782
5783 def int_hexagon_V6_vasrhbrndsat_128B :
5784 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhbrndsat_128B">;
5785
5786 def int_hexagon_V6_vsubuhsat_dv :
5787 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhsat_dv">;
5788
5789 def int_hexagon_V6_vsubuhsat_dv_128B :
5790 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubuhsat_dv_128B">;
5791
5792 def int_hexagon_V6_vabsdiffw :
5793 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffw">;
5794
5795 def int_hexagon_V6_vabsdiffw_128B :
5796 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffw_128B">;
5797
5798 // V62 HVX Instructions.
5799
5800 def int_hexagon_V6_vandnqrt_acc :
5801 Hexagon_v16i32_v16i32v512i1i32_Intrinsic<"HEXAGON_V6_vandnqrt_acc">;
5802
5803 def int_hexagon_V6_vandnqrt_acc_128B :
5804 Hexagon_v32i32_v32i32v1024i1i32_Intrinsic<"HEXAGON_V6_vandnqrt_acc_128B">;
5805
5806 def int_hexagon_V6_vaddclbh :
5807 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddclbh">;
5808
5809 def int_hexagon_V6_vaddclbh_128B :
5810 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddclbh_128B">;
5811
5812 def int_hexagon_V6_vmpyowh_64_acc :
5813 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc">;
5814
5815 def int_hexagon_V6_vmpyowh_64_acc_128B :
5816 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc_128B">;
5817
5818 def int_hexagon_V6_vmpyewuh_64 :
5819 Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyewuh_64">;
5820
5821 def int_hexagon_V6_vmpyewuh_64_128B :
5822 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyewuh_64_128B">;
5823
5824 def int_hexagon_V6_vsatuwuh :
5825 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatuwuh">;
5826
5827 def int_hexagon_V6_vsatuwuh_128B :
5828 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatuwuh_128B">;
5829
5830 def int_hexagon_V6_shuffeqh :
5831 Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_shuffeqh">;
5832
5833 def int_hexagon_V6_shuffeqh_128B :
5834 Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_shuffeqh_128B">;
5835
5836 def int_hexagon_V6_shuffeqw :
5837 Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_shuffeqw">;
5838
5839 def int_hexagon_V6_shuffeqw_128B :
5840 Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_shuffeqw_128B">;
5841
5842 def int_hexagon_V6_ldcnpnt0 :
5843 Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldcnpnt0">;
5844
5845 def int_hexagon_V6_ldcnpnt0_128B :
5846 Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldcnpnt0_128B">;
5847
5848 def int_hexagon_V6_vsubcarry :
5849 Hexagon_custom_v16i32v512i1_v16i32v16i32v512i1_Intrinsic;
5850
5851 def int_hexagon_V6_vsubcarry_128B :
5852 Hexagon_custom_v32i32v1024i1_v32i32v32i32v1024i1_Intrinsic_128B;
5853
5854 def int_hexagon_V6_vasrhbsat :
5855 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhbsat">;
5856
5857 def int_hexagon_V6_vasrhbsat_128B :
5858 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhbsat_128B">;
5859
5860 def int_hexagon_V6_vminb :
5861 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminb">;
5862
5863 def int_hexagon_V6_vminb_128B :
5864 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminb_128B">;
5865
5866 def int_hexagon_V6_vmpauhb_acc :
5867 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_acc">;
5868
5869 def int_hexagon_V6_vmpauhb_acc_128B :
5870 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_acc_128B">;
5871
5872 def int_hexagon_V6_vaddhw_acc :
5873 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhw_acc">;
5874
5875 def int_hexagon_V6_vaddhw_acc_128B :
5876 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhw_acc_128B">;
5877
5878 def int_hexagon_V6_vlsrb :
5879 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrb">;
5880
5881 def int_hexagon_V6_vlsrb_128B :
5882 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrb_128B">;
5883
5884 def int_hexagon_V6_vlutvwhi :
5885 Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwhi">;
5886
5887 def int_hexagon_V6_vlutvwhi_128B :
5888 Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwhi_128B">;
5889
5890 def int_hexagon_V6_vaddububb_sat :
5891 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddububb_sat">;
5892
5893 def int_hexagon_V6_vaddububb_sat_128B :
5894 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddububb_sat_128B">;
5895
5896 def int_hexagon_V6_vsubbsat_dv :
5897 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbsat_dv">;
5898
5899 def int_hexagon_V6_vsubbsat_dv_128B :
5900 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubbsat_dv_128B">;
5901
5902 def int_hexagon_V6_ldtp0 :
5903 Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldtp0">;
5904
5905 def int_hexagon_V6_ldtp0_128B :
5906 Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldtp0_128B">;
5907
5908 def int_hexagon_V6_vlutvvb_oracci :
5909 Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracci">;
5910
5911 def int_hexagon_V6_vlutvvb_oracci_128B :
5912 Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracci_128B">;
5913
5914 def int_hexagon_V6_vsubuwsat_dv :
5915 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuwsat_dv">;
5916
5917 def int_hexagon_V6_vsubuwsat_dv_128B :
5918 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubuwsat_dv_128B">;
5919
5920 def int_hexagon_V6_ldpnt0 :
5921 Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldpnt0">;
5922
5923 def int_hexagon_V6_ldpnt0_128B :
5924 Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldpnt0_128B">;
5925
5926 def int_hexagon_V6_vandvnqv :
5927 Hexagon_v16i32_v512i1v16i32_Intrinsic<"HEXAGON_V6_vandvnqv">;
5928
5929 def int_hexagon_V6_vandvnqv_128B :
5930 Hexagon_v32i32_v1024i1v32i32_Intrinsic<"HEXAGON_V6_vandvnqv_128B">;
5931
5932 def int_hexagon_V6_lvsplatb :
5933 Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplatb">;
5934
5935 def int_hexagon_V6_lvsplatb_128B :
5936 Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplatb_128B">;
5937
5938 def int_hexagon_V6_lvsplath :
5939 Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplath">;
5940
5941 def int_hexagon_V6_lvsplath_128B :
5942 Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplath_128B">;
5943
5944 def int_hexagon_V6_ldtpnt0 :
5945 Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldtpnt0">;
5946
5947 def int_hexagon_V6_ldtpnt0_128B :
5948 Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldtpnt0_128B">;
5949
5950 def int_hexagon_V6_vlutvwh_nm :
5951 Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_nm">;
5952
5953 def int_hexagon_V6_vlutvwh_nm_128B :
5954 Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_nm_128B">;
5955
5956 def int_hexagon_V6_ldnpnt0 :
5957 Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldnpnt0">;
5958
5959 def int_hexagon_V6_ldnpnt0_128B :
5960 Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldnpnt0_128B">;
5961
5962 def int_hexagon_V6_vmpauhb :
5963 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpauhb">;
5964
5965 def int_hexagon_V6_vmpauhb_128B :
5966 Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_128B">;
5967
5968 def int_hexagon_V6_ldtnp0 :
5969 Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldtnp0">;
5970
5971 def int_hexagon_V6_ldtnp0_128B :
5972 Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldtnp0_128B">;
5973
5974 def int_hexagon_V6_vrounduhub :
5975 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrounduhub">;
5976
5977 def int_hexagon_V6_vrounduhub_128B :
5978 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrounduhub_128B">;
5979
5980 def int_hexagon_V6_vadduhw_acc :
5981 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhw_acc">;
5982
5983 def int_hexagon_V6_vadduhw_acc_128B :
5984 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhw_acc_128B">;
5985
5986 def int_hexagon_V6_ldcp0 :
5987 Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldcp0">;
5988
5989 def int_hexagon_V6_ldcp0_128B :
5990 Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldcp0_128B">;
5991
5992 def int_hexagon_V6_vadduwsat :
5993 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduwsat">;
5994
5995 def int_hexagon_V6_vadduwsat_128B :
5996 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduwsat_128B">;
5997
5998 def int_hexagon_V6_ldtnpnt0 :
5999 Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldtnpnt0">;
6000
6001 def int_hexagon_V6_ldtnpnt0_128B :
6002 Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldtnpnt0_128B">;
6003
6004 def int_hexagon_V6_vaddbsat :
6005 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbsat">;
6006
6007 def int_hexagon_V6_vaddbsat_128B :
6008 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbsat_128B">;
6009
6010 def int_hexagon_V6_vandnqrt :
6011 Hexagon_v16i32_v512i1i32_Intrinsic<"HEXAGON_V6_vandnqrt">;
6012
6013 def int_hexagon_V6_vandnqrt_128B :
6014 Hexagon_v32i32_v1024i1i32_Intrinsic<"HEXAGON_V6_vandnqrt_128B">;
6015
6016 def int_hexagon_V6_vmpyiwub_acc :
6017 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_acc">;
6018
6019 def int_hexagon_V6_vmpyiwub_acc_128B :
6020 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_acc_128B">;
6021
6022 def int_hexagon_V6_vmaxb :
6023 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxb">;
6024
6025 def int_hexagon_V6_vmaxb_128B :
6026 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxb_128B">;
6027
6028 def int_hexagon_V6_vandvqv :
6029 Hexagon_v16i32_v512i1v16i32_Intrinsic<"HEXAGON_V6_vandvqv">;
6030
6031 def int_hexagon_V6_vandvqv_128B :
6032 Hexagon_v32i32_v1024i1v32i32_Intrinsic<"HEXAGON_V6_vandvqv_128B">;
6033
6034 def int_hexagon_V6_vaddcarry :
6035 Hexagon_custom_v16i32v512i1_v16i32v16i32v512i1_Intrinsic;
6036
6037 def int_hexagon_V6_vaddcarry_128B :
6038 Hexagon_custom_v32i32v1024i1_v32i32v32i32v1024i1_Intrinsic_128B;
6039
6040 def int_hexagon_V6_vasrwuhrndsat :
6041 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwuhrndsat">;
6042
6043 def int_hexagon_V6_vasrwuhrndsat_128B :
6044 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwuhrndsat_128B">;
6045
6046 def int_hexagon_V6_vlutvvbi :
6047 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvbi">;
6048
6049 def int_hexagon_V6_vlutvvbi_128B :
6050 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvbi_128B">;
6051
6052 def int_hexagon_V6_vsubuwsat :
6053 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuwsat">;
6054
6055 def int_hexagon_V6_vsubuwsat_128B :
6056 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuwsat_128B">;
6057
6058 def int_hexagon_V6_vaddbsat_dv :
6059 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbsat_dv">;
6060
6061 def int_hexagon_V6_vaddbsat_dv_128B :
6062 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddbsat_dv_128B">;
6063
6064 def int_hexagon_V6_ldnp0 :
6065 Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldnp0">;
6066
6067 def int_hexagon_V6_ldnp0_128B :
6068 Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldnp0_128B">;
6069
6070 def int_hexagon_V6_vasruwuhrndsat :
6071 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruwuhrndsat">;
6072
6073 def int_hexagon_V6_vasruwuhrndsat_128B :
6074 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruwuhrndsat_128B">;
6075
6076 def int_hexagon_V6_vrounduwuh :
6077 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrounduwuh">;
6078
6079 def int_hexagon_V6_vrounduwuh_128B :
6080 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrounduwuh_128B">;
6081
6082 def int_hexagon_V6_vlutvvb_nm :
6083 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_nm">;
6084
6085 def int_hexagon_V6_vlutvvb_nm_128B :
6086 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_nm_128B">;
6087
6088 def int_hexagon_V6_pred_scalar2v2 :
6089 Hexagon_v512i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2v2">;
6090
6091 def int_hexagon_V6_pred_scalar2v2_128B :
6092 Hexagon_v1024i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2v2_128B">;
6093
6094 def int_hexagon_V6_ldp0 :
6095 Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldp0">;
6096
6097 def int_hexagon_V6_ldp0_128B :
6098 Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldp0_128B">;
6099
6100 def int_hexagon_V6_vaddubh_acc :
6101 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubh_acc">;
6102
6103 def int_hexagon_V6_vaddubh_acc_128B :
6104 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubh_acc_128B">;
6105
6106 def int_hexagon_V6_vaddclbw :
6107 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddclbw">;
6108
6109 def int_hexagon_V6_vaddclbw_128B :
6110 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddclbw_128B">;
6111
6112 def int_hexagon_V6_ldcpnt0 :
6113 Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldcpnt0">;
6114
6115 def int_hexagon_V6_ldcpnt0_128B :
6116 Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldcpnt0_128B">;
6117
6118 def int_hexagon_V6_vadduwsat_dv :
6119 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduwsat_dv">;
6120
6121 def int_hexagon_V6_vadduwsat_dv_128B :
6122 Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vadduwsat_dv_128B">;
6123
6124 def int_hexagon_V6_vmpyiwub :
6125 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub">;
6126
6127 def int_hexagon_V6_vmpyiwub_128B :
6128 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_128B">;
6129
6130 def int_hexagon_V6_vsubububb_sat :
6131 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubububb_sat">;
6132
6133 def int_hexagon_V6_vsubububb_sat_128B :
6134 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubububb_sat_128B">;
6135
6136 def int_hexagon_V6_ldcnp0 :
6137 Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldcnp0">;
6138
6139 def int_hexagon_V6_ldcnp0_128B :
6140 Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldcnp0_128B">;
6141
6142 def int_hexagon_V6_vlutvwh_oracci :
6143 Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracci">;
6144
6145 def int_hexagon_V6_vlutvwh_oracci_128B :
6146 Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracci_128B">;
6147
6148 def int_hexagon_V6_vsubbsat :
6149 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbsat">;
6150
6151 def int_hexagon_V6_vsubbsat_128B :
6152 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbsat_128B">;
6153
6154 // V65 HVX Instructions.
6155
6156 def int_hexagon_V6_vasruhubrndsat :
6157 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruhubrndsat">;
6158
6159 def int_hexagon_V6_vasruhubrndsat_128B :
6160 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruhubrndsat_128B">;
6161
6162 def int_hexagon_V6_vrmpybub_rtt :
6163 Hexagon_v32i32_v16i32i64_Intrinsic<"HEXAGON_V6_vrmpybub_rtt">;
6164
6165 def int_hexagon_V6_vrmpybub_rtt_128B :
6166 Hexagon_v64i32_v32i32i64_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_128B">;
6167
6168 def int_hexagon_V6_vmpahhsat :
6169 Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpahhsat">;
6170
6171 def int_hexagon_V6_vmpahhsat_128B :
6172 Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpahhsat_128B">;
6173
6174 def int_hexagon_V6_vavguwrnd :
6175 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguwrnd">;
6176
6177 def int_hexagon_V6_vavguwrnd_128B :
6178 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguwrnd_128B">;
6179
6180 def int_hexagon_V6_vnavgb :
6181 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgb">;
6182
6183 def int_hexagon_V6_vnavgb_128B :
6184 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgb_128B">;
6185
6186 def int_hexagon_V6_vasrh_acc :
6187 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrh_acc">;
6188
6189 def int_hexagon_V6_vasrh_acc_128B :
6190 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrh_acc_128B">;
6191
6192 def int_hexagon_V6_vmpauhuhsat :
6193 Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpauhuhsat">;
6194
6195 def int_hexagon_V6_vmpauhuhsat_128B :
6196 Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpauhuhsat_128B">;
6197
6198 def int_hexagon_V6_vmpyh_acc :
6199 Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyh_acc">;
6200
6201 def int_hexagon_V6_vmpyh_acc_128B :
6202 Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyh_acc_128B">;
6203
6204 def int_hexagon_V6_vrmpybub_rtt_acc :
6205 Hexagon_v32i32_v32i32v16i32i64_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc">;
6206
6207 def int_hexagon_V6_vrmpybub_rtt_acc_128B :
6208 Hexagon_v64i32_v64i32v32i32i64_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc_128B">;
6209
6210 def int_hexagon_V6_vavgb :
6211 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgb">;
6212
6213 def int_hexagon_V6_vavgb_128B :
6214 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgb_128B">;
6215
6216 def int_hexagon_V6_vaslh_acc :
6217 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vaslh_acc">;
6218
6219 def int_hexagon_V6_vaslh_acc_128B :
6220 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vaslh_acc_128B">;
6221
6222 def int_hexagon_V6_vavguw :
6223 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguw">;
6224
6225 def int_hexagon_V6_vavguw_128B :
6226 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguw_128B">;
6227
6228 def int_hexagon_V6_vlut4 :
6229 Hexagon_v16i32_v16i32i64_Intrinsic<"HEXAGON_V6_vlut4">;
6230
6231 def int_hexagon_V6_vlut4_128B :
6232 Hexagon_v32i32_v32i32i64_Intrinsic<"HEXAGON_V6_vlut4_128B">;
6233
6234 def int_hexagon_V6_vmpyuhe_acc :
6235 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_acc">;
6236
6237 def int_hexagon_V6_vmpyuhe_acc_128B :
6238 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_acc_128B">;
6239
6240 def int_hexagon_V6_vrmpyub_rtt :
6241 Hexagon_v32i32_v16i32i64_Intrinsic<"HEXAGON_V6_vrmpyub_rtt">;
6242
6243 def int_hexagon_V6_vrmpyub_rtt_128B :
6244 Hexagon_v64i32_v32i32i64_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_128B">;
6245
6246 def int_hexagon_V6_vmpsuhuhsat :
6247 Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpsuhuhsat">;
6248
6249 def int_hexagon_V6_vmpsuhuhsat_128B :
6250 Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpsuhuhsat_128B">;
6251
6252 def int_hexagon_V6_vasruhubsat :
6253 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruhubsat">;
6254
6255 def int_hexagon_V6_vasruhubsat_128B :
6256 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruhubsat_128B">;
6257
6258 def int_hexagon_V6_vmpyuhe :
6259 Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe">;
6260
6261 def int_hexagon_V6_vmpyuhe_128B :
6262 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_128B">;
6263
6264 def int_hexagon_V6_vrmpyub_rtt_acc :
6265 Hexagon_v32i32_v32i32v16i32i64_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc">;
6266
6267 def int_hexagon_V6_vrmpyub_rtt_acc_128B :
6268 Hexagon_v64i32_v64i32v32i32i64_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc_128B">;
6269
6270 def int_hexagon_V6_vasruwuhsat :
6271 Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruwuhsat">;
6272
6273 def int_hexagon_V6_vasruwuhsat_128B :
6274 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruwuhsat_128B">;
6275
6276 def int_hexagon_V6_vmpabuu_acc :
6277 Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_acc">;
6278
6279 def int_hexagon_V6_vmpabuu_acc_128B :
6280 Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_acc_128B">;
6281
6282 def int_hexagon_V6_vprefixqw :
6283 Hexagon_v16i32_v512i1_Intrinsic<"HEXAGON_V6_vprefixqw">;
6284
6285 def int_hexagon_V6_vprefixqw_128B :
6286 Hexagon_v32i32_v1024i1_Intrinsic<"HEXAGON_V6_vprefixqw_128B">;
6287
6288 def int_hexagon_V6_vprefixqh :
6289 Hexagon_v16i32_v512i1_Intrinsic<"HEXAGON_V6_vprefixqh">;
6290
6291 def int_hexagon_V6_vprefixqh_128B :
6292 Hexagon_v32i32_v1024i1_Intrinsic<"HEXAGON_V6_vprefixqh_128B">;
6293
6294 def int_hexagon_V6_vprefixqb :
6295 Hexagon_v16i32_v512i1_Intrinsic<"HEXAGON_V6_vprefixqb">;
6296
6297 def int_hexagon_V6_vprefixqb_128B :
6298 Hexagon_v32i32_v1024i1_Intrinsic<"HEXAGON_V6_vprefixqb_128B">;
6299
6300 def int_hexagon_V6_vabsb :
6301 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsb">;
6302
6303 def int_hexagon_V6_vabsb_128B :
6304 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsb_128B">;
6305
6306 def int_hexagon_V6_vavgbrnd :
6307 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgbrnd">;
6308
6309 def int_hexagon_V6_vavgbrnd_128B :
6310 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgbrnd_128B">;
6311
6312 def int_hexagon_V6_vdd0 :
6313 Hexagon_v32i32__Intrinsic<"HEXAGON_V6_vdd0">;
6314
6315 def int_hexagon_V6_vdd0_128B :
6316 Hexagon_v64i32__Intrinsic<"HEXAGON_V6_vdd0_128B">;
6317
6318 def int_hexagon_V6_vmpabuu :
6319 Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpabuu">;
6320
6321 def int_hexagon_V6_vmpabuu_128B :
6322 Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_128B">;
6323
6324 def int_hexagon_V6_vabsb_sat :
6325 Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsb_sat">;
6326
6327 def int_hexagon_V6_vabsb_sat_128B :
6328 Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsb_sat_128B">;
6329
6330 // V66 HVX Instructions.
6331
6332 def int_hexagon_V6_vaddcarrysat :
6333 Hexagon_v16i32_v16i32v16i32v512i1_Intrinsic<"HEXAGON_V6_vaddcarrysat">;
6334
6335 def int_hexagon_V6_vaddcarrysat_128B :
6336 Hexagon_v32i32_v32i32v32i32v1024i1_Intrinsic<"HEXAGON_V6_vaddcarrysat_128B">;
6337
6338 def int_hexagon_V6_vasr_into :
6339 Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vasr_into">;
6340
6341 def int_hexagon_V6_vasr_into_128B :
6342 Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vasr_into_128B">;
6343
6344 def int_hexagon_V6_vsatdw :
6345 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatdw">;
6346
6347 def int_hexagon_V6_vsatdw_128B :
6348 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatdw_128B">;
6349
6350 def int_hexagon_V6_vrotr :
6351 Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrotr">;
6352
6353 def int_hexagon_V6_vrotr_128B :
6354 Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrotr_128B">;
6355