include/llvm/MCA/HWEventListener.h

   1 //===----------------------- HWEventListener.h ------------------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 /// \file
   9 ///
  10 /// This file defines the main interface for hardware event listeners.
  11 ///
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_MCA_HWEVENTLISTENER_H
  15 #define LLVM_MCA_HWEVENTLISTENER_H
  16
  17 #include "llvm/ADT/ArrayRef.h"
  18 #include "llvm/MCA/Instruction.h"
  19 #include "llvm/MCA/Support.h"
  20
  21 namespace llvm {
  22 namespace mca {
  23
  24 // An HWInstructionEvent represents state changes of instructions that
  25 // listeners might be interested in. Listeners can choose to ignore any event
  26 // they are not interested in.
  27 class HWInstructionEvent {
  28 public:
  29   // This is the list of event types that are shared by all targets, that
  30   // generic subtarget-agnostic classes (e.g., Pipeline, HWInstructionEvent,
  31   // ...) and generic Views can manipulate.
  32   // Subtargets are free to define additional event types, that are goin to be
  33   // handled by generic components as opaque values, but can still be
  34   // emitted by subtarget-specific pipeline stages (e.g., ExecuteStage,
  35   // DispatchStage, ...) and interpreted by subtarget-specific EventListener
  36   // implementations.
  37   enum GenericEventType {
  38     Invalid = 0,
  39     // Events generated by the Retire Control Unit.
  40     Retired,
  41     // Events generated by the Scheduler.
  42     Ready,
  43     Issued,
  44     Executed,
  45     // Events generated by the Dispatch logic.
  46     Dispatched,
  47
  48     LastGenericEventType,
  49   };
  50
  51   HWInstructionEvent(unsigned type, const InstRef &Inst)
  52       : Type(type), IR(Inst) {}
  53
  54   // The event type. The exact meaning depends on the subtarget.
  55   const unsigned Type;
  56
  57   // The instruction this event was generated for.
  58   const InstRef &IR;
  59 };
  60
  61 class HWInstructionIssuedEvent : public HWInstructionEvent {
  62 public:
  63   using ResourceRef = std::pair<uint64_t, uint64_t>;
  64   HWInstructionIssuedEvent(const InstRef &IR,
  65                            ArrayRef<std::pair<ResourceRef, ResourceCycles>> UR)
  66       : HWInstructionEvent(HWInstructionEvent::Issued, IR), UsedResources(UR) {}
  67
  68   ArrayRef<std::pair<ResourceRef, ResourceCycles>> UsedResources;
  69 };
  70
  71 class HWInstructionDispatchedEvent : public HWInstructionEvent {
  72 public:
  73   HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs,
  74                                unsigned UOps)
  75       : HWInstructionEvent(HWInstructionEvent::Dispatched, IR),
  76         UsedPhysRegs(Regs), MicroOpcodes(UOps) {}
  77   // Number of physical register allocated for this instruction. There is one
  78   // entry per register file.
  79   ArrayRef<unsigned> UsedPhysRegs;
  80   // Number of micro opcodes dispatched.
  81   // This field is often set to the total number of micro-opcodes specified by
  82   // the instruction descriptor of IR.
  83   // The only exception is when IR declares a number of micro opcodes
  84   // which exceeds the processor DispatchWidth, and - by construction - it
  85   // requires multiple cycles to be fully dispatched. In that particular case,
  86   // the dispatch logic would generate more than one dispatch event (one per
  87   // cycle), and each event would declare how many micro opcodes are effectively
  88   // been dispatched to the schedulers.
  89   unsigned MicroOpcodes;
  90 };
  91
  92 class HWInstructionRetiredEvent : public HWInstructionEvent {
  93 public:
  94   HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs)
  95       : HWInstructionEvent(HWInstructionEvent::Retired, IR),
  96         FreedPhysRegs(Regs) {}
  97   // Number of register writes that have been architecturally committed. There
  98   // is one entry per register file.
  99   ArrayRef<unsigned> FreedPhysRegs;
 100 };
 101
 102 // A HWStallEvent represents a pipeline stall caused by the lack of hardware
 103 // resources.
 104 class HWStallEvent {
 105 public:
 106   enum GenericEventType {
 107     Invalid = 0,
 108     // Generic stall events generated by the DispatchStage.
 109     RegisterFileStall,
 110     RetireControlUnitStall,
 111     // Generic stall events generated by the Scheduler.
 112     DispatchGroupStall,
 113     SchedulerQueueFull,
 114     LoadQueueFull,
 115     StoreQueueFull,
 116     LastGenericEvent
 117   };
 118
 119   HWStallEvent(unsigned type, const InstRef &Inst) : Type(type), IR(Inst) {}
 120
 121   // The exact meaning of the stall event type depends on the subtarget.
 122   const unsigned Type;
 123
 124   // The instruction this event was generated for.
 125   const InstRef &IR;
 126 };
 127
 128 class HWEventListener {
 129 public:
 130   // Generic events generated by the pipeline.
 131   virtual void onCycleBegin() {}
 132   virtual void onCycleEnd() {}
 133
 134   virtual void onEvent(const HWInstructionEvent &Event) {}
 135   virtual void onEvent(const HWStallEvent &Event) {}
 136
 137   using ResourceRef = std::pair<uint64_t, uint64_t>;
 138   virtual void onResourceAvailable(const ResourceRef &RRef) {}
 139
 140   // Events generated by the Scheduler when buffered resources are
 141   // consumed/freed for an instruction.
 142   virtual void onReservedBuffers(const InstRef &Inst,
 143                                  ArrayRef<unsigned> Buffers) {}
 144   virtual void onReleasedBuffers(const InstRef &Inst,
 145                                  ArrayRef<unsigned> Buffers) {}
 146
 147   virtual ~HWEventListener() {}
 148
 149 private:
 150   virtual void anchor();
 151 };
 152 } // namespace mca
 153 } // namespace llvm
 154
 155 #endif // LLVM_MCA_HWEVENTLISTENER_H