include/llvm/Support/ARMTargetParser.h

   1 //===-- ARMTargetParser - Parser for ARM target features --------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file implements a target parser to recognise ARM hardware features
  10 // such as FPU/CPU/ARCH/extensions and specific support such as HWDIV.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_SUPPORT_ARMTARGETPARSER_H
  15 #define LLVM_SUPPORT_ARMTARGETPARSER_H
  16
  17 #include "llvm/ADT/StringRef.h"
  18 #include "llvm/ADT/Triple.h"
  19 #include "llvm/Support/ARMBuildAttributes.h"
  20 #include <vector>
  21
  22 namespace llvm {
  23 namespace ARM {
  24
  25 // Arch extension modifiers for CPUs.
  26 // Note that this is not the same as the AArch64 list
  27 enum ArchExtKind : unsigned {
  28   AEK_INVALID =     0,
  29   AEK_NONE =        1,
  30   AEK_CRC =         1 << 1,
  31   AEK_CRYPTO =      1 << 2,
  32   AEK_FP =          1 << 3,
  33   AEK_HWDIVTHUMB =  1 << 4,
  34   AEK_HWDIVARM =    1 << 5,
  35   AEK_MP =          1 << 6,
  36   AEK_SIMD =        1 << 7,
  37   AEK_SEC =         1 << 8,
  38   AEK_VIRT =        1 << 9,
  39   AEK_DSP =         1 << 10,
  40   AEK_FP16 =        1 << 11,
  41   AEK_RAS =         1 << 12,
  42   AEK_SVE =         1 << 13,
  43   AEK_DOTPROD =     1 << 14,
  44   AEK_SHA2    =     1 << 15,
  45   AEK_AES     =     1 << 16,
  46   AEK_FP16FML =     1 << 17,
  47   AEK_SB      =     1 << 18,
  48   // Unsupported extensions.
  49   AEK_OS = 0x8000000,
  50   AEK_IWMMXT = 0x10000000,
  51   AEK_IWMMXT2 = 0x20000000,
  52   AEK_MAVERICK = 0x40000000,
  53   AEK_XSCALE = 0x80000000,
  54 };
  55
  56 // List of Arch Extension names.
  57 // FIXME: TableGen this.
  58 struct ExtName {
  59   const char *NameCStr;
  60   size_t NameLength;
  61   unsigned ID;
  62   const char *Feature;
  63   const char *NegFeature;
  64
  65   StringRef getName() const { return StringRef(NameCStr, NameLength); }
  66 };
  67
  68 const ExtName ARCHExtNames[] = {
  69 #define ARM_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE)                       \
  70   {NAME, sizeof(NAME) - 1, ID, FEATURE, NEGFEATURE},
  71 #include "ARMTargetParser.def"
  72 };
  73
  74 // List of HWDiv names (use getHWDivSynonym) and which architectural
  75 // features they correspond to (use getHWDivFeatures).
  76 // FIXME: TableGen this.
  77 const struct {
  78   const char *NameCStr;
  79   size_t NameLength;
  80   unsigned ID;
  81
  82   StringRef getName() const { return StringRef(NameCStr, NameLength); }
  83 } HWDivNames[] = {
  84 #define ARM_HW_DIV_NAME(NAME, ID) {NAME, sizeof(NAME) - 1, ID},
  85 #include "ARMTargetParser.def"
  86 };
  87
  88 // Arch names.
  89 enum class ArchKind {
  90 #define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) ID,
  91 #include "ARMTargetParser.def"
  92 };
  93
  94 // List of CPU names and their arches.
  95 // The same CPU can have multiple arches and can be default on multiple arches.
  96 // When finding the Arch for a CPU, first-found prevails. Sort them accordingly.
  97 // When this becomes table-generated, we'd probably need two tables.
  98 // FIXME: TableGen this.
  99 template <typename T> struct CpuNames {
 100   const char *NameCStr;
 101   size_t NameLength;
 102   T ArchID;
 103   bool Default; // is $Name the default CPU for $ArchID ?
 104   unsigned DefaultExtensions;
 105
 106   StringRef getName() const { return StringRef(NameCStr, NameLength); }
 107 };
 108
 109 const CpuNames<ArchKind> CPUNames[] = {
 110 #define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT)           \
 111   {NAME, sizeof(NAME) - 1, ARM::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT},
 112 #include "ARMTargetParser.def"
 113 };
 114
 115 // FPU names.
 116 enum FPUKind {
 117 #define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION) KIND,
 118 #include "ARMTargetParser.def"
 119   FK_LAST
 120 };
 121
 122 // FPU Version
 123 enum class FPUVersion {
 124   NONE,
 125   VFPV2,
 126   VFPV3,
 127   VFPV3_FP16,
 128   VFPV4,
 129   VFPV5
 130 };
 131
 132 // An FPU name restricts the FPU in one of three ways:
 133 enum class FPURestriction {
 134   None = 0, ///< No restriction
 135   D16,      ///< Only 16 D registers
 136   SP_D16    ///< Only single-precision instructions, with 16 D registers
 137 };
 138
 139 // An FPU name implies one of three levels of Neon support:
 140 enum class NeonSupportLevel {
 141   None = 0, ///< No Neon
 142   Neon,     ///< Neon
 143   Crypto    ///< Neon with Crypto
 144 };
 145
 146 // ISA kinds.
 147 enum class ISAKind { INVALID = 0, ARM, THUMB, AARCH64 };
 148
 149 // Endianness
 150 // FIXME: BE8 vs. BE32?
 151 enum class EndianKind { INVALID = 0, LITTLE, BIG };
 152
 153 // v6/v7/v8 Profile
 154 enum class ProfileKind { INVALID = 0, A, R, M };
 155
 156 // List of canonical FPU names (use getFPUSynonym) and which architectural
 157 // features they correspond to (use getFPUFeatures).
 158 // FIXME: TableGen this.
 159 // The entries must appear in the order listed in ARM::FPUKind for correct
 160 // indexing
 161 struct FPUName {
 162   const char *NameCStr;
 163   size_t NameLength;
 164   FPUKind ID;
 165   FPUVersion FPUVer;
 166   NeonSupportLevel NeonSupport;
 167   FPURestriction Restriction;
 168
 169   StringRef getName() const { return StringRef(NameCStr, NameLength); }
 170 };
 171
 172 static const FPUName FPUNames[] = {
 173 #define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION)                \
 174   {NAME, sizeof(NAME) - 1, KIND, VERSION, NEON_SUPPORT, RESTRICTION},
 175 #include "llvm/Support/ARMTargetParser.def"
 176 };
 177
 178 // List of canonical arch names (use getArchSynonym).
 179 // This table also provides the build attribute fields for CPU arch
 180 // and Arch ID, according to the Addenda to the ARM ABI, chapters
 181 // 2.4 and 2.3.5.2 respectively.
 182 // FIXME: SubArch values were simplified to fit into the expectations
 183 // of the triples and are not conforming with their official names.
 184 // Check to see if the expectation should be changed.
 185 // FIXME: TableGen this.
 186 template <typename T> struct ArchNames {
 187   const char *NameCStr;
 188   size_t NameLength;
 189   const char *CPUAttrCStr;
 190   size_t CPUAttrLength;
 191   const char *SubArchCStr;
 192   size_t SubArchLength;
 193   unsigned DefaultFPU;
 194   unsigned ArchBaseExtensions;
 195   T ID;
 196   ARMBuildAttrs::CPUArch ArchAttr; // Arch ID in build attributes.
 197
 198   StringRef getName() const { return StringRef(NameCStr, NameLength); }
 199
 200   // CPU class in build attributes.
 201   StringRef getCPUAttr() const { return StringRef(CPUAttrCStr, CPUAttrLength); }
 202
 203   // Sub-Arch name.
 204   StringRef getSubArch() const { return StringRef(SubArchCStr, SubArchLength); }
 205 };
 206
 207 static const ArchNames<ArchKind> ARCHNames[] = {
 208 #define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU,            \
 209                  ARCH_BASE_EXT)                                                \
 210   {NAME,         sizeof(NAME) - 1,                                             \
 211    CPU_ATTR,     sizeof(CPU_ATTR) - 1,                                         \
 212    SUB_ARCH,     sizeof(SUB_ARCH) - 1,                                         \
 213    ARCH_FPU,     ARCH_BASE_EXT,                                                \
 214    ArchKind::ID, ARCH_ATTR},
 215 #include "llvm/Support/ARMTargetParser.def"
 216 };
 217
 218 // Information by ID
 219 StringRef getFPUName(unsigned FPUKind);
 220 FPUVersion getFPUVersion(unsigned FPUKind);
 221 NeonSupportLevel getFPUNeonSupportLevel(unsigned FPUKind);
 222 FPURestriction getFPURestriction(unsigned FPUKind);
 223
 224 // FIXME: These should be moved to TargetTuple once it exists
 225 bool getFPUFeatures(unsigned FPUKind, std::vector<StringRef> &Features);
 226 bool getHWDivFeatures(unsigned HWDivKind, std::vector<StringRef> &Features);
 227 bool getExtensionFeatures(unsigned Extensions,
 228                           std::vector<StringRef> &Features);
 229
 230 StringRef getArchName(ArchKind AK);
 231 unsigned getArchAttr(ArchKind AK);
 232 StringRef getCPUAttr(ArchKind AK);
 233 StringRef getSubArch(ArchKind AK);
 234 StringRef getArchExtName(unsigned ArchExtKind);
 235 StringRef getArchExtFeature(StringRef ArchExt);
 236 StringRef getHWDivName(unsigned HWDivKind);
 237
 238 // Information by Name
 239 unsigned getDefaultFPU(StringRef CPU, ArchKind AK);
 240 unsigned getDefaultExtensions(StringRef CPU, ArchKind AK);
 241 StringRef getDefaultCPU(StringRef Arch);
 242 StringRef getCanonicalArchName(StringRef Arch);
 243 StringRef getFPUSynonym(StringRef FPU);
 244 StringRef getArchSynonym(StringRef Arch);
 245
 246 // Parser
 247 unsigned parseHWDiv(StringRef HWDiv);
 248 unsigned parseFPU(StringRef FPU);
 249 ArchKind parseArch(StringRef Arch);
 250 unsigned parseArchExt(StringRef ArchExt);
 251 ArchKind parseCPUArch(StringRef CPU);
 252 ISAKind parseArchISA(StringRef Arch);
 253 EndianKind parseArchEndian(StringRef Arch);
 254 ProfileKind parseArchProfile(StringRef Arch);
 255 unsigned parseArchVersion(StringRef Arch);
 256
 257 void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values);
 258 StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU);
 259
 260 } // namespace ARM
 261 } // namespace llvm
 262
 263 #endif