lib/Target/AArch64/AArch64SchedPredExynos.td

   1 //===- AArch64SchedPredExynos.td - AArch64 Sched Preds -----*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines scheduling predicate definitions that are used by the
  10 // AArch64 Exynos processors.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // Auxiliary predicates.
  15
  16 // Check the shift in arithmetic and logic instructions.
  17 def ExynosCheckShift : CheckAny<[CheckShiftBy0,
  18                                  CheckAll<
  19                                    [CheckShiftLSL,
  20                                     CheckAny<
  21                                       [CheckShiftBy1,
  22                                        CheckShiftBy2,
  23                                        CheckShiftBy3]>]>]>;
  24
  25 // Exynos predicates.
  26
  27 // Identify BLR specifying the LR register as the indirect target register.
  28 def ExynosBranchLinkLRPred : MCSchedPredicate<
  29                                CheckAll<[CheckOpcode<[BLR]>,
  30                                          CheckRegOperand<0, LR>]>>;
  31
  32 // Identify arithmetic instructions without or with limited extension or shift.
  33 def ExynosArithFn   : TIIPredicate<
  34                         "isExynosArithFast",
  35                         MCOpcodeSwitchStatement<
  36                           [MCOpcodeSwitchCase<
  37                              IsArithExtOp.ValidOpcodes,
  38                              MCReturnStatement<
  39                                CheckAny<[CheckExtBy0,
  40                                          CheckAll<
  41                                            [CheckAny<
  42                                              [CheckExtUXTW,
  43                                               CheckExtUXTX]>,
  44                                             CheckAny<
  45                                               [CheckExtBy1,
  46                                                CheckExtBy2,
  47                                                CheckExtBy3]>]>]>>>,
  48                            MCOpcodeSwitchCase<
  49                              IsArithShiftOp.ValidOpcodes,
  50                              MCReturnStatement<ExynosCheckShift>>,
  51                            MCOpcodeSwitchCase<
  52                              IsArithUnshiftOp.ValidOpcodes,
  53                              MCReturnStatement<TruePred>>],
  54                           MCReturnStatement<FalsePred>>>;
  55 def ExynosArithPred : MCSchedPredicate<ExynosArithFn>;
  56
  57 // Identify logic instructions with limited shift.
  58 def ExynosLogicFn   : TIIPredicate<
  59                         "isExynosLogicFast",
  60                         MCOpcodeSwitchStatement<
  61                           [MCOpcodeSwitchCase<
  62                              IsLogicShiftOp.ValidOpcodes,
  63                              MCReturnStatement<ExynosCheckShift>>,
  64                            MCOpcodeSwitchCase<
  65                              IsLogicUnshiftOp.ValidOpcodes,
  66                              MCReturnStatement<TruePred>>],
  67                           MCReturnStatement<FalsePred>>>;
  68 def ExynosLogicPred : MCSchedPredicate<ExynosLogicFn>;
  69
  70 // Identify more logic instructions with limited shift.
  71 def ExynosLogicExFn   : TIIPredicate<
  72                           "isExynosLogicExFast",
  73                           MCOpcodeSwitchStatement<
  74                             [MCOpcodeSwitchCase<
  75                                IsLogicShiftOp.ValidOpcodes,
  76                                MCReturnStatement<
  77                                  CheckAny<
  78                                    [ExynosCheckShift,
  79                                     CheckAll<
  80                                      [CheckShiftLSL,
  81                                       CheckShiftBy8]>]>>>,
  82                              MCOpcodeSwitchCase<
  83                                IsLogicUnshiftOp.ValidOpcodes,
  84                                MCReturnStatement<TruePred>>],
  85                             MCReturnStatement<FalsePred>>>;
  86 def ExynosLogicExPred : MCSchedPredicate<ExynosLogicExFn>;
  87
  88 // Identify a load or store using the register offset addressing mode
  89 // with a scaled non-extended register.
  90 def ExynosScaledIdxFn   : TIIPredicate<"isExynosScaledAddr",
  91                                        MCOpcodeSwitchStatement<
  92                                          [MCOpcodeSwitchCase<
  93                                             IsLoadStoreRegOffsetOp.ValidOpcodes,
  94                                             MCReturnStatement<
  95                                               CheckAny<
  96                                                 [CheckMemExtSXTW,
  97                                                  CheckMemExtUXTW,
  98                                                  CheckMemScaled]>>>],
  99                                          MCReturnStatement<FalsePred>>>;
 100 def ExynosScaledIdxPred : MCSchedPredicate<ExynosScaledIdxFn>;
 101
 102 // Identify FP instructions.
 103 def ExynosFPPred : MCSchedPredicate<CheckAny<[CheckDForm, CheckQForm]>>;
 104
 105 // Identify 128-bit NEON instructions.
 106 def ExynosQFormPred : MCSchedPredicate<CheckQForm>;
 107
 108 // Identify instructions that reset a register efficiently.
 109 def ExynosResetFn   : TIIPredicate<
 110                         "isExynosResetFast",
 111                         MCOpcodeSwitchStatement<
 112                           [MCOpcodeSwitchCase<
 113                              [ADR, ADRP,
 114                               MOVNWi, MOVNXi,
 115                               MOVZWi, MOVZXi],
 116                              MCReturnStatement<TruePred>>,
 117                            MCOpcodeSwitchCase<
 118                              [ORRWri, ORRXri],
 119                              MCReturnStatement<
 120                                CheckAll<
 121                                  [CheckIsRegOperand<1>,
 122                                   CheckAny<
 123                                     [CheckRegOperand<1, WZR>,
 124                                      CheckRegOperand<1, XZR>]>]>>>],
 125                           MCReturnStatement<
 126                             CheckAny<
 127                               [IsCopyIdiomFn,
 128                                IsZeroFPIdiomFn]>>>>;
 129 def ExynosResetPred : MCSchedPredicate<ExynosResetFn>;
 130
 131 // Identify EXTR as the alias for ROR (immediate).
 132 def ExynosRotateRightImmPred : MCSchedPredicate<
 133                                  CheckAll<[CheckOpcode<[EXTRWrri, EXTRXrri]>,
 134                                            CheckSameRegOperand<1, 2>]>>;
 135
 136 // Identify cheap arithmetic and logic immediate instructions.
 137 def ExynosCheapFn : TIIPredicate<
 138                       "isExynosCheapAsMove",
 139                       MCOpcodeSwitchStatement<
 140                         [MCOpcodeSwitchCase<
 141                            IsArithLogicImmOp.ValidOpcodes,
 142                            MCReturnStatement<TruePred>>],
 143                         MCReturnStatement<
 144                           CheckAny<
 145                             [ExynosArithFn, ExynosResetFn, ExynosLogicFn]>>>>;