lib/Target/AVR/AVRFrameLowering.cpp

   1 //===-- AVRFrameLowering.cpp - AVR Frame Information ----------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains the AVR implementation of TargetFrameLowering class.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "AVRFrameLowering.h"
  14
  15 #include "AVR.h"
  16 #include "AVRInstrInfo.h"
  17 #include "AVRMachineFunctionInfo.h"
  18 #include "AVRTargetMachine.h"
  19 #include "MCTargetDesc/AVRMCTargetDesc.h"
  20
  21 #include "llvm/CodeGen/MachineFrameInfo.h"
  22 #include "llvm/CodeGen/MachineFunction.h"
  23 #include "llvm/CodeGen/MachineFunctionPass.h"
  24 #include "llvm/CodeGen/MachineInstrBuilder.h"
  25 #include "llvm/CodeGen/MachineRegisterInfo.h"
  26 #include "llvm/IR/Function.h"
  27
  28 #include <vector>
  29
  30 namespace llvm {
  31
  32 AVRFrameLowering::AVRFrameLowering()
  33     : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 1, -2) {}
  34
  35 bool AVRFrameLowering::canSimplifyCallFramePseudos(
  36     const MachineFunction &MF) const {
  37   // Always simplify call frame pseudo instructions, even when
  38   // hasReservedCallFrame is false.
  39   return true;
  40 }
  41
  42 bool AVRFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
  43   // Reserve call frame memory in function prologue under the following
  44   // conditions:
  45   // - Y pointer is reserved to be the frame pointer.
  46   // - The function does not contain variable sized objects.
  47
  48   const MachineFrameInfo &MFI = MF.getFrameInfo();
  49   return hasFP(MF) && !MFI.hasVarSizedObjects();
  50 }
  51
  52 void AVRFrameLowering::emitPrologue(MachineFunction &MF,
  53                                     MachineBasicBlock &MBB) const {
  54   MachineBasicBlock::iterator MBBI = MBB.begin();
  55   CallingConv::ID CallConv = MF.getFunction().getCallingConv();
  56   DebugLoc DL = (MBBI != MBB.end()) ? MBBI->getDebugLoc() : DebugLoc();
  57   const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
  58   const AVRInstrInfo &TII = *STI.getInstrInfo();
  59   bool HasFP = hasFP(MF);
  60
  61   // Interrupt handlers re-enable interrupts in function entry.
  62   if (CallConv == CallingConv::AVR_INTR) {
  63     BuildMI(MBB, MBBI, DL, TII.get(AVR::BSETs))
  64         .addImm(0x07)
  65         .setMIFlag(MachineInstr::FrameSetup);
  66   }
  67
  68   // Save the frame pointer if we have one.
  69   if (HasFP) {
  70     BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHWRr))
  71         .addReg(AVR::R29R28, RegState::Kill)
  72         .setMIFlag(MachineInstr::FrameSetup);
  73   }
  74
  75   // Emit special prologue code to save R1, R0 and SREG in interrupt/signal
  76   // handlers before saving any other registers.
  77   if (CallConv == CallingConv::AVR_INTR ||
  78       CallConv == CallingConv::AVR_SIGNAL) {
  79     BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHWRr))
  80         .addReg(AVR::R1R0, RegState::Kill)
  81         .setMIFlag(MachineInstr::FrameSetup);
  82
  83     BuildMI(MBB, MBBI, DL, TII.get(AVR::INRdA), AVR::R0)
  84         .addImm(0x3f)
  85         .setMIFlag(MachineInstr::FrameSetup);
  86     BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr))
  87         .addReg(AVR::R0, RegState::Kill)
  88         .setMIFlag(MachineInstr::FrameSetup);
  89     BuildMI(MBB, MBBI, DL, TII.get(AVR::EORRdRr))
  90         .addReg(AVR::R0, RegState::Define)
  91         .addReg(AVR::R0, RegState::Kill)
  92         .addReg(AVR::R0, RegState::Kill)
  93         .setMIFlag(MachineInstr::FrameSetup);
  94   }
  95
  96   // Early exit if the frame pointer is not needed in this function.
  97   if (!HasFP) {
  98     return;
  99   }
 100
 101   const MachineFrameInfo &MFI = MF.getFrameInfo();
 102   const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
 103   unsigned FrameSize = MFI.getStackSize() - AFI->getCalleeSavedFrameSize();
 104
 105   // Skip the callee-saved push instructions.
 106   while (
 107       (MBBI != MBB.end()) && MBBI->getFlag(MachineInstr::FrameSetup) &&
 108       (MBBI->getOpcode() == AVR::PUSHRr || MBBI->getOpcode() == AVR::PUSHWRr)) {
 109     ++MBBI;
 110   }
 111
 112   // Update Y with the new base value.
 113   BuildMI(MBB, MBBI, DL, TII.get(AVR::SPREAD), AVR::R29R28)
 114       .addReg(AVR::SP)
 115       .setMIFlag(MachineInstr::FrameSetup);
 116
 117   // Mark the FramePtr as live-in in every block except the entry.
 118   for (MachineFunction::iterator I = std::next(MF.begin()), E = MF.end();
 119        I != E; ++I) {
 120     I->addLiveIn(AVR::R29R28);
 121   }
 122
 123   if (!FrameSize) {
 124     return;
 125   }
 126
 127   // Reserve the necessary frame memory by doing FP -= <size>.
 128   unsigned Opcode = (isUInt<6>(FrameSize)) ? AVR::SBIWRdK : AVR::SUBIWRdK;
 129
 130   MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opcode), AVR::R29R28)
 131                          .addReg(AVR::R29R28, RegState::Kill)
 132                          .addImm(FrameSize)
 133                          .setMIFlag(MachineInstr::FrameSetup);
 134   // The SREG implicit def is dead.
 135   MI->getOperand(3).setIsDead();
 136
 137   // Write back R29R28 to SP and temporarily disable interrupts.
 138   BuildMI(MBB, MBBI, DL, TII.get(AVR::SPWRITE), AVR::SP)
 139       .addReg(AVR::R29R28)
 140       .setMIFlag(MachineInstr::FrameSetup);
 141 }
 142
 143 void AVRFrameLowering::emitEpilogue(MachineFunction &MF,
 144                                     MachineBasicBlock &MBB) const {
 145   CallingConv::ID CallConv = MF.getFunction().getCallingConv();
 146   bool isHandler = (CallConv == CallingConv::AVR_INTR ||
 147                     CallConv == CallingConv::AVR_SIGNAL);
 148
 149   // Early exit if the frame pointer is not needed in this function except for
 150   // signal/interrupt handlers where special code generation is required.
 151   if (!hasFP(MF) && !isHandler) {
 152     return;
 153   }
 154
 155   MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
 156   assert(MBBI->getDesc().isReturn() &&
 157          "Can only insert epilog into returning blocks");
 158
 159   DebugLoc DL = MBBI->getDebugLoc();
 160   const MachineFrameInfo &MFI = MF.getFrameInfo();
 161   const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
 162   unsigned FrameSize = MFI.getStackSize() - AFI->getCalleeSavedFrameSize();
 163   const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
 164   const AVRInstrInfo &TII = *STI.getInstrInfo();
 165
 166   // Emit special epilogue code to restore R1, R0 and SREG in interrupt/signal
 167   // handlers at the very end of the function, just before reti.
 168   if (isHandler) {
 169     BuildMI(MBB, MBBI, DL, TII.get(AVR::POPRd), AVR::R0);
 170     BuildMI(MBB, MBBI, DL, TII.get(AVR::OUTARr))
 171         .addImm(0x3f)
 172         .addReg(AVR::R0, RegState::Kill);
 173     BuildMI(MBB, MBBI, DL, TII.get(AVR::POPWRd), AVR::R1R0);
 174   }
 175
 176   if (hasFP(MF))
 177     BuildMI(MBB, MBBI, DL, TII.get(AVR::POPWRd), AVR::R29R28);
 178
 179   // Early exit if there is no need to restore the frame pointer.
 180   if (!FrameSize) {
 181     return;
 182   }
 183
 184   // Skip the callee-saved pop instructions.
 185   while (MBBI != MBB.begin()) {
 186     MachineBasicBlock::iterator PI = std::prev(MBBI);
 187     int Opc = PI->getOpcode();
 188
 189     if (Opc != AVR::POPRd && Opc != AVR::POPWRd && !PI->isTerminator()) {
 190       break;
 191     }
 192
 193     --MBBI;
 194   }
 195
 196   unsigned Opcode;
 197
 198   // Select the optimal opcode depending on how big it is.
 199   if (isUInt<6>(FrameSize)) {
 200     Opcode = AVR::ADIWRdK;
 201   } else {
 202     Opcode = AVR::SUBIWRdK;
 203     FrameSize = -FrameSize;
 204   }
 205
 206   // Restore the frame pointer by doing FP += <size>.
 207   MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opcode), AVR::R29R28)
 208                          .addReg(AVR::R29R28, RegState::Kill)
 209                          .addImm(FrameSize);
 210   // The SREG implicit def is dead.
 211   MI->getOperand(3).setIsDead();
 212
 213   // Write back R29R28 to SP and temporarily disable interrupts.
 214   BuildMI(MBB, MBBI, DL, TII.get(AVR::SPWRITE), AVR::SP)
 215       .addReg(AVR::R29R28, RegState::Kill);
 216 }
 217
 218 // Return true if the specified function should have a dedicated frame
 219 // pointer register. This is true if the function meets any of the following
 220 // conditions:
 221 //  - a register has been spilled
 222 //  - has allocas
 223 //  - input arguments are passed using the stack
 224 //
 225 // Notice that strictly this is not a frame pointer because it contains SP after
 226 // frame allocation instead of having the original SP in function entry.
 227 bool AVRFrameLowering::hasFP(const MachineFunction &MF) const {
 228   const AVRMachineFunctionInfo *FuncInfo = MF.getInfo<AVRMachineFunctionInfo>();
 229
 230   return (FuncInfo->getHasSpills() || FuncInfo->getHasAllocas() ||
 231           FuncInfo->getHasStackArgs());
 232 }
 233
 234 bool AVRFrameLowering::spillCalleeSavedRegisters(
 235     MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
 236     const std::vector<CalleeSavedInfo> &CSI,
 237     const TargetRegisterInfo *TRI) const {
 238   if (CSI.empty()) {
 239     return false;
 240   }
 241
 242   unsigned CalleeFrameSize = 0;
 243   DebugLoc DL = MBB.findDebugLoc(MI);
 244   MachineFunction &MF = *MBB.getParent();
 245   const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
 246   const TargetInstrInfo &TII = *STI.getInstrInfo();
 247   AVRMachineFunctionInfo *AVRFI = MF.getInfo<AVRMachineFunctionInfo>();
 248
 249   for (unsigned i = CSI.size(); i != 0; --i) {
 250     unsigned Reg = CSI[i - 1].getReg();
 251     bool IsNotLiveIn = !MBB.isLiveIn(Reg);
 252
 253     assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 &&
 254            "Invalid register size");
 255
 256     // Add the callee-saved register as live-in only if it is not already a
 257     // live-in register, this usually happens with arguments that are passed
 258     // through callee-saved registers.
 259     if (IsNotLiveIn) {
 260       MBB.addLiveIn(Reg);
 261     }
 262
 263     // Do not kill the register when it is an input argument.
 264     BuildMI(MBB, MI, DL, TII.get(AVR::PUSHRr))
 265         .addReg(Reg, getKillRegState(IsNotLiveIn))
 266         .setMIFlag(MachineInstr::FrameSetup);
 267     ++CalleeFrameSize;
 268   }
 269
 270   AVRFI->setCalleeSavedFrameSize(CalleeFrameSize);
 271
 272   return true;
 273 }
 274
 275 bool AVRFrameLowering::restoreCalleeSavedRegisters(
 276     MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
 277     std::vector<CalleeSavedInfo> &CSI,
 278     const TargetRegisterInfo *TRI) const {
 279   if (CSI.empty()) {
 280     return false;
 281   }
 282
 283   DebugLoc DL = MBB.findDebugLoc(MI);
 284   const MachineFunction &MF = *MBB.getParent();
 285   const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
 286   const TargetInstrInfo &TII = *STI.getInstrInfo();
 287
 288   for (const CalleeSavedInfo &CCSI : CSI) {
 289     unsigned Reg = CCSI.getReg();
 290
 291     assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 &&
 292            "Invalid register size");
 293
 294     BuildMI(MBB, MI, DL, TII.get(AVR::POPRd), Reg);
 295   }
 296
 297   return true;
 298 }
 299
 300 /// Replace pseudo store instructions that pass arguments through the stack with
 301 /// real instructions. If insertPushes is true then all instructions are
 302 /// replaced with push instructions, otherwise regular std instructions are
 303 /// inserted.
 304 static void fixStackStores(MachineBasicBlock &MBB,
 305                            MachineBasicBlock::iterator MI,
 306                            const TargetInstrInfo &TII, bool insertPushes) {
 307   const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
 308   const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
 309
 310   // Iterate through the BB until we hit a call instruction or we reach the end.
 311   for (auto I = MI, E = MBB.end(); I != E && !I->isCall();) {
 312     MachineBasicBlock::iterator NextMI = std::next(I);
 313     MachineInstr &MI = *I;
 314     unsigned Opcode = I->getOpcode();
 315
 316     // Only care of pseudo store instructions where SP is the base pointer.
 317     if (Opcode != AVR::STDSPQRr && Opcode != AVR::STDWSPQRr) {
 318       I = NextMI;
 319       continue;
 320     }
 321
 322     assert(MI.getOperand(0).getReg() == AVR::SP &&
 323            "Invalid register, should be SP!");
 324     if (insertPushes) {
 325       // Replace this instruction with a push.
 326       Register SrcReg = MI.getOperand(2).getReg();
 327       bool SrcIsKill = MI.getOperand(2).isKill();
 328
 329       // We can't use PUSHWRr here because when expanded the order of the new
 330       // instructions are reversed from what we need. Perform the expansion now.
 331       if (Opcode == AVR::STDWSPQRr) {
 332         BuildMI(MBB, I, MI.getDebugLoc(), TII.get(AVR::PUSHRr))
 333             .addReg(TRI.getSubReg(SrcReg, AVR::sub_hi),
 334                     getKillRegState(SrcIsKill));
 335         BuildMI(MBB, I, MI.getDebugLoc(), TII.get(AVR::PUSHRr))
 336             .addReg(TRI.getSubReg(SrcReg, AVR::sub_lo),
 337                     getKillRegState(SrcIsKill));
 338       } else {
 339         BuildMI(MBB, I, MI.getDebugLoc(), TII.get(AVR::PUSHRr))
 340             .addReg(SrcReg, getKillRegState(SrcIsKill));
 341       }
 342
 343       MI.eraseFromParent();
 344       I = NextMI;
 345       continue;
 346     }
 347
 348     // Replace this instruction with a regular store. Use Y as the base
 349     // pointer since it is guaranteed to contain a copy of SP.
 350     unsigned STOpc =
 351         (Opcode == AVR::STDWSPQRr) ? AVR::STDWPtrQRr : AVR::STDPtrQRr;
 352
 353     MI.setDesc(TII.get(STOpc));
 354     MI.getOperand(0).setReg(AVR::R29R28);
 355
 356     I = NextMI;
 357   }
 358 }
 359
 360 MachineBasicBlock::iterator AVRFrameLowering::eliminateCallFramePseudoInstr(
 361     MachineFunction &MF, MachineBasicBlock &MBB,
 362     MachineBasicBlock::iterator MI) const {
 363   const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
 364   const AVRInstrInfo &TII = *STI.getInstrInfo();
 365
 366   // There is nothing to insert when the call frame memory is allocated during
 367   // function entry. Delete the call frame pseudo and replace all pseudo stores
 368   // with real store instructions.
 369   if (hasReservedCallFrame(MF)) {
 370     fixStackStores(MBB, MI, TII, false);
 371     return MBB.erase(MI);
 372   }
 373
 374   DebugLoc DL = MI->getDebugLoc();
 375   unsigned int Opcode = MI->getOpcode();
 376   int Amount = TII.getFrameSize(*MI);
 377
 378   // Adjcallstackup does not need to allocate stack space for the call, instead
 379   // we insert push instructions that will allocate the necessary stack.
 380   // For adjcallstackdown we convert it into an 'adiw reg, <amt>' handling
 381   // the read and write of SP in I/O space.
 382   if (Amount != 0) {
 383     assert(getStackAlignment() == 1 && "Unsupported stack alignment");
 384
 385     if (Opcode == TII.getCallFrameSetupOpcode()) {
 386       fixStackStores(MBB, MI, TII, true);
 387     } else {
 388       assert(Opcode == TII.getCallFrameDestroyOpcode());
 389
 390       // Select the best opcode to adjust SP based on the offset size.
 391       unsigned addOpcode;
 392       if (isUInt<6>(Amount)) {
 393         addOpcode = AVR::ADIWRdK;
 394       } else {
 395         addOpcode = AVR::SUBIWRdK;
 396         Amount = -Amount;
 397       }
 398
 399       // Build the instruction sequence.
 400       BuildMI(MBB, MI, DL, TII.get(AVR::SPREAD), AVR::R31R30).addReg(AVR::SP);
 401
 402       MachineInstr *New = BuildMI(MBB, MI, DL, TII.get(addOpcode), AVR::R31R30)
 403                               .addReg(AVR::R31R30, RegState::Kill)
 404                               .addImm(Amount);
 405       New->getOperand(3).setIsDead();
 406
 407       BuildMI(MBB, MI, DL, TII.get(AVR::SPWRITE), AVR::SP)
 408           .addReg(AVR::R31R30, RegState::Kill);
 409     }
 410   }
 411
 412   return MBB.erase(MI);
 413 }
 414
 415 void AVRFrameLowering::determineCalleeSaves(MachineFunction &MF,
 416                                             BitVector &SavedRegs,
 417                                             RegScavenger *RS) const {
 418   TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
 419
 420   // If we have a frame pointer, the Y register needs to be saved as well.
 421   // We don't do that here however - the prologue and epilogue generation
 422   // code will handle it specially.
 423 }
 424 /// The frame analyzer pass.
 425 ///
 426 /// Scans the function for allocas and used arguments
 427 /// that are passed through the stack.
 428 struct AVRFrameAnalyzer : public MachineFunctionPass {
 429   static char ID;
 430   AVRFrameAnalyzer() : MachineFunctionPass(ID) {}
 431
 432   bool runOnMachineFunction(MachineFunction &MF) {
 433     const MachineFrameInfo &MFI = MF.getFrameInfo();
 434     AVRMachineFunctionInfo *FuncInfo = MF.getInfo<AVRMachineFunctionInfo>();
 435
 436     // If there are no fixed frame indexes during this stage it means there
 437     // are allocas present in the function.
 438     if (MFI.getNumObjects() != MFI.getNumFixedObjects()) {
 439       // Check for the type of allocas present in the function. We only care
 440       // about fixed size allocas so do not give false positives if only
 441       // variable sized allocas are present.
 442       for (unsigned i = 0, e = MFI.getObjectIndexEnd(); i != e; ++i) {
 443         // Variable sized objects have size 0.
 444         if (MFI.getObjectSize(i)) {
 445           FuncInfo->setHasAllocas(true);
 446           break;
 447         }
 448       }
 449     }
 450
 451     // If there are fixed frame indexes present, scan the function to see if
 452     // they are really being used.
 453     if (MFI.getNumFixedObjects() == 0) {
 454       return false;
 455     }
 456
 457     // Ok fixed frame indexes present, now scan the function to see if they
 458     // are really being used, otherwise we can ignore them.
 459     for (const MachineBasicBlock &BB : MF) {
 460       for (const MachineInstr &MI : BB) {
 461         int Opcode = MI.getOpcode();
 462
 463         if ((Opcode != AVR::LDDRdPtrQ) && (Opcode != AVR::LDDWRdPtrQ) &&
 464             (Opcode != AVR::STDPtrQRr) && (Opcode != AVR::STDWPtrQRr)) {
 465           continue;
 466         }
 467
 468         for (const MachineOperand &MO : MI.operands()) {
 469           if (!MO.isFI()) {
 470             continue;
 471           }
 472
 473           if (MFI.isFixedObjectIndex(MO.getIndex())) {
 474             FuncInfo->setHasStackArgs(true);
 475             return false;
 476           }
 477         }
 478       }
 479     }
 480
 481     return false;
 482   }
 483
 484   StringRef getPassName() const { return "AVR Frame Analyzer"; }
 485 };
 486
 487 char AVRFrameAnalyzer::ID = 0;
 488
 489 /// Creates instance of the frame analyzer pass.
 490 FunctionPass *createAVRFrameAnalyzerPass() { return new AVRFrameAnalyzer(); }
 491
 492 /// Create the Dynalloca Stack Pointer Save/Restore pass.
 493 /// Insert a copy of SP before allocating the dynamic stack memory and restore
 494 /// it in function exit to restore the original SP state. This avoids the need
 495 /// of reserving a register pair for a frame pointer.
 496 struct AVRDynAllocaSR : public MachineFunctionPass {
 497   static char ID;
 498   AVRDynAllocaSR() : MachineFunctionPass(ID) {}
 499
 500   bool runOnMachineFunction(MachineFunction &MF) {
 501     // Early exit when there are no variable sized objects in the function.
 502     if (!MF.getFrameInfo().hasVarSizedObjects()) {
 503       return false;
 504     }
 505
 506     const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
 507     const TargetInstrInfo &TII = *STI.getInstrInfo();
 508     MachineBasicBlock &EntryMBB = MF.front();
 509     MachineBasicBlock::iterator MBBI = EntryMBB.begin();
 510     DebugLoc DL = EntryMBB.findDebugLoc(MBBI);
 511
 512     unsigned SPCopy =
 513         MF.getRegInfo().createVirtualRegister(&AVR::DREGSRegClass);
 514
 515     // Create a copy of SP in function entry before any dynallocas are
 516     // inserted.
 517     BuildMI(EntryMBB, MBBI, DL, TII.get(AVR::COPY), SPCopy).addReg(AVR::SP);
 518
 519     // Restore SP in all exit basic blocks.
 520     for (MachineBasicBlock &MBB : MF) {
 521       // If last instruction is a return instruction, add a restore copy.
 522       if (!MBB.empty() && MBB.back().isReturn()) {
 523         MBBI = MBB.getLastNonDebugInstr();
 524         DL = MBBI->getDebugLoc();
 525         BuildMI(MBB, MBBI, DL, TII.get(AVR::COPY), AVR::SP)
 526             .addReg(SPCopy, RegState::Kill);
 527       }
 528     }
 529
 530     return true;
 531   }
 532
 533   StringRef getPassName() const {
 534     return "AVR dynalloca stack pointer save/restore";
 535   }
 536 };
 537
 538 char AVRDynAllocaSR::ID = 0;
 539
 540 /// createAVRDynAllocaSRPass - returns an instance of the dynalloca stack
 541 /// pointer save/restore pass.
 542 FunctionPass *createAVRDynAllocaSRPass() { return new AVRDynAllocaSR(); }
 543
 544 } // end of namespace llvm
 545