lib/Target/ARM/ARMInstrInfo.h

   1 //===- ARMInstrInfo.h - ARM Instruction Information -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the ARM implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef ARMINSTRUCTIONINFO_H
  15 #define ARMINSTRUCTIONINFO_H
  16
  17 #include "llvm/Target/TargetInstrInfo.h"
  18 #include "ARMRegisterInfo.h"
  19
  20 namespace llvm {
  21   class ARMSubtarget;
  22
  23 /// ARMII - This namespace holds all of the target specific flags that
  24 /// instruction info tracks.
  25 ///
  26 namespace ARMII {
  27   enum {
  28     //===------------------------------------------------------------------===//
  29     // Instruction Flags.
  30
  31     //===------------------------------------------------------------------===//
  32     // This three-bit field describes the addressing mode used.  Zero is unused
  33     // so that we can tell if we forgot to set a value.
  34
  35     AddrModeMask  = 0xf,
  36     AddrModeNone  = 0,
  37     AddrMode1     = 1,
  38     AddrMode2     = 2,
  39     AddrMode3     = 3,
  40     AddrMode4     = 4,
  41     AddrMode5     = 5,
  42     AddrModeT1    = 6,
  43     AddrModeT2    = 7,
  44     AddrModeT4    = 8,
  45     AddrModeTs    = 9,   // i8 * 4 for pc and sp relative data
  46
  47     // Size* - Flags to keep track of the size of an instruction.
  48     SizeShift     = 4,
  49     SizeMask      = 7 << SizeShift,
  50     SizeSpecial   = 1,   // 0 byte pseudo or special case.
  51     Size8Bytes    = 2,
  52     Size4Bytes    = 3,
  53     Size2Bytes    = 4,
  54
  55     // IndexMode - Unindex, pre-indexed, or post-indexed. Only valid for load
  56     // and store ops
  57     IndexModeShift = 7,
  58     IndexModeMask  = 3 << IndexModeShift,
  59     IndexModePre   = 1,
  60     IndexModePost  = 2,
  61
  62     // Opcode
  63     OpcodeShift   = 9,
  64     OpcodeMask    = 0xf << OpcodeShift,
  65
  66     // Format
  67     FormShift   = 13,
  68     FormMask    = 31 << FormShift,
  69
  70     // Pseudo instructions
  71     Pseudo      = 1 << FormShift,
  72
  73     // Multiply instructions
  74     MulFrm      = 2 << FormShift,
  75     MulSMLAW    = 3 << FormShift,
  76     MulSMULW    = 4 << FormShift,
  77     MulSMLA     = 5 << FormShift,
  78     MulSMUL     = 6 << FormShift,
  79
  80     // Branch instructions
  81     Branch      = 7 << FormShift,
  82     BranchMisc  = 8 << FormShift,
  83
  84     // Data Processing instructions
  85     DPRdIm      = 9 << FormShift,
  86     DPRdReg     = 10 << FormShift,
  87     DPRdSoReg   = 11 << FormShift,
  88     DPRdMisc    = 12 << FormShift,
  89
  90     DPRnIm      = 13 << FormShift,
  91     DPRnReg     = 14 << FormShift,
  92     DPRnSoReg   = 15 << FormShift,
  93
  94     DPRIm       = 16 << FormShift,
  95     DPRReg      = 17 << FormShift,
  96     DPRSoReg    = 18 << FormShift,
  97
  98     DPRImS      = 19 << FormShift,
  99     DPRRegS     = 20 << FormShift,
 100     DPRSoRegS   = 21 << FormShift,
 101
 102     // Load and Store
 103     LdFrm       = 22 << FormShift,
 104     StFrm       = 23 << FormShift,
 105
 106     // Miscellaneous arithmetic instructions
 107     ArithMisc   = 24 << FormShift,
 108
 109     // Thumb format
 110     ThumbFrm    = 25 << FormShift,
 111
 112     // VFP format
 113     VPFFrm      = 26 << FormShift,
 114
 115     // Field shifts - such shifts are used to set field while generating
 116     // machine instructions.
 117     RegRsShift  = 8,
 118     RegRdShift  = 12,
 119     RegRnShift  = 16,
 120     L_BitShift  = 20,
 121     S_BitShift  = 20,
 122     U_BitShift  = 23,
 123     IndexShift  = 24,
 124     I_BitShift  = 25
 125   };
 126 }
 127
 128 class ARMInstrInfo : public TargetInstrInfoImpl {
 129   const ARMRegisterInfo RI;
 130 public:
 131   ARMInstrInfo(const ARMSubtarget &STI);
 132
 133   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
 134   /// such, whenever a client has an instance of instruction info, it should
 135   /// always be able to get register info as well (through this method).
 136   ///
 137   virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
 138
 139   /// getPointerRegClass - Return the register class to use to hold pointers.
 140   /// This is used for addressing modes.
 141   virtual const TargetRegisterClass *getPointerRegClass() const;
 142
 143   /// Return true if the instruction is a register to register move and
 144   /// leave the source and dest operands in the passed parameters.
 145   ///
 146   virtual bool isMoveInstr(const MachineInstr &MI,
 147                            unsigned &SrcReg, unsigned &DstReg) const;
 148   virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
 149   virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
 150
 151   virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
 152                                               MachineBasicBlock::iterator &MBBI,
 153                                               LiveVariables &LV) const;
 154
 155   // Branch analysis.
 156   virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
 157                              MachineBasicBlock *&FBB,
 158                              std::vector<MachineOperand> &Cond) const;
 159   virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
 160   virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
 161                                 MachineBasicBlock *FBB,
 162                                 const std::vector<MachineOperand> &Cond) const;
 163   virtual void copyRegToReg(MachineBasicBlock &MBB,
 164                             MachineBasicBlock::iterator I,
 165                             unsigned DestReg, unsigned SrcReg,
 166                             const TargetRegisterClass *DestRC,
 167                             const TargetRegisterClass *SrcRC) const;
 168   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
 169                                    MachineBasicBlock::iterator MBBI,
 170                                    unsigned SrcReg, bool isKill, int FrameIndex,
 171                                    const TargetRegisterClass *RC) const;
 172
 173   virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
 174                               SmallVectorImpl<MachineOperand> &Addr,
 175                               const TargetRegisterClass *RC,
 176                               SmallVectorImpl<MachineInstr*> &NewMIs) const;
 177
 178   virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
 179                                     MachineBasicBlock::iterator MBBI,
 180                                     unsigned DestReg, int FrameIndex,
 181                                     const TargetRegisterClass *RC) const;
 182
 183   virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
 184                                SmallVectorImpl<MachineOperand> &Addr,
 185                                const TargetRegisterClass *RC,
 186                                SmallVectorImpl<MachineInstr*> &NewMIs) const;
 187   virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
 188                                          MachineBasicBlock::iterator MI,
 189                                  const std::vector<CalleeSavedInfo> &CSI) const;
 190   virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
 191                                            MachineBasicBlock::iterator MI,
 192                                  const std::vector<CalleeSavedInfo> &CSI) const;
 193
 194   virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
 195                                           SmallVectorImpl<unsigned> &Ops,
 196                                           int FrameIndex) const;
 197
 198   virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
 199                                           SmallVectorImpl<unsigned> &Ops,
 200                                           MachineInstr* LoadMI) const {
 201     return 0;
 202   }
 203
 204   virtual bool canFoldMemoryOperand(MachineInstr *MI,
 205                                     SmallVectorImpl<unsigned> &Ops) const;
 206
 207   virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
 208   virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
 209
 210   // Predication support.
 211   virtual bool isPredicated(const MachineInstr *MI) const;
 212
 213   virtual
 214   bool PredicateInstruction(MachineInstr *MI,
 215                             const std::vector<MachineOperand> &Pred) const;
 216
 217   virtual
 218   bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
 219                          const std::vector<MachineOperand> &Pred2) const;
 220
 221   virtual bool DefinesPredicate(MachineInstr *MI,
 222                                 std::vector<MachineOperand> &Pred) const;
 223 };
 224
 225   // Utility routines
 226   namespace ARM {
 227     /// GetInstSize - Returns the size of the specified MachineInstr.
 228     ///
 229     unsigned GetInstSize(MachineInstr *MI);
 230
 231     /// GetFunctionSize - Returns the size of the specified MachineFunction.
 232     ///
 233     unsigned GetFunctionSize(MachineFunction &MF);
 234   }
 235 }
 236
 237 #endif