Fix bugs section.
[llvm-complete.git] / lib / Target / PowerPC / PPCRegisterInfo.cpp
blobb9273af1a48ef326580b388f19d5cd09315c5f26
1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the PowerPC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
15 #include "PPC.h"
16 #include "PPCInstrBuilder.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCRegisterInfo.h"
19 #include "PPCFrameInfo.h"
20 #include "PPCSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Type.h"
23 #include "llvm/CodeGen/ValueTypes.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineModuleInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineLocation.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAGNodes.h"
31 #include "llvm/Target/TargetFrameInfo.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include <cstdlib>
41 using namespace llvm;
43 /// getRegisterNumbering - Given the enum value for some register, e.g.
44 /// PPC::F14, return the number that it corresponds to (e.g. 14).
45 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
46 using namespace PPC;
47 switch (RegEnum) {
48 case R0 : case X0 : case F0 : case V0 : case CR0: return 0;
49 case R1 : case X1 : case F1 : case V1 : case CR1: return 1;
50 case R2 : case X2 : case F2 : case V2 : case CR2: return 2;
51 case R3 : case X3 : case F3 : case V3 : case CR3: return 3;
52 case R4 : case X4 : case F4 : case V4 : case CR4: return 4;
53 case R5 : case X5 : case F5 : case V5 : case CR5: return 5;
54 case R6 : case X6 : case F6 : case V6 : case CR6: return 6;
55 case R7 : case X7 : case F7 : case V7 : case CR7: return 7;
56 case R8 : case X8 : case F8 : case V8 : return 8;
57 case R9 : case X9 : case F9 : case V9 : return 9;
58 case R10: case X10: case F10: case V10: return 10;
59 case R11: case X11: case F11: case V11: return 11;
60 case R12: case X12: case F12: case V12: return 12;
61 case R13: case X13: case F13: case V13: return 13;
62 case R14: case X14: case F14: case V14: return 14;
63 case R15: case X15: case F15: case V15: return 15;
64 case R16: case X16: case F16: case V16: return 16;
65 case R17: case X17: case F17: case V17: return 17;
66 case R18: case X18: case F18: case V18: return 18;
67 case R19: case X19: case F19: case V19: return 19;
68 case R20: case X20: case F20: case V20: return 20;
69 case R21: case X21: case F21: case V21: return 21;
70 case R22: case X22: case F22: case V22: return 22;
71 case R23: case X23: case F23: case V23: return 23;
72 case R24: case X24: case F24: case V24: return 24;
73 case R25: case X25: case F25: case V25: return 25;
74 case R26: case X26: case F26: case V26: return 26;
75 case R27: case X27: case F27: case V27: return 27;
76 case R28: case X28: case F28: case V28: return 28;
77 case R29: case X29: case F29: case V29: return 29;
78 case R30: case X30: case F30: case V30: return 30;
79 case R31: case X31: case F31: case V31: return 31;
80 default:
81 cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
82 abort();
86 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
87 const TargetInstrInfo &tii)
88 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
89 Subtarget(ST), TII(tii) {
90 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
91 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
92 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
93 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
94 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
95 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
96 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
97 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
99 // 64-bit
100 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
101 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
102 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
103 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
104 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
107 void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
108 MachineBasicBlock::iterator I,
109 unsigned DestReg,
110 const MachineInstr *Orig) const {
111 MachineInstr *MI = Orig->clone();
112 MI->getOperand(0).setReg(DestReg);
113 MBB.insert(I, MI);
116 const unsigned*
117 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
118 // 32-bit Darwin calling convention.
119 static const unsigned Macho32_CalleeSavedRegs[] = {
120 PPC::R13, PPC::R14, PPC::R15,
121 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
122 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
123 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
124 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
126 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
127 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
128 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
129 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
130 PPC::F30, PPC::F31,
132 PPC::CR2, PPC::CR3, PPC::CR4,
133 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
134 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
135 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
137 PPC::LR, 0
140 static const unsigned ELF32_CalleeSavedRegs[] = {
141 PPC::R13, PPC::R14, PPC::R15,
142 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
143 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
144 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
145 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
147 PPC::F9,
148 PPC::F10, PPC::F11, PPC::F12, PPC::F13,
149 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
150 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
151 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
152 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
153 PPC::F30, PPC::F31,
155 PPC::CR2, PPC::CR3, PPC::CR4,
156 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
157 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
158 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
160 PPC::LR, 0
162 // 64-bit Darwin calling convention.
163 static const unsigned Macho64_CalleeSavedRegs[] = {
164 PPC::X14, PPC::X15,
165 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
166 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
167 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
168 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
170 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
171 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
172 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
173 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
174 PPC::F30, PPC::F31,
176 PPC::CR2, PPC::CR3, PPC::CR4,
177 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
178 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
179 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
181 PPC::LR8, 0
184 if (Subtarget.isMachoABI())
185 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegs :
186 Macho32_CalleeSavedRegs;
188 // ELF 32.
189 return ELF32_CalleeSavedRegs;
192 const TargetRegisterClass* const*
193 PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
194 // 32-bit Macho calling convention.
195 static const TargetRegisterClass * const Macho32_CalleeSavedRegClasses[] = {
196 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
197 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
198 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
199 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
200 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
202 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
203 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
204 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
205 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
206 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
208 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
210 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
211 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
212 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
214 &PPC::GPRCRegClass, 0
217 static const TargetRegisterClass * const ELF32_CalleeSavedRegClasses[] = {
218 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
219 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
220 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
221 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
222 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
224 &PPC::F8RCRegClass,
225 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
226 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
227 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
228 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
229 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
230 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
232 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
234 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
235 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
236 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
238 &PPC::GPRCRegClass, 0
241 // 64-bit Macho calling convention.
242 static const TargetRegisterClass * const Macho64_CalleeSavedRegClasses[] = {
243 &PPC::G8RCRegClass,&PPC::G8RCRegClass,
244 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
245 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
246 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
247 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
249 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
250 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
251 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
252 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
253 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
255 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
257 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
258 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
259 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
261 &PPC::G8RCRegClass, 0
264 if (Subtarget.isMachoABI())
265 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegClasses :
266 Macho32_CalleeSavedRegClasses;
268 // ELF 32.
269 return ELF32_CalleeSavedRegClasses;
272 // needsFP - Return true if the specified function should have a dedicated frame
273 // pointer register. This is true if the function has variable sized allocas or
274 // if frame pointer elimination is disabled.
276 static bool needsFP(const MachineFunction &MF) {
277 const MachineFrameInfo *MFI = MF.getFrameInfo();
278 return NoFramePointerElim || MFI->hasVarSizedObjects();
281 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
282 BitVector Reserved(getNumRegs());
283 Reserved.set(PPC::R0);
284 Reserved.set(PPC::R1);
285 Reserved.set(PPC::LR);
286 // In Linux, r2 is reserved for the OS.
287 if (!Subtarget.isDarwin())
288 Reserved.set(PPC::R2);
289 // On PPC64, r13 is the thread pointer. Never allocate this register.
290 // Note that this is overconservative, as it also prevents allocation of
291 // R31 when the FP is not needed.
292 if (Subtarget.isPPC64()) {
293 Reserved.set(PPC::R13);
294 Reserved.set(PPC::R31);
296 if (needsFP(MF))
297 Reserved.set(PPC::R31);
298 return Reserved;
301 //===----------------------------------------------------------------------===//
302 // Stack Frame Processing methods
303 //===----------------------------------------------------------------------===//
305 // hasFP - Return true if the specified function actually has a dedicated frame
306 // pointer register. This is true if the function needs a frame pointer and has
307 // a non-zero stack size.
308 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const {
309 const MachineFrameInfo *MFI = MF.getFrameInfo();
310 return MFI->getStackSize() && needsFP(MF);
313 /// MustSaveLR - Return true if this function requires that we save the LR
314 /// register onto the stack in the prolog and restore it in the epilog of the
315 /// function.
316 static bool MustSaveLR(const MachineFunction &MF) {
317 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
319 // We need an save/restore of LR if there is any use/def of LR explicitly, or
320 // if there is some use of the LR stack slot (e.g. for builtin_return_address.
321 return MFI->usesLR() || MFI->isLRStoreRequired() ||
322 // FIXME: Anything that has a call should clobber the LR register,
323 // isn't this redundant??
324 MF.getFrameInfo()->hasCalls();
327 void PPCRegisterInfo::
328 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
329 MachineBasicBlock::iterator I) const {
330 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
331 MBB.erase(I);
334 /// LowerDynamicAlloc - Generate the code for allocating an object in the
335 /// current frame. The sequence of code with be in the general form
337 /// addi R0, SP, #frameSize ; get the address of the previous frame
338 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
339 /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation
341 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
342 // Get the instruction.
343 MachineInstr &MI = *II;
344 // Get the instruction's basic block.
345 MachineBasicBlock &MBB = *MI.getParent();
346 // Get the basic block's function.
347 MachineFunction &MF = *MBB.getParent();
348 // Get the frame info.
349 MachineFrameInfo *MFI = MF.getFrameInfo();
350 // Determine whether 64-bit pointers are used.
351 bool LP64 = Subtarget.isPPC64();
353 // Get the maximum call stack size.
354 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
355 // Get the total frame size.
356 unsigned FrameSize = MFI->getStackSize();
358 // Get stack alignments.
359 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
360 unsigned MaxAlign = MFI->getMaxAlignment();
361 assert(MaxAlign <= TargetAlign &&
362 "Dynamic alloca with large aligns not supported");
364 // Determine the previous frame's address. If FrameSize can't be
365 // represented as 16 bits or we need special alignment, then we load the
366 // previous frame's address from 0(SP). Why not do an addis of the hi?
367 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
368 // Constructing the constant and adding would take 3 instructions.
369 // Fortunately, a frame greater than 32K is rare.
370 if (MaxAlign < TargetAlign && isInt16(FrameSize)) {
371 BuildMI(MBB, II, TII.get(PPC::ADDI), PPC::R0)
372 .addReg(PPC::R31)
373 .addImm(FrameSize);
374 } else if (LP64) {
375 BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0)
376 .addImm(0)
377 .addReg(PPC::X1);
378 } else {
379 BuildMI(MBB, II, TII.get(PPC::LWZ), PPC::R0)
380 .addImm(0)
381 .addReg(PPC::R1);
384 // Grow the stack and update the stack pointer link, then
385 // determine the address of new allocated space.
386 if (LP64) {
387 BuildMI(MBB, II, TII.get(PPC::STDUX))
388 .addReg(PPC::X0)
389 .addReg(PPC::X1)
390 .addReg(MI.getOperand(1).getReg());
391 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
392 .addReg(PPC::X1)
393 .addImm(maxCallFrameSize);
394 } else {
395 BuildMI(MBB, II, TII.get(PPC::STWUX))
396 .addReg(PPC::R0)
397 .addReg(PPC::R1)
398 .addReg(MI.getOperand(1).getReg());
399 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
400 .addReg(PPC::R1)
401 .addImm(maxCallFrameSize);
404 // Discard the DYNALLOC instruction.
405 MBB.erase(II);
408 void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
409 int SPAdj, RegScavenger *RS) const {
410 assert(SPAdj == 0 && "Unexpected");
412 // Get the instruction.
413 MachineInstr &MI = *II;
414 // Get the instruction's basic block.
415 MachineBasicBlock &MBB = *MI.getParent();
416 // Get the basic block's function.
417 MachineFunction &MF = *MBB.getParent();
418 // Get the frame info.
419 MachineFrameInfo *MFI = MF.getFrameInfo();
421 // Find out which operand is the frame index.
422 unsigned FIOperandNo = 0;
423 while (!MI.getOperand(FIOperandNo).isFrameIndex()) {
424 ++FIOperandNo;
425 assert(FIOperandNo != MI.getNumOperands() &&
426 "Instr doesn't have FrameIndex operand!");
428 // Take into account whether it's an add or mem instruction
429 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2;
430 if (MI.getOpcode() == TargetInstrInfo::INLINEASM)
431 OffsetOperandNo = FIOperandNo-1;
433 // Get the frame index.
434 int FrameIndex = MI.getOperand(FIOperandNo).getIndex();
436 // Get the frame pointer save index. Users of this index are primarily
437 // DYNALLOC instructions.
438 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
439 int FPSI = FI->getFramePointerSaveIndex();
440 // Get the instruction opcode.
441 unsigned OpC = MI.getOpcode();
443 // Special case for dynamic alloca.
444 if (FPSI && FrameIndex == FPSI &&
445 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
446 lowerDynamicAlloc(II);
447 return;
450 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
451 MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1,
452 false);
454 // Figure out if the offset in the instruction is shifted right two bits. This
455 // is true for instructions like "STD", which the machine implicitly adds two
456 // low zeros to.
457 bool isIXAddr = false;
458 switch (OpC) {
459 case PPC::LWA:
460 case PPC::LD:
461 case PPC::STD:
462 case PPC::STD_32:
463 isIXAddr = true;
464 break;
467 // Now add the frame object offset to the offset from r1.
468 int Offset = MFI->getObjectOffset(FrameIndex);
469 if (!isIXAddr)
470 Offset += MI.getOperand(OffsetOperandNo).getImm();
471 else
472 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
474 // If we're not using a Frame Pointer that has been set to the value of the
475 // SP before having the stack size subtracted from it, then add the stack size
476 // to Offset to get the correct offset.
477 Offset += MFI->getStackSize();
479 // If we can, encode the offset directly into the instruction. If this is a
480 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
481 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
482 // clear can be encoded. This is extremely uncommon, because normally you
483 // only "std" to a stack slot that is at least 4-byte aligned, but it can
484 // happen in invalid code.
485 if (isInt16(Offset) && (!isIXAddr || (Offset & 3) == 0)) {
486 if (isIXAddr)
487 Offset >>= 2; // The actual encoded value has the low two bits zero.
488 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
489 return;
492 // Insert a set of r0 with the full offset value before the ld, st, or add
493 BuildMI(MBB, II, TII.get(PPC::LIS), PPC::R0).addImm(Offset >> 16);
494 BuildMI(MBB, II, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0).addImm(Offset);
496 // Convert into indexed form of the instruction
497 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
498 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
499 unsigned OperandBase;
500 if (OpC != TargetInstrInfo::INLINEASM) {
501 assert(ImmToIdxMap.count(OpC) &&
502 "No indexed form of load or store available!");
503 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
504 MI.setDesc(TII.get(NewOpcode));
505 OperandBase = 1;
506 } else {
507 OperandBase = OffsetOperandNo;
510 unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
511 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
512 MI.getOperand(OperandBase+1).ChangeToRegister(PPC::R0, false);
515 /// VRRegNo - Map from a numbered VR register to its enum value.
517 static const unsigned short VRRegNo[] = {
518 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
519 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
520 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
521 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
524 /// RemoveVRSaveCode - We have found that this function does not need any code
525 /// to manipulate the VRSAVE register, even though it uses vector registers.
526 /// This can happen when the only registers used are known to be live in or out
527 /// of the function. Remove all of the VRSAVE related code from the function.
528 static void RemoveVRSaveCode(MachineInstr *MI) {
529 MachineBasicBlock *Entry = MI->getParent();
530 MachineFunction *MF = Entry->getParent();
532 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
533 MachineBasicBlock::iterator MBBI = MI;
534 ++MBBI;
535 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
536 MBBI->eraseFromParent();
538 bool RemovedAllMTVRSAVEs = true;
539 // See if we can find and remove the MTVRSAVE instruction from all of the
540 // epilog blocks.
541 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
542 // If last instruction is a return instruction, add an epilogue
543 if (!I->empty() && I->back().getDesc().isReturn()) {
544 bool FoundIt = false;
545 for (MBBI = I->end(); MBBI != I->begin(); ) {
546 --MBBI;
547 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
548 MBBI->eraseFromParent(); // remove it.
549 FoundIt = true;
550 break;
553 RemovedAllMTVRSAVEs &= FoundIt;
557 // If we found and removed all MTVRSAVE instructions, remove the read of
558 // VRSAVE as well.
559 if (RemovedAllMTVRSAVEs) {
560 MBBI = MI;
561 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
562 --MBBI;
563 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
564 MBBI->eraseFromParent();
567 // Finally, nuke the UPDATE_VRSAVE.
568 MI->eraseFromParent();
571 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
572 // instruction selector. Based on the vector registers that have been used,
573 // transform this into the appropriate ORI instruction.
574 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
575 MachineFunction *MF = MI->getParent()->getParent();
577 unsigned UsedRegMask = 0;
578 for (unsigned i = 0; i != 32; ++i)
579 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
580 UsedRegMask |= 1 << (31-i);
582 // Live in and live out values already must be in the mask, so don't bother
583 // marking them.
584 for (MachineRegisterInfo::livein_iterator
585 I = MF->getRegInfo().livein_begin(),
586 E = MF->getRegInfo().livein_end(); I != E; ++I) {
587 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
588 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
589 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
591 for (MachineRegisterInfo::liveout_iterator
592 I = MF->getRegInfo().liveout_begin(),
593 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
594 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
595 if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
596 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
599 unsigned SrcReg = MI->getOperand(1).getReg();
600 unsigned DstReg = MI->getOperand(0).getReg();
601 // If no registers are used, turn this into a copy.
602 if (UsedRegMask == 0) {
603 // Remove all VRSAVE code.
604 RemoveVRSaveCode(MI);
605 return;
606 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
607 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
608 .addReg(SrcReg).addImm(UsedRegMask);
609 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
610 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
611 .addReg(SrcReg).addImm(UsedRegMask >> 16);
612 } else {
613 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
614 .addReg(SrcReg).addImm(UsedRegMask >> 16);
615 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
616 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF);
619 // Remove the old UPDATE_VRSAVE instruction.
620 MI->eraseFromParent();
623 /// determineFrameLayout - Determine the size of the frame and maximum call
624 /// frame size.
625 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const {
626 MachineFrameInfo *MFI = MF.getFrameInfo();
628 // Get the number of bytes to allocate from the FrameInfo
629 unsigned FrameSize = MFI->getStackSize();
631 // Get the alignments provided by the target, and the maximum alignment
632 // (if any) of the fixed frame objects.
633 unsigned MaxAlign = MFI->getMaxAlignment();
634 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
635 unsigned AlignMask = TargetAlign - 1; //
637 // If we are a leaf function, and use up to 224 bytes of stack space,
638 // don't have a frame pointer, calls, or dynamic alloca then we do not need
639 // to adjust the stack pointer (we fit in the Red Zone).
640 if (FrameSize <= 224 && // Fits in red zone.
641 !MFI->hasVarSizedObjects() && // No dynamic alloca.
642 !MFI->hasCalls() && // No calls.
643 MaxAlign <= TargetAlign) { // No special alignment.
644 // No need for frame
645 MFI->setStackSize(0);
646 return;
649 // Get the maximum call frame size of all the calls.
650 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
652 // Maximum call frame needs to be at least big enough for linkage and 8 args.
653 unsigned minCallFrameSize =
654 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(),
655 Subtarget.isMachoABI());
656 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
658 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
659 // that allocations will be aligned.
660 if (MFI->hasVarSizedObjects())
661 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
663 // Update maximum call frame size.
664 MFI->setMaxCallFrameSize(maxCallFrameSize);
666 // Include call frame size in total.
667 FrameSize += maxCallFrameSize;
669 // Make sure the frame is aligned.
670 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
672 // Update frame info.
673 MFI->setStackSize(FrameSize);
676 void PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
677 RegScavenger *RS)
678 const {
679 // Save and clear the LR state.
680 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
681 unsigned LR = getRARegister();
682 FI->setUsesLR(MF.getRegInfo().isPhysRegUsed(LR));
683 MF.getRegInfo().setPhysRegUnused(LR);
685 // Save R31 if necessary
686 int FPSI = FI->getFramePointerSaveIndex();
687 bool IsPPC64 = Subtarget.isPPC64();
688 bool IsELF32_ABI = Subtarget.isELF32_ABI();
689 bool IsMachoABI = Subtarget.isMachoABI();
690 const MachineFrameInfo *MFI = MF.getFrameInfo();
692 // If the frame pointer save index hasn't been defined yet.
693 if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects()) &&
694 IsELF32_ABI) {
695 // Find out what the fix offset of the frame pointer save area.
696 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
697 IsMachoABI);
698 // Allocate the frame index for frame pointer save area.
699 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
700 // Save the result.
701 FI->setFramePointerSaveIndex(FPSI);
706 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
707 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
708 MachineBasicBlock::iterator MBBI = MBB.begin();
709 MachineFrameInfo *MFI = MF.getFrameInfo();
710 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
712 // Prepare for frame info.
713 unsigned FrameLabelId = 0;
715 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
716 // process it.
717 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
718 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
719 HandleVRSaveUpdate(MBBI, TII);
720 break;
724 // Move MBBI back to the beginning of the function.
725 MBBI = MBB.begin();
727 // Work out frame sizes.
728 determineFrameLayout(MF);
729 unsigned FrameSize = MFI->getStackSize();
731 int NegFrameSize = -FrameSize;
733 // Get processor type.
734 bool IsPPC64 = Subtarget.isPPC64();
735 // Get operating system
736 bool IsMachoABI = Subtarget.isMachoABI();
737 // Check if the link register (LR) has been used.
738 bool UsesLR = MustSaveLR(MF);
739 // Do we have a frame pointer for this function?
740 bool HasFP = hasFP(MF) && FrameSize;
742 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
743 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
745 if (IsPPC64) {
746 if (UsesLR)
747 BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0);
749 if (HasFP)
750 BuildMI(MBB, MBBI, TII.get(PPC::STD))
751 .addReg(PPC::X31).addImm(FPOffset/4).addReg(PPC::X1);
753 if (UsesLR)
754 BuildMI(MBB, MBBI, TII.get(PPC::STD))
755 .addReg(PPC::X0).addImm(LROffset/4).addReg(PPC::X1);
756 } else {
757 if (UsesLR)
758 BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0);
760 if (HasFP)
761 BuildMI(MBB, MBBI, TII.get(PPC::STW))
762 .addReg(PPC::R31).addImm(FPOffset).addReg(PPC::R1);
764 if (UsesLR)
765 BuildMI(MBB, MBBI, TII.get(PPC::STW))
766 .addReg(PPC::R0).addImm(LROffset).addReg(PPC::R1);
769 // Skip if a leaf routine.
770 if (!FrameSize) return;
772 // Get stack alignments.
773 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
774 unsigned MaxAlign = MFI->getMaxAlignment();
776 if (MMI && MMI->needsFrameInfo()) {
777 // Mark effective beginning of when frame pointer becomes valid.
778 FrameLabelId = MMI->NextLabelID();
779 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId);
782 // Adjust stack pointer: r1 += NegFrameSize.
783 // If there is a preferred stack alignment, align R1 now
784 if (!IsPPC64) {
785 // PPC32.
786 if (MaxAlign > TargetAlign) {
787 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
788 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
789 BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0)
790 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
791 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0).addReg(PPC::R0)
792 .addImm(NegFrameSize);
793 BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
794 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
795 } else if (isInt16(NegFrameSize)) {
796 BuildMI(MBB, MBBI, TII.get(PPC::STWU),
797 PPC::R1).addReg(PPC::R1).addImm(NegFrameSize).addReg(PPC::R1);
798 } else {
799 BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0).addImm(NegFrameSize >> 16);
800 BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0)
801 .addImm(NegFrameSize & 0xFFFF);
802 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)).addReg(PPC::R1).addReg(PPC::R1)
803 .addReg(PPC::R0);
805 } else { // PPC64.
806 if (MaxAlign > TargetAlign) {
807 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
808 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
809 BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0)
810 .addReg(PPC::X1).addImm(0).addImm(64-Log2_32(MaxAlign));
811 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0).addReg(PPC::X0)
812 .addImm(NegFrameSize);
813 BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
814 .addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0);
815 } else if (isInt16(NegFrameSize)) {
816 BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1)
817 .addReg(PPC::X1).addImm(NegFrameSize/4).addReg(PPC::X1);
818 } else {
819 BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0).addImm(NegFrameSize >>16);
820 BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0).addReg(PPC::X0)
821 .addImm(NegFrameSize & 0xFFFF);
822 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)).addReg(PPC::X1).addReg(PPC::X1)
823 .addReg(PPC::X0);
827 if (MMI && MMI->needsFrameInfo()) {
828 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
830 if (NegFrameSize) {
831 // Show update of SP.
832 MachineLocation SPDst(MachineLocation::VirtualFP);
833 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
834 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
835 } else {
836 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31);
837 Moves.push_back(MachineMove(FrameLabelId, SP, SP));
840 if (HasFP) {
841 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
842 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31);
843 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
846 // Add callee saved registers to move list.
847 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
848 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
849 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
850 unsigned Reg = CSI[I].getReg();
851 if (Reg == PPC::LR || Reg == PPC::LR8) continue;
852 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
853 MachineLocation CSSrc(Reg);
854 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
857 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
858 MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR);
859 Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc));
861 // Mark effective beginning of when frame pointer is ready.
862 unsigned ReadyLabelId = MMI->NextLabelID();
863 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId);
865 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
866 (IsPPC64 ? PPC::X1 : PPC::R1));
867 MachineLocation FPSrc(MachineLocation::VirtualFP);
868 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
871 // If there is a frame pointer, copy R1 into R31
872 if (HasFP) {
873 if (!IsPPC64) {
874 BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31).addReg(PPC::R1)
875 .addReg(PPC::R1);
876 } else {
877 BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31).addReg(PPC::X1)
878 .addReg(PPC::X1);
883 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
884 MachineBasicBlock &MBB) const {
885 MachineBasicBlock::iterator MBBI = prior(MBB.end());
886 assert(MBBI->getOpcode() == PPC::BLR &&
887 "Can only insert epilog into returning blocks");
889 // Get alignment info so we know how to restore r1
890 const MachineFrameInfo *MFI = MF.getFrameInfo();
891 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
892 unsigned MaxAlign = MFI->getMaxAlignment();
894 // Get the number of bytes allocated from the FrameInfo.
895 unsigned FrameSize = MFI->getStackSize();
897 // Get processor type.
898 bool IsPPC64 = Subtarget.isPPC64();
899 // Get operating system
900 bool IsMachoABI = Subtarget.isMachoABI();
901 // Check if the link register (LR) has been used.
902 bool UsesLR = MustSaveLR(MF);
903 // Do we have a frame pointer for this function?
904 bool HasFP = hasFP(MF) && FrameSize;
906 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
907 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
909 if (FrameSize) {
910 // The loaded (or persistent) stack pointer value is offset by the 'stwu'
911 // on entry to the function. Add this offset back now.
912 if (!Subtarget.isPPC64()) {
913 if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
914 !MFI->hasVarSizedObjects()) {
915 BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1)
916 .addReg(PPC::R1).addImm(FrameSize);
917 } else {
918 BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1);
920 } else {
921 if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
922 !MFI->hasVarSizedObjects()) {
923 BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1)
924 .addReg(PPC::X1).addImm(FrameSize);
925 } else {
926 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1);
931 if (IsPPC64) {
932 if (UsesLR)
933 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0)
934 .addImm(LROffset/4).addReg(PPC::X1);
936 if (HasFP)
937 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31)
938 .addImm(FPOffset/4).addReg(PPC::X1);
940 if (UsesLR)
941 BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0);
942 } else {
943 if (UsesLR)
944 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0)
945 .addImm(LROffset).addReg(PPC::R1);
947 if (HasFP)
948 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31)
949 .addImm(FPOffset).addReg(PPC::R1);
951 if (UsesLR)
952 BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0);
956 unsigned PPCRegisterInfo::getRARegister() const {
957 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
960 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
961 if (!Subtarget.isPPC64())
962 return hasFP(MF) ? PPC::R31 : PPC::R1;
963 else
964 return hasFP(MF) ? PPC::X31 : PPC::X1;
967 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
968 const {
969 // Initial state of the frame pointer is R1.
970 MachineLocation Dst(MachineLocation::VirtualFP);
971 MachineLocation Src(PPC::R1, 0);
972 Moves.push_back(MachineMove(0, Dst, Src));
975 unsigned PPCRegisterInfo::getEHExceptionRegister() const {
976 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
979 unsigned PPCRegisterInfo::getEHHandlerRegister() const {
980 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
983 int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
984 // FIXME: Most probably dwarf numbers differs for Linux and Darwin
985 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
988 #include "PPCGenRegisterInfo.inc"