test/tools/llvm-mca/X86/BtVer2/register-files-4.s

   1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
   2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=22 -dispatch-stats -register-file-stats -resource-pressure=false -timeline -timeline-max-iterations=3 < %s | FileCheck %s
   3
   4 idiv %eax
   5
   6 # CHECK:      Iterations:        22
   7 # CHECK-NEXT: Instructions:      22
   8 # CHECK-NEXT: Total Cycles:      553
   9 # CHECK-NEXT: Total uOps:        44
  10
  11 # CHECK:      Dispatch Width:    2
  12 # CHECK-NEXT: uOps Per Cycle:    0.08
  13 # CHECK-NEXT: IPC:               0.04
  14 # CHECK-NEXT: Block RThroughput: 25.0
  15
  16 # CHECK:      Instruction Info:
  17 # CHECK-NEXT: [1]: #uOps
  18 # CHECK-NEXT: [2]: Latency
  19 # CHECK-NEXT: [3]: RThroughput
  20 # CHECK-NEXT: [4]: MayLoad
  21 # CHECK-NEXT: [5]: MayStore
  22 # CHECK-NEXT: [6]: HasSideEffects (U)
  23
  24 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
  25 # CHECK-NEXT:  2      25    25.00                 U     idivl   %eax
  26
  27 # CHECK:      Dynamic Dispatch Stall Cycles:
  28 # CHECK-NEXT: RAT     - Register unavailable:                      6  (1.1%)
  29 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
  30 # CHECK-NEXT: SCHEDQ  - Scheduler full:                            5  (0.9%)
  31 # CHECK-NEXT: LQ      - Load queue full:                           0
  32 # CHECK-NEXT: SQ      - Store queue full:                          0
  33 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
  34
  35 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
  36 # CHECK-NEXT: [# dispatched], [# cycles]
  37 # CHECK-NEXT:  0,              531  (96.0%)
  38 # CHECK-NEXT:  2,              22  (4.0%)
  39
  40 # CHECK:      Register File statistics:
  41 # CHECK-NEXT: Total number of mappings created:    66
  42 # CHECK-NEXT: Max number of mappings used:         63
  43
  44 # CHECK:      *  Register File #1 -- JFpuPRF:
  45 # CHECK-NEXT:    Number of physical registers:     72
  46 # CHECK-NEXT:    Total number of mappings created: 0
  47 # CHECK-NEXT:    Max number of mappings used:      0
  48
  49 # CHECK:      *  Register File #2 -- JIntegerPRF:
  50 # CHECK-NEXT:    Number of physical registers:     64
  51 # CHECK-NEXT:    Total number of mappings created: 66
  52 # CHECK-NEXT:    Max number of mappings used:      63
  53
  54 # CHECK:      Timeline view:
  55 # CHECK-NEXT:                     0123456789          0123456789          0123456789          01234567
  56 # CHECK-NEXT: Index     0123456789          0123456789          0123456789          0123456789
  57
  58 # CHECK:      [0,0]     DeeeeeeeeeeeeeeeeeeeeeeeeeER  .    .    .    .    .    .    .    .    .    . .   idivl  %eax
  59 # CHECK-NEXT: [1,0]     .D========================eeeeeeeeeeeeeeeeeeeeeeeeeER  .    .    .    .    . .   idivl  %eax
  60 # CHECK-NEXT: [2,0]     . D================================================eeeeeeeeeeeeeeeeeeeeeeeeeER   idivl  %eax
  61
  62 # CHECK:      Average Wait times (based on the timeline view):
  63 # CHECK-NEXT: [0]: Executions
  64 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
  65 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
  66 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
  67
  68 # CHECK:            [0]    [1]    [2]    [3]
  69 # CHECK-NEXT: 0.     3     25.0   0.3    0.0       idivl        %eax