test/tools/llvm-mca/X86/Znver1/partial-reg-update-7.s

   1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
   2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1 -resource-pressure=false -timeline < %s | FileCheck %s
   3
   4 # An instruction that writes to a 32-bit register will not have any false
   5 # dependence on the corresponding 64-bit register because the upper part of
   6 # the 64-bit register is set to zero
   7
   8 imulq %rax, %rcx
   9 addl  %edx, %ecx
  10 addq  %rcx, %rdx
  11
  12 # CHECK:      Iterations:        1
  13 # CHECK-NEXT: Instructions:      3
  14 # CHECK-NEXT: Total Cycles:      9
  15 # CHECK-NEXT: Total uOps:        4
  16
  17 # CHECK:      Dispatch Width:    4
  18 # CHECK-NEXT: uOps Per Cycle:    0.44
  19 # CHECK-NEXT: IPC:               0.33
  20 # CHECK-NEXT: Block RThroughput: 1.0
  21
  22 # CHECK:      Instruction Info:
  23 # CHECK-NEXT: [1]: #uOps
  24 # CHECK-NEXT: [2]: Latency
  25 # CHECK-NEXT: [3]: RThroughput
  26 # CHECK-NEXT: [4]: MayLoad
  27 # CHECK-NEXT: [5]: MayStore
  28 # CHECK-NEXT: [6]: HasSideEffects (U)
  29
  30 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
  31 # CHECK-NEXT:  2      4     1.00                        imulq   %rax, %rcx
  32 # CHECK-NEXT:  1      1     0.25                        addl    %edx, %ecx
  33 # CHECK-NEXT:  1      1     0.25                        addq    %rcx, %rdx
  34
  35 # CHECK:      Timeline view:
  36 # CHECK-NEXT: Index     012345678
  37
  38 # CHECK:      [0,0]     DeeeeER .   imulq       %rax, %rcx
  39 # CHECK-NEXT: [0,1]     D====eER.   addl        %edx, %ecx
  40 # CHECK-NEXT: [0,2]     D=====eER   addq        %rcx, %rdx
  41
  42 # CHECK:      Average Wait times (based on the timeline view):
  43 # CHECK-NEXT: [0]: Executions
  44 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
  45 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
  46 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
  47
  48 # CHECK:            [0]    [1]    [2]    [3]
  49 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       imulq        %rax, %rcx
  50 # CHECK-NEXT: 1.     1     5.0    0.0    0.0       addl %edx, %ecx
  51 # CHECK-NEXT: 2.     1     6.0    0.0    0.0       addq %rcx, %rdx