lib/MC/MCSubtargetInfo.cpp

   1 //===- MCSubtargetInfo.cpp - Subtarget Information ------------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 #include "llvm/MC/MCSubtargetInfo.h"
  10 #include "llvm/ADT/ArrayRef.h"
  11 #include "llvm/ADT/StringRef.h"
  12 #include "llvm/MC/MCInstrItineraries.h"
  13 #include "llvm/MC/MCSchedule.h"
  14 #include "llvm/MC/SubtargetFeature.h"
  15 #include "llvm/Support/raw_ostream.h"
  16 #include <algorithm>
  17 #include <cassert>
  18 #include <cstring>
  19
  20 using namespace llvm;
  21
  22 static FeatureBitset getFeatures(StringRef CPU, StringRef FS,
  23                                  ArrayRef<SubtargetFeatureKV> ProcDesc,
  24                                  ArrayRef<SubtargetFeatureKV> ProcFeatures) {
  25   SubtargetFeatures Features(FS);
  26   return Features.getFeatureBits(CPU, ProcDesc, ProcFeatures);
  27 }
  28
  29 void MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) {
  30   FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures);
  31   if (!CPU.empty())
  32     CPUSchedModel = &getSchedModelForCPU(CPU);
  33   else
  34     CPUSchedModel = &MCSchedModel::GetDefaultSchedModel();
  35 }
  36
  37 void MCSubtargetInfo::setDefaultFeatures(StringRef CPU, StringRef FS) {
  38   FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures);
  39 }
  40
  41 MCSubtargetInfo::MCSubtargetInfo(
  42     const Triple &TT, StringRef C, StringRef FS,
  43     ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
  44     const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
  45     const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
  46     const InstrStage *IS, const unsigned *OC, const unsigned *FP)
  47     : TargetTriple(TT), CPU(C), ProcFeatures(PF), ProcDesc(PD),
  48       ProcSchedModels(ProcSched), WriteProcResTable(WPR), WriteLatencyTable(WL),
  49       ReadAdvanceTable(RA), Stages(IS), OperandCycles(OC), ForwardingPaths(FP) {
  50   InitMCProcessorInfo(CPU, FS);
  51 }
  52
  53 FeatureBitset MCSubtargetInfo::ToggleFeature(uint64_t FB) {
  54   FeatureBits.flip(FB);
  55   return FeatureBits;
  56 }
  57
  58 FeatureBitset MCSubtargetInfo::ToggleFeature(const FeatureBitset &FB) {
  59   FeatureBits ^= FB;
  60   return FeatureBits;
  61 }
  62
  63 FeatureBitset MCSubtargetInfo::ToggleFeature(StringRef FS) {
  64   SubtargetFeatures::ToggleFeature(FeatureBits, FS, ProcFeatures);
  65   return FeatureBits;
  66 }
  67
  68 FeatureBitset MCSubtargetInfo::ApplyFeatureFlag(StringRef FS) {
  69   SubtargetFeatures::ApplyFeatureFlag(FeatureBits, FS, ProcFeatures);
  70   return FeatureBits;
  71 }
  72
  73 bool MCSubtargetInfo::checkFeatures(StringRef FS) const {
  74   SubtargetFeatures T(FS);
  75   FeatureBitset Set, All;
  76   for (std::string F : T.getFeatures()) {
  77     SubtargetFeatures::ApplyFeatureFlag(Set, F, ProcFeatures);
  78     if (F[0] == '-')
  79       F[0] = '+';
  80     SubtargetFeatures::ApplyFeatureFlag(All, F, ProcFeatures);
  81   }
  82   return (FeatureBits & All) == Set;
  83 }
  84
  85 const MCSchedModel &MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
  86   assert(ProcSchedModels && "Processor machine model not available!");
  87
  88   ArrayRef<SubtargetInfoKV> SchedModels(ProcSchedModels, ProcDesc.size());
  89
  90   assert(std::is_sorted(SchedModels.begin(), SchedModels.end(),
  91                     [](const SubtargetInfoKV &LHS, const SubtargetInfoKV &RHS) {
  92                       return strcmp(LHS.Key, RHS.Key) < 0;
  93                     }) &&
  94          "Processor machine model table is not sorted");
  95
  96   // Find entry
  97   auto Found =
  98     std::lower_bound(SchedModels.begin(), SchedModels.end(), CPU);
  99   if (Found == SchedModels.end() || StringRef(Found->Key) != CPU) {
 100     if (CPU != "help") // Don't error if the user asked for help.
 101       errs() << "'" << CPU
 102              << "' is not a recognized processor for this target"
 103              << " (ignoring processor)\n";
 104     return MCSchedModel::GetDefaultSchedModel();
 105   }
 106   assert(Found->Value && "Missing processor SchedModel value");
 107   return *(const MCSchedModel *)Found->Value;
 108 }
 109
 110 InstrItineraryData
 111 MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
 112   const MCSchedModel &SchedModel = getSchedModelForCPU(CPU);
 113   return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
 114 }
 115
 116 void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
 117   InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles,
 118                                   ForwardingPaths);
 119 }