utils/TableGen/InstrInfoEmitter.cpp

   1 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. --*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This tablegen backend is responsible for emitting a description of the target
  10 // instruction set for the code generator.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "CodeGenDAGPatterns.h"
  15 #include "CodeGenInstruction.h"
  16 #include "CodeGenSchedule.h"
  17 #include "CodeGenTarget.h"
  18 #include "PredicateExpander.h"
  19 #include "SequenceToOffsetTable.h"
  20 #include "TableGenBackends.h"
  21 #include "llvm/ADT/ArrayRef.h"
  22 #include "llvm/ADT/StringExtras.h"
  23 #include "llvm/Support/Casting.h"
  24 #include "llvm/Support/raw_ostream.h"
  25 #include "llvm/TableGen/Error.h"
  26 #include "llvm/TableGen/Record.h"
  27 #include "llvm/TableGen/TableGenBackend.h"
  28 #include <cassert>
  29 #include <cstdint>
  30 #include <map>
  31 #include <string>
  32 #include <utility>
  33 #include <vector>
  34
  35 using namespace llvm;
  36
  37 namespace {
  38
  39 class InstrInfoEmitter {
  40   RecordKeeper &Records;
  41   CodeGenDAGPatterns CDP;
  42   const CodeGenSchedModels &SchedModels;
  43
  44 public:
  45   InstrInfoEmitter(RecordKeeper &R):
  46     Records(R), CDP(R), SchedModels(CDP.getTargetInfo().getSchedModels()) {}
  47
  48   // run - Output the instruction set description.
  49   void run(raw_ostream &OS);
  50
  51 private:
  52   void emitEnums(raw_ostream &OS);
  53
  54   typedef std::map<std::vector<std::string>, unsigned> OperandInfoMapTy;
  55
  56   /// The keys of this map are maps which have OpName enum values as their keys
  57   /// and instruction operand indices as their values.  The values of this map
  58   /// are lists of instruction names.
  59   typedef std::map<std::map<unsigned, unsigned>,
  60                    std::vector<std::string>> OpNameMapTy;
  61   typedef std::map<std::string, unsigned>::iterator StrUintMapIter;
  62
  63   /// Generate member functions in the target-specific GenInstrInfo class.
  64   ///
  65   /// This method is used to custom expand TIIPredicate definitions.
  66   /// See file llvm/Target/TargetInstPredicates.td for a description of what is
  67   /// a TIIPredicate and how to use it.
  68   void emitTIIHelperMethods(raw_ostream &OS, StringRef TargetName,
  69                             bool ExpandDefinition = true);
  70
  71   /// Expand TIIPredicate definitions to functions that accept a const MCInst
  72   /// reference.
  73   void emitMCIIHelperMethods(raw_ostream &OS, StringRef TargetName);
  74   void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
  75                   Record *InstrInfo,
  76                   std::map<std::vector<Record*>, unsigned> &EL,
  77                   const OperandInfoMapTy &OpInfo,
  78                   raw_ostream &OS);
  79   void emitOperandTypesEnum(raw_ostream &OS, const CodeGenTarget &Target);
  80   void initOperandMapData(
  81             ArrayRef<const CodeGenInstruction *> NumberedInstructions,
  82             StringRef Namespace,
  83             std::map<std::string, unsigned> &Operands,
  84             OpNameMapTy &OperandMap);
  85   void emitOperandNameMappings(raw_ostream &OS, const CodeGenTarget &Target,
  86             ArrayRef<const CodeGenInstruction*> NumberedInstructions);
  87
  88   // Operand information.
  89   void EmitOperandInfo(raw_ostream &OS, OperandInfoMapTy &OperandInfoIDs);
  90   std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
  91 };
  92
  93 } // end anonymous namespace
  94
  95 static void PrintDefList(const std::vector<Record*> &Uses,
  96                          unsigned Num, raw_ostream &OS) {
  97   OS << "static const MCPhysReg ImplicitList" << Num << "[] = { ";
  98   for (Record *U : Uses)
  99     OS << getQualifiedName(U) << ", ";
 100   OS << "0 };\n";
 101 }
 102
 103 //===----------------------------------------------------------------------===//
 104 // Operand Info Emission.
 105 //===----------------------------------------------------------------------===//
 106
 107 std::vector<std::string>
 108 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
 109   std::vector<std::string> Result;
 110
 111   for (auto &Op : Inst.Operands) {
 112     // Handle aggregate operands and normal operands the same way by expanding
 113     // either case into a list of operands for this op.
 114     std::vector<CGIOperandList::OperandInfo> OperandList;
 115
 116     // This might be a multiple operand thing.  Targets like X86 have
 117     // registers in their multi-operand operands.  It may also be an anonymous
 118     // operand, which has a single operand, but no declared class for the
 119     // operand.
 120     DagInit *MIOI = Op.MIOperandInfo;
 121
 122     if (!MIOI || MIOI->getNumArgs() == 0) {
 123       // Single, anonymous, operand.
 124       OperandList.push_back(Op);
 125     } else {
 126       for (unsigned j = 0, e = Op.MINumOperands; j != e; ++j) {
 127         OperandList.push_back(Op);
 128
 129         auto *OpR = cast<DefInit>(MIOI->getArg(j))->getDef();
 130         OperandList.back().Rec = OpR;
 131       }
 132     }
 133
 134     for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
 135       Record *OpR = OperandList[j].Rec;
 136       std::string Res;
 137
 138       if (OpR->isSubClassOf("RegisterOperand"))
 139         OpR = OpR->getValueAsDef("RegClass");
 140       if (OpR->isSubClassOf("RegisterClass"))
 141         Res += getQualifiedName(OpR) + "RegClassID, ";
 142       else if (OpR->isSubClassOf("PointerLikeRegClass"))
 143         Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", ";
 144       else
 145         // -1 means the operand does not have a fixed register class.
 146         Res += "-1, ";
 147
 148       // Fill in applicable flags.
 149       Res += "0";
 150
 151       // Ptr value whose register class is resolved via callback.
 152       if (OpR->isSubClassOf("PointerLikeRegClass"))
 153         Res += "|(1<<MCOI::LookupPtrRegClass)";
 154
 155       // Predicate operands.  Check to see if the original unexpanded operand
 156       // was of type PredicateOp.
 157       if (Op.Rec->isSubClassOf("PredicateOp"))
 158         Res += "|(1<<MCOI::Predicate)";
 159
 160       // Optional def operands.  Check to see if the original unexpanded operand
 161       // was of type OptionalDefOperand.
 162       if (Op.Rec->isSubClassOf("OptionalDefOperand"))
 163         Res += "|(1<<MCOI::OptionalDef)";
 164
 165       // Fill in operand type.
 166       Res += ", ";
 167       assert(!Op.OperandType.empty() && "Invalid operand type.");
 168       Res += Op.OperandType;
 169
 170       // Fill in constraint info.
 171       Res += ", ";
 172
 173       const CGIOperandList::ConstraintInfo &Constraint =
 174         Op.Constraints[j];
 175       if (Constraint.isNone())
 176         Res += "0";
 177       else if (Constraint.isEarlyClobber())
 178         Res += "(1 << MCOI::EARLY_CLOBBER)";
 179       else {
 180         assert(Constraint.isTied());
 181         Res += "((" + utostr(Constraint.getTiedOperand()) +
 182                     " << 16) | (1 << MCOI::TIED_TO))";
 183       }
 184
 185       Result.push_back(Res);
 186     }
 187   }
 188
 189   return Result;
 190 }
 191
 192 void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
 193                                        OperandInfoMapTy &OperandInfoIDs) {
 194   // ID #0 is for no operand info.
 195   unsigned OperandListNum = 0;
 196   OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
 197
 198   OS << "\n";
 199   const CodeGenTarget &Target = CDP.getTargetInfo();
 200   for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
 201     std::vector<std::string> OperandInfo = GetOperandInfo(*Inst);
 202     unsigned &N = OperandInfoIDs[OperandInfo];
 203     if (N != 0) continue;
 204
 205     N = ++OperandListNum;
 206     OS << "static const MCOperandInfo OperandInfo" << N << "[] = { ";
 207     for (const std::string &Info : OperandInfo)
 208       OS << "{ " << Info << " }, ";
 209     OS << "};\n";
 210   }
 211 }
 212
 213 /// Initialize data structures for generating operand name mappings.
 214 ///
 215 /// \param Operands [out] A map used to generate the OpName enum with operand
 216 ///        names as its keys and operand enum values as its values.
 217 /// \param OperandMap [out] A map for representing the operand name mappings for
 218 ///        each instructions.  This is used to generate the OperandMap table as
 219 ///        well as the getNamedOperandIdx() function.
 220 void InstrInfoEmitter::initOperandMapData(
 221         ArrayRef<const CodeGenInstruction *> NumberedInstructions,
 222         StringRef Namespace,
 223         std::map<std::string, unsigned> &Operands,
 224         OpNameMapTy &OperandMap) {
 225   unsigned NumOperands = 0;
 226   for (const CodeGenInstruction *Inst : NumberedInstructions) {
 227     if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable"))
 228       continue;
 229     std::map<unsigned, unsigned> OpList;
 230     for (const auto &Info : Inst->Operands) {
 231       StrUintMapIter I = Operands.find(Info.Name);
 232
 233       if (I == Operands.end()) {
 234         I = Operands.insert(Operands.begin(),
 235                     std::pair<std::string, unsigned>(Info.Name, NumOperands++));
 236       }
 237       OpList[I->second] = Info.MIOperandNo;
 238     }
 239     OperandMap[OpList].push_back(Namespace.str() + "::" +
 240                                  Inst->TheDef->getName().str());
 241   }
 242 }
 243
 244 /// Generate a table and function for looking up the indices of operands by
 245 /// name.
 246 ///
 247 /// This code generates:
 248 /// - An enum in the llvm::TargetNamespace::OpName namespace, with one entry
 249 ///   for each operand name.
 250 /// - A 2-dimensional table called OperandMap for mapping OpName enum values to
 251 ///   operand indices.
 252 /// - A function called getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
 253 ///   for looking up the operand index for an instruction, given a value from
 254 ///   OpName enum
 255 void InstrInfoEmitter::emitOperandNameMappings(raw_ostream &OS,
 256            const CodeGenTarget &Target,
 257            ArrayRef<const CodeGenInstruction*> NumberedInstructions) {
 258   StringRef Namespace = Target.getInstNamespace();
 259   std::string OpNameNS = "OpName";
 260   // Map of operand names to their enumeration value.  This will be used to
 261   // generate the OpName enum.
 262   std::map<std::string, unsigned> Operands;
 263   OpNameMapTy OperandMap;
 264
 265   initOperandMapData(NumberedInstructions, Namespace, Operands, OperandMap);
 266
 267   OS << "#ifdef GET_INSTRINFO_OPERAND_ENUM\n";
 268   OS << "#undef GET_INSTRINFO_OPERAND_ENUM\n";
 269   OS << "namespace llvm {\n";
 270   OS << "namespace " << Namespace << " {\n";
 271   OS << "namespace " << OpNameNS << " {\n";
 272   OS << "enum {\n";
 273   for (const auto &Op : Operands)
 274     OS << "  " << Op.first << " = " << Op.second << ",\n";
 275
 276   OS << "OPERAND_LAST";
 277   OS << "\n};\n";
 278   OS << "} // end namespace OpName\n";
 279   OS << "} // end namespace " << Namespace << "\n";
 280   OS << "} // end namespace llvm\n";
 281   OS << "#endif //GET_INSTRINFO_OPERAND_ENUM\n\n";
 282
 283   OS << "#ifdef GET_INSTRINFO_NAMED_OPS\n";
 284   OS << "#undef GET_INSTRINFO_NAMED_OPS\n";
 285   OS << "namespace llvm {\n";
 286   OS << "namespace " << Namespace << " {\n";
 287   OS << "LLVM_READONLY\n";
 288   OS << "int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {\n";
 289   if (!Operands.empty()) {
 290     OS << "  static const int16_t OperandMap [][" << Operands.size()
 291        << "] = {\n";
 292     for (const auto &Entry : OperandMap) {
 293       const std::map<unsigned, unsigned> &OpList = Entry.first;
 294       OS << "{";
 295
 296       // Emit a row of the OperandMap table
 297       for (unsigned i = 0, e = Operands.size(); i != e; ++i)
 298         OS << (OpList.count(i) == 0 ? -1 : (int)OpList.find(i)->second) << ", ";
 299
 300       OS << "},\n";
 301     }
 302     OS << "};\n";
 303
 304     OS << "  switch(Opcode) {\n";
 305     unsigned TableIndex = 0;
 306     for (const auto &Entry : OperandMap) {
 307       for (const std::string &Name : Entry.second)
 308         OS << "  case " << Name << ":\n";
 309
 310       OS << "    return OperandMap[" << TableIndex++ << "][NamedIdx];\n";
 311     }
 312     OS << "    default: return -1;\n";
 313     OS << "  }\n";
 314   } else {
 315     // There are no operands, so no need to emit anything
 316     OS << "  return -1;\n";
 317   }
 318   OS << "}\n";
 319   OS << "} // end namespace " << Namespace << "\n";
 320   OS << "} // end namespace llvm\n";
 321   OS << "#endif //GET_INSTRINFO_NAMED_OPS\n\n";
 322 }
 323
 324 /// Generate an enum for all the operand types for this target, under the
 325 /// llvm::TargetNamespace::OpTypes namespace.
 326 /// Operand types are all definitions derived of the Operand Target.td class.
 327 void InstrInfoEmitter::emitOperandTypesEnum(raw_ostream &OS,
 328                                             const CodeGenTarget &Target) {
 329
 330   StringRef Namespace = Target.getInstNamespace();
 331   std::vector<Record *> Operands = Records.getAllDerivedDefinitions("Operand");
 332
 333   OS << "#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
 334   OS << "#undef GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
 335   OS << "namespace llvm {\n";
 336   OS << "namespace " << Namespace << " {\n";
 337   OS << "namespace OpTypes {\n";
 338   OS << "enum OperandType {\n";
 339
 340   unsigned EnumVal = 0;
 341   for (const Record *Op : Operands) {
 342     if (!Op->isAnonymous())
 343       OS << "  " << Op->getName() << " = " << EnumVal << ",\n";
 344     ++EnumVal;
 345   }
 346
 347   OS << "  OPERAND_TYPE_LIST_END" << "\n};\n";
 348   OS << "} // end namespace OpTypes\n";
 349   OS << "} // end namespace " << Namespace << "\n";
 350   OS << "} // end namespace llvm\n";
 351   OS << "#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM\n\n";
 352 }
 353
 354 void InstrInfoEmitter::emitMCIIHelperMethods(raw_ostream &OS,
 355                                              StringRef TargetName) {
 356   RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate");
 357   if (TIIPredicates.empty())
 358     return;
 359
 360   OS << "#ifdef GET_INSTRINFO_MC_HELPER_DECLS\n";
 361   OS << "#undef GET_INSTRINFO_MC_HELPER_DECLS\n\n";
 362
 363   OS << "namespace llvm {\n";
 364   OS << "class MCInst;\n\n";
 365
 366   OS << "namespace " << TargetName << "_MC {\n\n";
 367
 368   for (const Record *Rec : TIIPredicates) {
 369     OS << "bool " << Rec->getValueAsString("FunctionName")
 370         << "(const MCInst &MI);\n";
 371   }
 372
 373   OS << "\n} // end " << TargetName << "_MC namespace\n";
 374   OS << "} // end llvm namespace\n\n";
 375
 376   OS << "#endif // GET_INSTRINFO_MC_HELPER_DECLS\n\n";
 377
 378   OS << "#ifdef GET_INSTRINFO_MC_HELPERS\n";
 379   OS << "#undef GET_INSTRINFO_MC_HELPERS\n\n";
 380
 381   OS << "namespace llvm {\n";
 382   OS << "namespace " << TargetName << "_MC {\n\n";
 383
 384   PredicateExpander PE(TargetName);
 385   PE.setExpandForMC(true);
 386
 387   for (const Record *Rec : TIIPredicates) {
 388     OS << "bool " << Rec->getValueAsString("FunctionName");
 389     OS << "(const MCInst &MI) {\n";
 390
 391     OS.indent(PE.getIndentLevel() * 2);
 392     PE.expandStatement(OS, Rec->getValueAsDef("Body"));
 393     OS << "\n}\n\n";
 394   }
 395
 396   OS << "} // end " << TargetName << "_MC namespace\n";
 397   OS << "} // end llvm namespace\n\n";
 398
 399   OS << "#endif // GET_GENISTRINFO_MC_HELPERS\n";
 400 }
 401
 402 void InstrInfoEmitter::emitTIIHelperMethods(raw_ostream &OS,
 403                                             StringRef TargetName,
 404                                             bool ExpandDefinition) {
 405   RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate");
 406   if (TIIPredicates.empty())
 407     return;
 408
 409   PredicateExpander PE(TargetName);
 410   PE.setExpandForMC(false);
 411
 412   for (const Record *Rec : TIIPredicates) {
 413     OS << (ExpandDefinition ? "" : "static ") << "bool ";
 414     if (ExpandDefinition)
 415       OS << TargetName << "InstrInfo::";
 416     OS << Rec->getValueAsString("FunctionName");
 417     OS << "(const MachineInstr &MI)";
 418     if (!ExpandDefinition) {
 419       OS << ";\n";
 420       continue;
 421     }
 422
 423     OS << " {\n";
 424     OS.indent(PE.getIndentLevel() * 2);
 425     PE.expandStatement(OS, Rec->getValueAsDef("Body"));
 426     OS << "\n}\n\n";
 427   }
 428 }
 429
 430 //===----------------------------------------------------------------------===//
 431 // Main Output.
 432 //===----------------------------------------------------------------------===//
 433
 434 // run - Emit the main instruction description records for the target...
 435 void InstrInfoEmitter::run(raw_ostream &OS) {
 436   emitSourceFileHeader("Target Instruction Enum Values and Descriptors", OS);
 437   emitEnums(OS);
 438
 439   OS << "#ifdef GET_INSTRINFO_MC_DESC\n";
 440   OS << "#undef GET_INSTRINFO_MC_DESC\n";
 441
 442   OS << "namespace llvm {\n\n";
 443
 444   CodeGenTarget &Target = CDP.getTargetInfo();
 445   const std::string &TargetName = Target.getName();
 446   Record *InstrInfo = Target.getInstructionSet();
 447
 448   // Keep track of all of the def lists we have emitted already.
 449   std::map<std::vector<Record*>, unsigned> EmittedLists;
 450   unsigned ListNumber = 0;
 451
 452   // Emit all of the instruction's implicit uses and defs.
 453   for (const CodeGenInstruction *II : Target.getInstructionsByEnumValue()) {
 454     Record *Inst = II->TheDef;
 455     std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
 456     if (!Uses.empty()) {
 457       unsigned &IL = EmittedLists[Uses];
 458       if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
 459     }
 460     std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
 461     if (!Defs.empty()) {
 462       unsigned &IL = EmittedLists[Defs];
 463       if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
 464     }
 465   }
 466
 467   OperandInfoMapTy OperandInfoIDs;
 468
 469   // Emit all of the operand info records.
 470   EmitOperandInfo(OS, OperandInfoIDs);
 471
 472   // Emit all of the MCInstrDesc records in their ENUM ordering.
 473   //
 474   OS << "\nextern const MCInstrDesc " << TargetName << "Insts[] = {\n";
 475   ArrayRef<const CodeGenInstruction*> NumberedInstructions =
 476     Target.getInstructionsByEnumValue();
 477
 478   SequenceToOffsetTable<std::string> InstrNames;
 479   unsigned Num = 0;
 480   for (const CodeGenInstruction *Inst : NumberedInstructions) {
 481     // Keep a list of the instruction names.
 482     InstrNames.add(Inst->TheDef->getName());
 483     // Emit the record into the table.
 484     emitRecord(*Inst, Num++, InstrInfo, EmittedLists, OperandInfoIDs, OS);
 485   }
 486   OS << "};\n\n";
 487
 488   // Emit the array of instruction names.
 489   InstrNames.layout();
 490   OS << "extern const char " << TargetName << "InstrNameData[] = {\n";
 491   InstrNames.emit(OS, printChar);
 492   OS << "};\n\n";
 493
 494   OS << "extern const unsigned " << TargetName <<"InstrNameIndices[] = {";
 495   Num = 0;
 496   for (const CodeGenInstruction *Inst : NumberedInstructions) {
 497     // Newline every eight entries.
 498     if (Num % 8 == 0)
 499       OS << "\n    ";
 500     OS << InstrNames.get(Inst->TheDef->getName()) << "U, ";
 501     ++Num;
 502   }
 503
 504   OS << "\n};\n\n";
 505
 506   // MCInstrInfo initialization routine.
 507   OS << "static inline void Init" << TargetName
 508      << "MCInstrInfo(MCInstrInfo *II) {\n";
 509   OS << "  II->InitMCInstrInfo(" << TargetName << "Insts, "
 510      << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, "
 511      << NumberedInstructions.size() << ");\n}\n\n";
 512
 513   OS << "} // end llvm namespace\n";
 514
 515   OS << "#endif // GET_INSTRINFO_MC_DESC\n\n";
 516
 517   // Create a TargetInstrInfo subclass to hide the MC layer initialization.
 518   OS << "#ifdef GET_INSTRINFO_HEADER\n";
 519   OS << "#undef GET_INSTRINFO_HEADER\n";
 520
 521   std::string ClassName = TargetName + "GenInstrInfo";
 522   OS << "namespace llvm {\n";
 523   OS << "struct " << ClassName << " : public TargetInstrInfo {\n"
 524      << "  explicit " << ClassName
 525      << "(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);\n"
 526      << "  ~" << ClassName << "() override = default;\n";
 527
 528
 529   OS << "\n};\n} // end llvm namespace\n";
 530
 531   OS << "#endif // GET_INSTRINFO_HEADER\n\n";
 532
 533   OS << "#ifdef GET_INSTRINFO_HELPER_DECLS\n";
 534   OS << "#undef GET_INSTRINFO_HELPER_DECLS\n\n";
 535   emitTIIHelperMethods(OS, TargetName, /* ExpandDefintion = */false);
 536   OS << "\n";
 537   OS << "#endif // GET_INSTRINFO_HELPER_DECLS\n\n";
 538
 539   OS << "#ifdef GET_INSTRINFO_HELPERS\n";
 540   OS << "#undef GET_INSTRINFO_HELPERS\n\n";
 541   emitTIIHelperMethods(OS, TargetName, /* ExpandDefintion = */true);
 542   OS << "#endif // GET_INSTRINFO_HELPERS\n\n";
 543
 544   OS << "#ifdef GET_INSTRINFO_CTOR_DTOR\n";
 545   OS << "#undef GET_INSTRINFO_CTOR_DTOR\n";
 546
 547   OS << "namespace llvm {\n";
 548   OS << "extern const MCInstrDesc " << TargetName << "Insts[];\n";
 549   OS << "extern const unsigned " << TargetName << "InstrNameIndices[];\n";
 550   OS << "extern const char " << TargetName << "InstrNameData[];\n";
 551   OS << ClassName << "::" << ClassName
 552      << "(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode)\n"
 553      << "  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {\n"
 554      << "  InitMCInstrInfo(" << TargetName << "Insts, " << TargetName
 555      << "InstrNameIndices, " << TargetName << "InstrNameData, "
 556      << NumberedInstructions.size() << ");\n}\n";
 557   OS << "} // end llvm namespace\n";
 558
 559   OS << "#endif // GET_INSTRINFO_CTOR_DTOR\n\n";
 560
 561   emitOperandNameMappings(OS, Target, NumberedInstructions);
 562
 563   emitOperandTypesEnum(OS, Target);
 564
 565   emitMCIIHelperMethods(OS, TargetName);
 566 }
 567
 568 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
 569                                   Record *InstrInfo,
 570                          std::map<std::vector<Record*>, unsigned> &EmittedLists,
 571                                   const OperandInfoMapTy &OpInfo,
 572                                   raw_ostream &OS) {
 573   int MinOperands = 0;
 574   if (!Inst.Operands.empty())
 575     // Each logical operand can be multiple MI operands.
 576     MinOperands = Inst.Operands.back().MIOperandNo +
 577                   Inst.Operands.back().MINumOperands;
 578
 579   OS << "  { ";
 580   OS << Num << ",\t" << MinOperands << ",\t"
 581      << Inst.Operands.NumDefs << ",\t"
 582      << Inst.TheDef->getValueAsInt("Size") << ",\t"
 583      << SchedModels.getSchedClassIdx(Inst) << ",\t0";
 584
 585   CodeGenTarget &Target = CDP.getTargetInfo();
 586
 587   // Emit all of the target independent flags...
 588   if (Inst.isPseudo)           OS << "|(1ULL<<MCID::Pseudo)";
 589   if (Inst.isReturn)           OS << "|(1ULL<<MCID::Return)";
 590   if (Inst.isEHScopeReturn)    OS << "|(1ULL<<MCID::EHScopeReturn)";
 591   if (Inst.isBranch)           OS << "|(1ULL<<MCID::Branch)";
 592   if (Inst.isIndirectBranch)   OS << "|(1ULL<<MCID::IndirectBranch)";
 593   if (Inst.isCompare)          OS << "|(1ULL<<MCID::Compare)";
 594   if (Inst.isMoveImm)          OS << "|(1ULL<<MCID::MoveImm)";
 595   if (Inst.isMoveReg)          OS << "|(1ULL<<MCID::MoveReg)";
 596   if (Inst.isBitcast)          OS << "|(1ULL<<MCID::Bitcast)";
 597   if (Inst.isAdd)              OS << "|(1ULL<<MCID::Add)";
 598   if (Inst.isTrap)             OS << "|(1ULL<<MCID::Trap)";
 599   if (Inst.isSelect)           OS << "|(1ULL<<MCID::Select)";
 600   if (Inst.isBarrier)          OS << "|(1ULL<<MCID::Barrier)";
 601   if (Inst.hasDelaySlot)       OS << "|(1ULL<<MCID::DelaySlot)";
 602   if (Inst.isCall)             OS << "|(1ULL<<MCID::Call)";
 603   if (Inst.canFoldAsLoad)      OS << "|(1ULL<<MCID::FoldableAsLoad)";
 604   if (Inst.mayLoad)            OS << "|(1ULL<<MCID::MayLoad)";
 605   if (Inst.mayStore)           OS << "|(1ULL<<MCID::MayStore)";
 606   if (Inst.isPredicable)       OS << "|(1ULL<<MCID::Predicable)";
 607   if (Inst.isConvertibleToThreeAddress) OS << "|(1ULL<<MCID::ConvertibleTo3Addr)";
 608   if (Inst.isCommutable)       OS << "|(1ULL<<MCID::Commutable)";
 609   if (Inst.isTerminator)       OS << "|(1ULL<<MCID::Terminator)";
 610   if (Inst.isReMaterializable) OS << "|(1ULL<<MCID::Rematerializable)";
 611   if (Inst.isNotDuplicable)    OS << "|(1ULL<<MCID::NotDuplicable)";
 612   if (Inst.Operands.hasOptionalDef) OS << "|(1ULL<<MCID::HasOptionalDef)";
 613   if (Inst.usesCustomInserter) OS << "|(1ULL<<MCID::UsesCustomInserter)";
 614   if (Inst.hasPostISelHook)    OS << "|(1ULL<<MCID::HasPostISelHook)";
 615   if (Inst.Operands.isVariadic)OS << "|(1ULL<<MCID::Variadic)";
 616   if (Inst.hasSideEffects)     OS << "|(1ULL<<MCID::UnmodeledSideEffects)";
 617   if (Inst.isAsCheapAsAMove)   OS << "|(1ULL<<MCID::CheapAsAMove)";
 618   if (!Target.getAllowRegisterRenaming() || Inst.hasExtraSrcRegAllocReq)
 619     OS << "|(1ULL<<MCID::ExtraSrcRegAllocReq)";
 620   if (!Target.getAllowRegisterRenaming() || Inst.hasExtraDefRegAllocReq)
 621     OS << "|(1ULL<<MCID::ExtraDefRegAllocReq)";
 622   if (Inst.isRegSequence) OS << "|(1ULL<<MCID::RegSequence)";
 623   if (Inst.isExtractSubreg) OS << "|(1ULL<<MCID::ExtractSubreg)";
 624   if (Inst.isInsertSubreg) OS << "|(1ULL<<MCID::InsertSubreg)";
 625   if (Inst.isConvergent) OS << "|(1ULL<<MCID::Convergent)";
 626   if (Inst.variadicOpsAreDefs) OS << "|(1ULL<<MCID::VariadicOpsAreDefs)";
 627
 628   // Emit all of the target-specific flags...
 629   BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
 630   if (!TSF)
 631     PrintFatalError(Inst.TheDef->getLoc(), "no TSFlags?");
 632   uint64_t Value = 0;
 633   for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) {
 634     if (const auto *Bit = dyn_cast<BitInit>(TSF->getBit(i)))
 635       Value |= uint64_t(Bit->getValue()) << i;
 636     else
 637       PrintFatalError(Inst.TheDef->getLoc(),
 638                       "Invalid TSFlags bit in " + Inst.TheDef->getName());
 639   }
 640   OS << ", 0x";
 641   OS.write_hex(Value);
 642   OS << "ULL, ";
 643
 644   // Emit the implicit uses and defs lists...
 645   std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
 646   if (UseList.empty())
 647     OS << "nullptr, ";
 648   else
 649     OS << "ImplicitList" << EmittedLists[UseList] << ", ";
 650
 651   std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
 652   if (DefList.empty())
 653     OS << "nullptr, ";
 654   else
 655     OS << "ImplicitList" << EmittedLists[DefList] << ", ";
 656
 657   // Emit the operand info.
 658   std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
 659   if (OperandInfo.empty())
 660     OS << "nullptr";
 661   else
 662     OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
 663
 664   if (Inst.HasComplexDeprecationPredicate)
 665     // Emit a function pointer to the complex predicate method.
 666     OS << ", -1 "
 667        << ",&get" << Inst.DeprecatedReason << "DeprecationInfo";
 668   else if (!Inst.DeprecatedReason.empty())
 669     // Emit the Subtarget feature.
 670     OS << ", " << Target.getInstNamespace() << "::" << Inst.DeprecatedReason
 671        << " ,nullptr";
 672   else
 673     // Instruction isn't deprecated.
 674     OS << ", -1 ,nullptr";
 675
 676   OS << " },  // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
 677 }
 678
 679 // emitEnums - Print out enum values for all of the instructions.
 680 void InstrInfoEmitter::emitEnums(raw_ostream &OS) {
 681   OS << "#ifdef GET_INSTRINFO_ENUM\n";
 682   OS << "#undef GET_INSTRINFO_ENUM\n";
 683
 684   OS << "namespace llvm {\n\n";
 685
 686   CodeGenTarget Target(Records);
 687
 688   // We must emit the PHI opcode first...
 689   StringRef Namespace = Target.getInstNamespace();
 690
 691   if (Namespace.empty())
 692     PrintFatalError("No instructions defined!");
 693
 694   OS << "namespace " << Namespace << " {\n";
 695   OS << "  enum {\n";
 696   unsigned Num = 0;
 697   for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue())
 698     OS << "    " << Inst->TheDef->getName() << "\t= " << Num++ << ",\n";
 699   OS << "    INSTRUCTION_LIST_END = " << Num << "\n";
 700   OS << "  };\n\n";
 701   OS << "} // end " << Namespace << " namespace\n";
 702   OS << "} // end llvm namespace\n";
 703   OS << "#endif // GET_INSTRINFO_ENUM\n\n";
 704
 705   OS << "#ifdef GET_INSTRINFO_SCHED_ENUM\n";
 706   OS << "#undef GET_INSTRINFO_SCHED_ENUM\n";
 707   OS << "namespace llvm {\n\n";
 708   OS << "namespace " << Namespace << " {\n";
 709   OS << "namespace Sched {\n";
 710   OS << "  enum {\n";
 711   Num = 0;
 712   for (const auto &Class : SchedModels.explicit_classes())
 713     OS << "    " << Class.Name << "\t= " << Num++ << ",\n";
 714   OS << "    SCHED_LIST_END = " << Num << "\n";
 715   OS << "  };\n";
 716   OS << "} // end Sched namespace\n";
 717   OS << "} // end " << Namespace << " namespace\n";
 718   OS << "} // end llvm namespace\n";
 719
 720   OS << "#endif // GET_INSTRINFO_SCHED_ENUM\n\n";
 721 }
 722
 723 namespace llvm {
 724
 725 void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) {
 726   InstrInfoEmitter(RK).run(OS);
 727   EmitMapTable(RK, OS);
 728 }
 729
 730 } // end llvm namespace