test/MC/AMDGPU/xdl-insts-gfx1011-gfx1012.s

   1 // RUN: llvm-mc -arch=amdgcn -mcpu=gfx1011 -show-encoding %s | FileCheck %s
   2 // RUN: llvm-mc -arch=amdgcn -mcpu=gfx1012 -show-encoding %s | FileCheck %s
   3
   4 v_dot2c_f32_f16_e32 v5, v1, v2
   5 // CHECK: encoding: [0x01,0x05,0x0a,0x04]
   6
   7 v_dot2c_f32_f16_e32 v255, v1, v2
   8 // CHECK: encoding: [0x01,0x05,0xfe,0x05]
   9
  10 v_dot2c_f32_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
  11 // CHECK: encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x00]
  12
  13 v_dot2c_f32_f16_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
  14 // CHECK: encoding: [0xfa,0x04,0xfe,0x05,0x01,0xe4,0x00,0x00]
  15
  16 v_dot2c_f32_f16_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
  17 // CHECK: encoding: [0xfa,0x04,0x0a,0x04,0xff,0xe4,0x00,0x00]
  18
  19 v_dot2c_f32_f16_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
  20 // CHECK: encoding: [0xfa,0xfe,0x0b,0x04,0x01,0xe4,0x00,0x00]
  21
  22 v_dot2c_f32_f16_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
  23 // CHECK: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x1b,0x00,0x00]
  24
  25 v_dot2c_f32_f16_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
  26 // CHECK: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x40,0x01,0x00]
  27
  28 v_dot2c_f32_f16_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
  29 // CHECK: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x41,0x01,0x00]
  30
  31 v_dot2c_f32_f16_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
  32 // CHECK: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x01,0x01,0x00]
  33
  34 v_dot2c_f32_f16_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
  35 // CHECK: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x0f,0x01,0x00]
  36
  37 v_dot2c_f32_f16_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
  38 // CHECK: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x11,0x01,0x00]
  39
  40 v_dot2c_f32_f16_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
  41 // CHECK: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x1f,0x01,0x00]
  42
  43 v_dot2c_f32_f16_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
  44 // CHECK: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x21,0x01,0x00]
  45
  46 v_dot2c_f32_f16_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
  47 // CHECK: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x2f,0x01,0x00]
  48
  49 v_dot2c_f32_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
  50 // CHECK: encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x10]
  51
  52 v_dot2c_f32_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
  53 // CHECK: encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x30]
  54
  55 v_dot2c_f32_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
  56 // CHECK: encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0xf0]
  57
  58 v_dot2c_f32_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
  59 // CHECK: encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0xf0]
  60
  61 v_dot2c_f32_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
  62 // CHECK: encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x01]
  63
  64 v_dot2c_f32_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
  65 // CHECK: encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x03]
  66
  67 v_dot2c_f32_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
  68 // CHECK: encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x0f]
  69
  70 v_dot2c_f32_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
  71 // CHECK: encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x0f]
  72
  73 v_dot2c_f32_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
  74 // CHECK: encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x08,0x00]
  75
  76 v_dot2c_f32_f16_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
  77 // CHECK: encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x10,0x00]
  78
  79 v_dot2c_f32_f16_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
  80 // CHECK: encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x20,0x00]
  81
  82 v_dot2c_f32_f16_dpp v5, v1, -v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
  83 // CHECK: encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x40,0x00]
  84
  85 v_dot2c_f32_f16_dpp v5, v1, |v2|  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
  86 // CHECK: encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x80,0x00]
  87
  88 v_dot4c_i32_i8_e32 v5, v1, v2
  89 // CHECK: encoding: [0x01,0x05,0x0a,0x1a]
  90
  91 v_dot4c_i32_i8_e32 v255, v1, v2
  92 // CHECK: encoding: [0x01,0x05,0xfe,0x1b]
  93
  94 v_dot4c_i32_i8_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
  95 // CHECK: encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x00]
  96
  97 v_dot4c_i32_i8_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
  98 // CHECK: encoding: [0xfa,0x04,0xfe,0x1b,0x01,0xe4,0x00,0x00]
  99
 100 v_dot4c_i32_i8_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
 101 // CHECK: encoding: [0xfa,0x04,0x0a,0x1a,0xff,0xe4,0x00,0x00]
 102
 103 v_dot4c_i32_i8_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
 104 // CHECK: encoding: [0xfa,0xfe,0x0b,0x1a,0x01,0xe4,0x00,0x00]
 105
 106 v_dot4c_i32_i8_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 107 // CHECK: encoding: [0xfa,0x04,0x0a,0x1a,0x01,0x1b,0x00,0x00]
 108
 109 v_dot4c_i32_i8_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
 110 // CHECK: encoding: [0xfa,0x04,0x0a,0x1a,0x01,0x40,0x01,0x00]
 111
 112 v_dot4c_i32_i8_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
 113 // CHECK: encoding: [0xfa,0x04,0x0a,0x1a,0x01,0x41,0x01,0x00]
 114
 115 v_dot4c_i32_i8_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
 116 // CHECK: encoding: [0xfa,0x04,0x0a,0x1a,0x01,0x01,0x01,0x00]
 117
 118 v_dot4c_i32_i8_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
 119 // CHECK: encoding: [0xfa,0x04,0x0a,0x1a,0x01,0x0f,0x01,0x00]
 120
 121 v_dot4c_i32_i8_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
 122 // CHECK: encoding: [0xfa,0x04,0x0a,0x1a,0x01,0x11,0x01,0x00]
 123
 124 v_dot4c_i32_i8_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
 125 // CHECK: encoding: [0xfa,0x04,0x0a,0x1a,0x01,0x1f,0x01,0x00]
 126
 127 v_dot4c_i32_i8_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
 128 // CHECK: encoding: [0xfa,0x04,0x0a,0x1a,0x01,0x21,0x01,0x00]
 129
 130 v_dot4c_i32_i8_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
 131 // CHECK: encoding: [0xfa,0x04,0x0a,0x1a,0x01,0x2f,0x01,0x00]
 132
 133 v_dot4c_i32_i8_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
 134 // CHECK: encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x10]
 135
 136 v_dot4c_i32_i8_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
 137 // CHECK: encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x30]
 138
 139 v_dot4c_i32_i8_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
 140 // CHECK: encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0xf0]
 141
 142 v_dot4c_i32_i8_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
 143 // CHECK: encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0xf0]
 144
 145 v_dot4c_i32_i8_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
 146 // CHECK: encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x01]
 147
 148 v_dot4c_i32_i8_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
 149 // CHECK: encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x03]
 150
 151 v_dot4c_i32_i8_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
 152 // CHECK: encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x0f]
 153
 154 v_dot4c_i32_i8_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
 155 // CHECK: encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x0f]
 156
 157 v_dot4c_i32_i8_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
 158 // CHECK: encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x08,0x00]