test/MC/ARM/thumb2-narrow-dp.ll

   1 // RUN: llvm-mc -triple thumbv7 -show-encoding < %s | FileCheck %s
   2
   3 // Test each of the Thumb1 data-processing instructions
   4 // The assembly syntax for these instructions allows an optional Rd register
   5 //   OP{S}{<c>}{<q>}  {<Rd>,} <Rn>, <Rm>
   6 // Assemblers should chose the narrow thumb encoding when possible, i.e.
   7 //   - Rd == Rn
   8 //   - Rd, Rn and Rm are < r8
   9 // In addition, some operations are commutative, allowing the transformation
  10 // when:
  11 //   - Rd == Rn || Rd == Rm
  12 //   - Rd, Rn and Rm are < r8
  13
  14 // ADD immediate (not SP) A8.8.4
  15     ADDS     r0, r0, #5          // T1
  16 // CHECK: adds  r0, r0, #5          @ encoding: [0x40,0x1d]
  17     ADDS     r1, r1, #8          // T2
  18 // CHECK: adds  r1, #8              @ encoding: [0x08,0x31]
  19     ADDS.W   r1, r1, #8          // .w => T3
  20 // CHECK: adds.w r1, r1, #8         @ encoding: [0x11,0xf1,0x08,0x01]
  21     ADDS     r8, r8, #8          // T3
  22 // CHECK: adds.w r8, r8, #8         @ encoding: [0x18,0xf1,0x08,0x08]
  23
  24     IT EQ
  25 // CHECK: it eq                     @ encoding: [0x08,0xbf]
  26     ADDEQ    r0, r0, #5          // T1
  27 // CHECK: addeq r0, r0, #5          @ encoding: [0x40,0x1d]
  28     IT EQ
  29 // CHECK: it eq                     @ encoding: [0x08,0xbf]
  30     ADDEQ    r1, r1, #8          // T2
  31 // CHECK: addeq r1, #8              @ encoding: [0x08,0x31]
  32
  33     IT EQ
  34 // CHECK: it eq                     @ encoding: [0x08,0xbf]
  35     ADDSEQ   r0, r0, #5          // T3
  36 // CHECK: addseq.w r0, r0, #5       @ encoding: [0x10,0xf1,0x05,0x00]
  37     IT EQ
  38 // CHECK: it eq                     @ encoding: [0x08,0xbf]
  39     ADDSEQ   r1, r1, #8          // T3
  40 // CHECK: addseq.w r1, r1, #8       @ encoding: [0x11,0xf1,0x08,0x01]
  41
  42 // ADD register (not SP) A8.8.6 (commutative)
  43     ADDS     r0, r2, r1          // ADDS has T1 narrow 3 operand
  44 // CHECK: adds  r0, r2, r1          @ encoding: [0x50,0x18]
  45     ADDS     r2, r2, r1          // ADDS has T1 narrow 3 operand
  46 // CHECK: adds  r2, r2, r1          @ encoding: [0x52,0x18]
  47     ADD      r3, r1, r3          // T2
  48 // CHECK: add  r3, r1               @ encoding: [0x0b,0x44]
  49
  50     IT EQ
  51 // CHECK: it eq                     @ encoding: [0x08,0xbf]
  52     ADDEQ    r0, r2, r1          // (In IT) ADD has T1 narrow 3 operand
  53 // CHECK: addeq r0, r2, r1          @ encoding: [0x50,0x18]
  54     IT EQ
  55 // CHECK: it eq                     @ encoding: [0x08,0xbf]
  56     ADDEQ    r2, r2, r1          // (In IT) ADD has T1 narrow 3 operand
  57 // CHECK: addeq r2, r2, r1          @ encoding: [0x52,0x18]
  58
  59     IT EQ
  60 // CHECK: it eq                     @ encoding: [0x08,0xbf]
  61     ADDSEQ   r0, r2, r1          // T3
  62 // CHECK: addseq.w r0, r2, r1       @ encoding: [0x12,0xeb,0x01,0x00]
  63     IT EQ
  64 // CHECK: it eq                     @ encoding: [0x08,0xbf]
  65     ADDSEQ   r2, r2, r1          // T3
  66 // CHECK: addseq.w r2, r2, r1       @ encoding: [0x12,0xeb,0x01,0x02]
  67
  68     ADD      r3, r3, r1          // T2
  69 // CHECK: add  r3, r1               @ encoding: [0x0b,0x44]
  70     ADD      r4, r4, pc          // T2
  71 // CHECK: add  r4, pc               @ encoding: [0x7c,0x44]
  72     ADD      r4, pc, r4          // T2
  73 // CHECK: add  r4, pc               @ encoding: [0x7c,0x44]
  74     ADD      pc, pc, r2          // T2
  75 // CHECK: add  pc, r2               @ encoding: [0x97,0x44]
  76     ADD      pc, r2, pc          // T2
  77 // CHECK: add  pc, r2               @ encoding: [0x97,0x44]
  78     ADD      pc, pc, sp          // T2
  79 // CHECK: add   pc, sp              @ encoding: [0xef,0x44]
  80     ADD      pc, sp, pc          // T2
  81 // CHECK: add   pc, sp, pc          @ encoding: [0xef,0x44]
  82
  83 // ADD (SP plus immediate) A8.8.9
  84     ADD      sp, sp, #20         // T2
  85 // FIXME: ARMARM says 'add   sp, sp, #20'
  86 // CHECK: add   sp, #20             @ encoding: [0x05,0xb0]
  87     ADD      sp, sp, #508        // T2
  88 // CHECK: add   sp, #508            @ encoding: [0x7f,0xb0]
  89     ADD      sp, sp, #512        // T3
  90 // CHECK: add.w sp, sp, #512        @ encoding: [0x0d,0xf5,0x00,0x7d]
  91
  92 // ADD (SP plus register) A8.8.10 (commutative)
  93     ADD      r9, sp, r9          // T1
  94 // CHECK: add   r9, sp, r9          @ encoding: [0xe9,0x44]
  95     ADD      r9, r9, sp          // T1
  96 // FIXME: ARMARM says 'add   r9, sp, r9'
  97 // CHECK: add   r9, sp              @ encoding: [0xe9,0x44]
  98     ADD      sp, sp, r10         // T2
  99 // CHECK: add   sp, r10             @ encoding: [0xd5,0x44]
 100     ADD      sp, r10, sp         // T2
 101 // CHECK: add   sp, r10             @ encoding: [0xd5,0x44]
 102     ADD      sp, sp, pc          // T2
 103 // CHECK: add   sp, pc              @ encoding: [0xfd,0x44]
 104
 105 // AND (commutative)
 106     ANDS     r0, r2, r1          // Must be wide - 3 distinct registers
 107     ANDS     r2, r2, r1          // Should choose narrow
 108     ANDS     r2, r1, r2          // Should choose narrow - commutative
 109     ANDS.W   r0, r0, r1          // Explicitly wide
 110     ANDS.W   r3, r1, r3
 111     AND      r0, r1, r0          // Must use wide encoding as not flag-setting
 112     ANDS     r7, r7, r1          // Should use narrow
 113     ANDS     r7, r1, r7          // Commutative
 114     ANDS     r8, r1, r8          // high registers so must use wide encoding
 115     ANDS     r8, r8, r1
 116     ANDS     r0, r8, r0
 117     ANDS     r1, r1, r8
 118     ANDS     r2, r2, r1, lsl #1  // Must use wide - shifted register
 119     ANDS     r0, r1, r0, lsr #1
 120 // CHECK: ands.w  r0, r2, r1              @ encoding: [0x12,0xea,0x01,0x00]
 121 // CHECK: ands    r2, r1                  @ encoding: [0x0a,0x40]
 122 // CHECK: ands    r2, r1                  @ encoding: [0x0a,0x40]
 123 // CHECK: ands.w  r0, r0, r1              @ encoding: [0x10,0xea,0x01,0x00]
 124 // CHECK: ands.w  r3, r1, r3              @ encoding: [0x11,0xea,0x03,0x03]
 125 // CHECK: and.w   r0, r1, r0              @ encoding: [0x01,0xea,0x00,0x00]
 126 // CHECK: ands    r7, r1                  @ encoding: [0x0f,0x40]
 127 // CHECK: ands    r7, r1                  @ encoding: [0x0f,0x40]
 128 // CHECK: ands.w  r8, r1, r8              @ encoding: [0x11,0xea,0x08,0x08]
 129 // CHECK: ands.w  r8, r8, r1              @ encoding: [0x18,0xea,0x01,0x08]
 130 // CHECK: ands.w  r0, r8, r0              @ encoding: [0x18,0xea,0x00,0x00]
 131 // CHECK: ands.w  r1, r1, r8              @ encoding: [0x11,0xea,0x08,0x01]
 132 // CHECK: ands.w  r2, r2, r1, lsl #1      @ encoding: [0x12,0xea,0x41,0x02]
 133 // CHECK: ands.w  r0, r1, r0, lsr #1      @ encoding: [0x11,0xea,0x50,0x00]
 134
 135     IT EQ
 136     ANDEQ    r0, r2, r1          // Must be wide - 3 distinct registers
 137     IT EQ
 138     ANDEQ    r3, r3, r1          // Should choose narrow
 139     IT EQ
 140     ANDEQ    r3, r1, r3          // Should choose narrow - commutative
 141     IT EQ
 142     ANDEQ.W  r0, r0, r1          // Explicitly wide
 143     IT EQ
 144     ANDEQ.W  r2, r1, r2
 145     IT EQ
 146     ANDSEQ   r0, r1, r0          // Must use wide encoding as flag-setting
 147     IT EQ
 148     ANDEQ    r7, r7, r1          // Should use narrow
 149     IT EQ
 150     ANDEQ    r7, r1, r7          // Commutative
 151     IT EQ
 152     ANDEQ    r8, r1, r8          // high registers so must use wide encoding
 153     IT EQ
 154     ANDEQ    r8, r8, r1
 155     IT EQ
 156     ANDEQ    r4, r8, r4
 157     IT EQ
 158     ANDEQ    r4, r4, r8
 159     IT EQ
 160     ANDEQ    r0, r0, r1, lsl #1  // Must use wide - shifted register
 161     IT EQ
 162     ANDEQ    r5, r1, r5, lsr #1
 163 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 164 // CHECK: andeq.w  r0, r2, r1             @ encoding: [0x02,0xea,0x01,0x00]
 165 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 166 // CHECK: andeq    r3, r1                 @ encoding: [0x0b,0x40]
 167 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 168 // CHECK: andeq    r3, r1                 @ encoding: [0x0b,0x40]
 169 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 170 // CHECK: andeq.w  r0, r0, r1             @ encoding: [0x00,0xea,0x01,0x00]
 171 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 172 // CHECK: andeq.w  r2, r1, r2             @ encoding: [0x01,0xea,0x02,0x02]
 173 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 174 // CHECK: andseq.w r0, r1, r0             @ encoding: [0x11,0xea,0x00,0x00]
 175 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 176 // CHECK: andeq    r7, r1                 @ encoding: [0x0f,0x40]
 177 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 178 // CHECK: andeq    r7, r1                 @ encoding: [0x0f,0x40]
 179 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 180 // CHECK: andeq.w  r8, r1, r8             @ encoding: [0x01,0xea,0x08,0x08]
 181 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 182 // CHECK: andeq.w  r8, r8, r1             @ encoding: [0x08,0xea,0x01,0x08]
 183 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 184 // CHECK: andeq.w  r4, r8, r4             @ encoding: [0x08,0xea,0x04,0x04]
 185 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 186 // CHECK: andeq.w  r4, r4, r8             @ encoding: [0x04,0xea,0x08,0x04]
 187 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 188 // CHECK: andeq.w  r0, r0, r1, lsl #1     @ encoding: [0x00,0xea,0x41,0x00]
 189 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 190 // CHECK: andeq.w  r5, r1, r5, lsr #1     @ encoding: [0x01,0xea,0x55,0x05]
 191
 192 // EOR (commutative)
 193     EORS     r0, r2, r1          // Must be wide - 3 distinct registers
 194     EORS     r5, r5, r1          // Should choose narrow
 195     EORS     r5, r1, r5          // Should choose narrow - commutative
 196     EORS.W   r0, r0, r1          // Explicitly wide
 197     EORS.W   r2, r1, r2
 198     EOR      r1, r1, r1          // Must use wide encoding as not flag-setting
 199     EORS     r7, r7, r1          // Should use narrow
 200     EORS     r7, r1, r7          // Commutative
 201     EORS     r8, r1, r8          // high registers so must use wide encoding
 202     EORS     r8, r8, r1
 203     EORS     r6, r8, r6
 204     EORS     r0, r0, r8
 205     EORS     r2, r2, r1, lsl #1  // Must use wide - shifted register
 206     EORS     r0, r1, r0, lsr #1
 207 // CHECK: eors.w  r0, r2, r1              @ encoding: [0x92,0xea,0x01,0x00]
 208 // CHECK: eors    r5, r1                  @ encoding: [0x4d,0x40]
 209 // CHECK: eors    r5, r1                  @ encoding: [0x4d,0x40]
 210 // CHECK: eors.w  r0, r0, r1              @ encoding: [0x90,0xea,0x01,0x00]
 211 // CHECK: eors.w  r2, r1, r2              @ encoding: [0x91,0xea,0x02,0x02]
 212 // CHECK: eor.w   r1, r1, r1              @ encoding: [0x81,0xea,0x01,0x01]
 213 // CHECK: eors    r7, r1                  @ encoding: [0x4f,0x40]
 214 // CHECK: eors    r7, r1                  @ encoding: [0x4f,0x40]
 215 // CHECK: eors.w  r8, r1, r8              @ encoding: [0x91,0xea,0x08,0x08]
 216 // CHECK: eors.w  r8, r8, r1              @ encoding: [0x98,0xea,0x01,0x08]
 217 // CHECK: eors.w  r6, r8, r6              @ encoding: [0x98,0xea,0x06,0x06]
 218 // CHECK: eors.w  r0, r0, r8              @ encoding: [0x90,0xea,0x08,0x00]
 219 // CHECK: eors.w  r2, r2, r1, lsl #1      @ encoding: [0x92,0xea,0x41,0x02]
 220 // CHECK: eors.w  r0, r1, r0, lsr #1      @ encoding: [0x91,0xea,0x50,0x00]
 221
 222     IT EQ
 223     EOREQ    r3, r2, r1          // Must be wide - 3 distinct registers
 224     IT EQ
 225     EOREQ    r0, r0, r1          // Should choose narrow
 226     IT EQ
 227     EOREQ    r2, r1, r2          // Should choose narrow - commutative
 228     IT EQ
 229     EOREQ.W  r3, r3, r1          // Explicitly wide
 230     IT EQ
 231     EOREQ.W  r0, r1, r0
 232     IT EQ
 233     EORSEQ   r1, r1, r1          // Must use wide encoding as flag-setting
 234     IT EQ
 235     EOREQ    r7, r7, r1          // Should use narrow
 236     IT EQ
 237     EOREQ    r7, r1, r7          // Commutative
 238     IT EQ
 239     EOREQ    r8, r1, r8          // high registers so must use wide encoding
 240     IT EQ
 241     EOREQ    r8, r8, r1
 242     IT EQ
 243     EOREQ    r0, r8, r0
 244     IT EQ
 245     EOREQ    r3, r3, r8
 246     IT EQ
 247     EOREQ    r4, r4, r1, lsl #1  // Must use wide - shifted register
 248     IT EQ
 249     EOREQ    r0, r1, r0, lsr #1
 250 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 251 // CHECK: eoreq.w  r3, r2, r1             @ encoding: [0x82,0xea,0x01,0x03]
 252 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 253 // CHECK: eoreq    r0, r1                 @ encoding: [0x48,0x40]
 254 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 255 // CHECK: eoreq    r2, r1                 @ encoding: [0x4a,0x40]
 256 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 257 // CHECK: eoreq.w  r3, r3, r1             @ encoding: [0x83,0xea,0x01,0x03]
 258 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 259 // CHECK: eoreq.w  r0, r1, r0             @ encoding: [0x81,0xea,0x00,0x00]
 260 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 261 // CHECK: eorseq.w r1, r1, r1             @ encoding: [0x91,0xea,0x01,0x01]
 262 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 263 // CHECK: eoreq    r7, r1                 @ encoding: [0x4f,0x40]
 264 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 265 // CHECK: eoreq    r7, r1                 @ encoding: [0x4f,0x40]
 266 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 267 // CHECK: eoreq.w  r8, r1, r8             @ encoding: [0x81,0xea,0x08,0x08]
 268 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 269 // CHECK: eoreq.w  r8, r8, r1             @ encoding: [0x88,0xea,0x01,0x08]
 270 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 271 // CHECK: eoreq.w  r0, r8, r0             @ encoding: [0x88,0xea,0x00,0x00]
 272 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 273 // CHECK: eoreq.w  r3, r3, r8             @ encoding: [0x83,0xea,0x08,0x03]
 274 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 275 // CHECK: eoreq.w  r4, r4, r1, lsl #1     @ encoding: [0x84,0xea,0x41,0x04]
 276 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 277 // CHECK: eoreq.w  r0, r1, r0, lsr #1     @ encoding: [0x81,0xea,0x50,0x00]
 278
 279 // LSL
 280     LSLS     r0, r2, r1          // Must be wide - 3 distinct registers
 281     LSLS     r2, r2, r1          // Should choose narrow
 282     LSLS     r2, r1, r2          // Should choose wide - not commutative
 283     LSLS.W   r0, r0, r1          // Explicitly wide
 284     LSLS.W   r4, r1, r4
 285     LSL      r4, r1, r4          // Must use wide encoding as not flag-setting
 286     LSLS     r7, r7, r1          // Should use narrow
 287     LSLS     r8, r1, r8          // high registers so must use wide encoding
 288     LSLS     r8, r8, r1
 289     LSLS     r3, r8, r3
 290     LSLS     r5, r5, r8
 291 // CHECK: lsls.w  r0, r2, r1              @ encoding: [0x12,0xfa,0x01,0xf0]
 292 // CHECK: lsls    r2, r1                  @ encoding: [0x8a,0x40]
 293 // CHECK: lsls.w  r2, r1, r2              @ encoding: [0x11,0xfa,0x02,0xf2]
 294 // CHECK: lsls.w  r0, r0, r1              @ encoding: [0x10,0xfa,0x01,0xf0]
 295 // CHECK: lsls.w  r4, r1, r4              @ encoding: [0x11,0xfa,0x04,0xf4]
 296 // CHECK: lsl.w   r4, r1, r4              @ encoding: [0x01,0xfa,0x04,0xf4]
 297 // CHECK: lsls    r7, r1                  @ encoding: [0x8f,0x40]
 298 // CHECK: lsls.w  r8, r1, r8              @ encoding: [0x11,0xfa,0x08,0xf8]
 299 // CHECK: lsls.w  r8, r8, r1              @ encoding: [0x18,0xfa,0x01,0xf8]
 300 // CHECK: lsls.w  r3, r8, r3              @ encoding: [0x18,0xfa,0x03,0xf3]
 301 // CHECK: lsls.w  r5, r5, r8              @ encoding: [0x15,0xfa,0x08,0xf5]
 302
 303     IT EQ
 304     LSLEQ    r0, r2, r1          // Must be wide - 3 distinct registers
 305     IT EQ
 306     LSLEQ    r2, r2, r1          // Should choose narrow
 307     IT EQ
 308     LSLEQ    r2, r1, r2          // Should choose wide - not commutative
 309     IT EQ
 310     LSLEQ.W  r0, r0, r1          // Explicitly wide
 311     IT EQ
 312     LSLEQ.W  r3, r1, r3
 313     IT EQ
 314     LSLSEQ   r4, r1, r4          // Must use wide encoding as flag-setting
 315     IT EQ
 316     LSLEQ    r7, r7, r1          // Should use narrow
 317     IT EQ
 318     LSLEQ    r8, r1, r8          // high registers so must use wide encoding
 319     IT EQ
 320     LSLEQ    r8, r8, r1
 321     IT EQ
 322     LSLEQ    r0, r8, r0
 323     IT EQ
 324     LSLEQ    r3, r3, r8
 325 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 326 // CHECK: lsleq.w  r0, r2, r1             @ encoding: [0x02,0xfa,0x01,0xf0]
 327 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 328 // CHECK: lsleq    r2, r1                 @ encoding: [0x8a,0x40]
 329 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 330 // CHECK: lsleq.w  r2, r1, r2             @ encoding: [0x01,0xfa,0x02,0xf2]
 331 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 332 // CHECK: lsleq.w  r0, r0, r1             @ encoding: [0x00,0xfa,0x01,0xf0]
 333 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 334 // CHECK: lsleq.w  r3, r1, r3             @ encoding: [0x01,0xfa,0x03,0xf3]
 335 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 336 // CHECK: lslseq.w r4, r1, r4             @ encoding: [0x11,0xfa,0x04,0xf4]
 337 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 338 // CHECK: lsleq    r7, r1                 @ encoding: [0x8f,0x40]
 339 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 340 // CHECK: lsleq.w  r8, r1, r8             @ encoding: [0x01,0xfa,0x08,0xf8]
 341 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 342 // CHECK: lsleq.w  r8, r8, r1             @ encoding: [0x08,0xfa,0x01,0xf8]
 343 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 344 // CHECK: lsleq.w  r0, r8, r0             @ encoding: [0x08,0xfa,0x00,0xf0]
 345 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 346 // CHECK: lsleq.w  r3, r3, r8             @ encoding: [0x03,0xfa,0x08,0xf3]
 347
 348 // LSR
 349     LSRS     r6, r2, r1          // Must be wide - 3 distinct registers
 350     LSRS     r2, r2, r1          // Should choose narrow
 351     LSRS     r2, r1, r2          // Should choose wide - not commutative
 352     LSRS.W   r2, r2, r1          // Explicitly wide
 353     LSRS.W   r3, r1, r3
 354     LSR      r4, r1, r4          // Must use wide encoding as not flag-setting
 355     LSRS     r7, r7, r1          // Should use narrow
 356     LSRS     r8, r1, r8          // high registers so must use wide encoding
 357     LSRS     r8, r8, r1
 358     LSRS     r2, r8, r2
 359     LSRS     r5, r5, r8
 360 // CHECK: lsrs.w  r6, r2, r1              @ encoding: [0x32,0xfa,0x01,0xf6]
 361 // CHECK: lsrs    r2, r1                  @ encoding: [0xca,0x40]
 362 // CHECK: lsrs.w  r2, r1, r2              @ encoding: [0x31,0xfa,0x02,0xf2]
 363 // CHECK: lsrs.w  r2, r2, r1              @ encoding: [0x32,0xfa,0x01,0xf2]
 364 // CHECK: lsrs.w  r3, r1, r3              @ encoding: [0x31,0xfa,0x03,0xf3]
 365 // CHECK: lsr.w   r4, r1, r4              @ encoding: [0x21,0xfa,0x04,0xf4]
 366 // CHECK: lsrs    r7, r1                  @ encoding: [0xcf,0x40]
 367 // CHECK: lsrs.w  r8, r1, r8              @ encoding: [0x31,0xfa,0x08,0xf8]
 368 // CHECK: lsrs.w  r8, r8, r1              @ encoding: [0x38,0xfa,0x01,0xf8]
 369 // CHECK: lsrs.w  r2, r8, r2              @ encoding: [0x38,0xfa,0x02,0xf2]
 370 // CHECK: lsrs.w  r5, r5, r8              @ encoding: [0x35,0xfa,0x08,0xf5]
 371
 372     IT EQ
 373     LSREQ    r6, r2, r1          // Must be wide - 3 distinct registers
 374     IT EQ
 375     LSREQ    r7, r7, r1          // Should choose narrow
 376     IT EQ
 377     LSREQ    r7, r1, r7          // Should choose wide - not commutative
 378     IT EQ
 379     LSREQ.W  r7, r7, r1          // Explicitly wide
 380     IT EQ
 381     LSREQ.W  r2, r1, r2
 382     IT EQ
 383     LSRSEQ   r0, r1, r0          // Must use wide encoding as flag-setting
 384     IT EQ
 385     LSREQ    r7, r7, r1          // Should use narrow
 386     IT EQ
 387     LSREQ    r8, r1, r8          // high registers so must use wide encoding
 388     IT EQ
 389     LSREQ    r8, r8, r1
 390     IT EQ
 391     LSREQ    r1, r8, r1
 392     IT EQ
 393     LSREQ    r4, r4, r8
 394 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 395 // CHECK: lsreq.w  r6, r2, r1             @ encoding: [0x22,0xfa,0x01,0xf6]
 396 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 397 // CHECK: lsreq    r7, r1                 @ encoding: [0xcf,0x40]
 398 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 399 // CHECK: lsreq.w  r7, r1, r7             @ encoding: [0x21,0xfa,0x07,0xf7]
 400 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 401 // CHECK: lsreq.w  r7, r7, r1             @ encoding: [0x27,0xfa,0x01,0xf7]
 402 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 403 // CHECK: lsreq.w  r2, r1, r2             @ encoding: [0x21,0xfa,0x02,0xf2]
 404 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 405 // CHECK: lsrseq.w r0, r1, r0             @ encoding: [0x31,0xfa,0x00,0xf0]
 406 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 407 // CHECK: lsreq    r7, r1                 @ encoding: [0xcf,0x40]
 408 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 409 // CHECK: lsreq.w  r8, r1, r8             @ encoding: [0x21,0xfa,0x08,0xf8]
 410 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 411 // CHECK: lsreq.w  r8, r8, r1             @ encoding: [0x28,0xfa,0x01,0xf8]
 412 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 413 // CHECK: lsreq.w  r1, r8, r1             @ encoding: [0x28,0xfa,0x01,0xf1]
 414 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 415 // CHECK: lsreq.w  r4, r4, r8             @ encoding: [0x24,0xfa,0x08,0xf4]
 416
 417 // ASR
 418     ASRS     r7, r6, r5          // Must be wide - 3 distinct registers
 419     ASRS     r0, r0, r1          // Should choose narrow
 420     ASRS     r0, r1, r0          // Should choose wide - not commutative
 421     ASRS.W   r3, r3, r1          // Explicitly wide
 422     ASRS.W   r1, r1, r1
 423     ASR      r0, r1, r0          // Must use wide encoding as not flag-setting
 424     ASRS     r7, r7, r1          // Should use narrow
 425     ASRS     r8, r1, r8          // high registers so must use wide encoding
 426     ASRS     r8, r8, r1
 427     ASRS     r5, r8, r5
 428     ASRS     r5, r5, r8
 429 // CHECK: asrs.w  r7, r6, r5              @ encoding: [0x56,0xfa,0x05,0xf7]
 430 // CHECK: asrs    r0, r1                  @ encoding: [0x08,0x41]
 431 // CHECK: asrs.w  r0, r1, r0              @ encoding: [0x51,0xfa,0x00,0xf0]
 432 // CHECK: asrs.w  r3, r3, r1              @ encoding: [0x53,0xfa,0x01,0xf3]
 433 // CHECK: asrs.w  r1, r1, r1              @ encoding: [0x51,0xfa,0x01,0xf1]
 434 // CHECK: asr.w   r0, r1, r0              @ encoding: [0x41,0xfa,0x00,0xf0]
 435 // CHECK: asrs    r7, r1                  @ encoding: [0x0f,0x41]
 436 // CHECK: asrs.w  r8, r1, r8              @ encoding: [0x51,0xfa,0x08,0xf8]
 437 // CHECK: asrs.w  r8, r8, r1              @ encoding: [0x58,0xfa,0x01,0xf8]
 438 // CHECK: asrs.w  r5, r8, r5              @ encoding: [0x58,0xfa,0x05,0xf5]
 439 // CHECK: asrs.w  r5, r5, r8              @ encoding: [0x55,0xfa,0x08,0xf5]
 440
 441     IT EQ
 442     ASREQ    r0, r2, r1          // Must be wide - 3 distinct registers
 443     IT EQ
 444     ASREQ    r2, r2, r1          // Should choose narrow
 445     IT EQ
 446     ASREQ    r1, r2, r1          // Should choose wide - not commutative
 447     IT EQ
 448     ASREQ.W  r4, r4, r1          // Explicitly wide
 449     IT EQ
 450     ASREQ.W  r6, r1, r6
 451     IT EQ
 452     ASRSEQ   r3, r1, r3          // Must use wide encoding as flag-setting
 453     IT EQ
 454     ASREQ    r7, r7, r1          // Should use narrow
 455     IT EQ
 456     ASREQ    r8, r1, r8          // high registers so must use wide encoding
 457     IT EQ
 458     ASREQ    r8, r8, r1
 459     IT EQ
 460     ASREQ    r1, r8, r1
 461     IT EQ
 462     ASREQ    r3, r3, r8
 463 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 464 // CHECK: asreq.w  r0, r2, r1             @ encoding: [0x42,0xfa,0x01,0xf0]
 465 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 466 // CHECK: asreq    r2, r1                 @ encoding: [0x0a,0x41]
 467 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 468 // CHECK: asreq.w  r1, r2, r1             @ encoding: [0x42,0xfa,0x01,0xf1]
 469 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 470 // CHECK: asreq.w  r4, r4, r1             @ encoding: [0x44,0xfa,0x01,0xf4]
 471 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 472 // CHECK: asreq.w  r6, r1, r6             @ encoding: [0x41,0xfa,0x06,0xf6]
 473 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 474 // CHECK: asrseq.w r3, r1, r3             @ encoding: [0x51,0xfa,0x03,0xf3]
 475 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 476 // CHECK: asreq    r7, r1                 @ encoding: [0x0f,0x41]
 477 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 478 // CHECK: asreq.w  r8, r1, r8             @ encoding: [0x41,0xfa,0x08,0xf8]
 479 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 480 // CHECK: asreq.w  r8, r8, r1             @ encoding: [0x48,0xfa,0x01,0xf8]
 481 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 482 // CHECK: asreq.w  r1, r8, r1             @ encoding: [0x48,0xfa,0x01,0xf1]
 483 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 484 // CHECK: asreq.w  r3, r3, r8             @ encoding: [0x43,0xfa,0x08,0xf3]
 485
 486 // ADC (commutative)
 487     ADCS     r5, r2, r1          // Must be wide - 3 distinct registers
 488     ADCS     r5, r5, r1          // Should choose narrow
 489     ADCS     r3, r1, r3          // Should choose narrow - commutative
 490     ADCS.W   r2, r2, r1          // Explicitly wide
 491     ADCS.W   r3, r1, r3
 492     ADC      r0, r1, r0          // Must use wide encoding as not flag-setting
 493     ADCS     r7, r7, r1          // Should use narrow
 494     ADCS     r7, r1, r7          // Commutative
 495     ADCS     r8, r1, r8          // high registers so must use wide encoding
 496     ADCS     r8, r8, r1
 497     ADCS     r5, r8, r5
 498     ADCS     r2, r2, r8
 499     ADCS     r3, r3, r1, lsl #1  // Must use wide - shifted register
 500     ADCS     r4, r1, r4, lsr #1
 501 // CHECK: adcs.w  r5, r2, r1              @ encoding: [0x52,0xeb,0x01,0x05]
 502 // CHECK: adcs    r5, r1                  @ encoding: [0x4d,0x41]
 503 // CHECK: adcs    r3, r1                  @ encoding: [0x4b,0x41]
 504 // CHECK: adcs.w  r2, r2, r1              @ encoding: [0x52,0xeb,0x01,0x02]
 505 // CHECK: adcs.w  r3, r1, r3              @ encoding: [0x51,0xeb,0x03,0x03]
 506 // CHECK: adc.w   r0, r1, r0              @ encoding: [0x41,0xeb,0x00,0x00]
 507 // CHECK: adcs    r7, r1                  @ encoding: [0x4f,0x41]
 508 // CHECK: adcs    r7, r1                  @ encoding: [0x4f,0x41]
 509 // CHECK: adcs.w  r8, r1, r8              @ encoding: [0x51,0xeb,0x08,0x08]
 510 // CHECK: adcs.w  r8, r8, r1              @ encoding: [0x58,0xeb,0x01,0x08]
 511 // CHECK: adcs.w  r5, r8, r5              @ encoding: [0x58,0xeb,0x05,0x05]
 512 // CHECK: adcs.w  r2, r2, r8              @ encoding: [0x52,0xeb,0x08,0x02]
 513 // CHECK: adcs.w  r3, r3, r1, lsl #1      @ encoding: [0x53,0xeb,0x41,0x03]
 514 // CHECK: adcs.w  r4, r1, r4, lsr #1      @ encoding: [0x51,0xeb,0x54,0x04]
 515
 516     IT EQ
 517     ADCEQ    r1, r2, r3          // Must be wide - 3 distinct registers
 518     IT EQ
 519     ADCEQ    r1, r1, r1          // Should choose narrow
 520     IT EQ
 521     ADCEQ    r3, r1, r3          // Should choose narrow - commutative
 522     IT EQ
 523     ADCEQ.W  r3, r3, r1          // Explicitly wide
 524     IT EQ
 525     ADCEQ.W  r0, r1, r0
 526     IT EQ
 527     ADCSEQ   r3, r1, r3          // Must use wide encoding as flag-setting
 528     IT EQ
 529     ADCEQ    r7, r7, r1          // Should use narrow
 530     IT EQ
 531     ADCEQ    r7, r1, r7          // Commutative
 532     IT EQ
 533     ADCEQ    r8, r1, r8          // high registers so must use wide encoding
 534     IT EQ
 535     ADCEQ    r8, r8, r1
 536     IT EQ
 537     ADCEQ    r3, r8, r3
 538     IT EQ
 539     ADCEQ    r1, r1, r8
 540     IT EQ
 541     ADCEQ    r2, r2, r1, lsl #1  // Must use wide - shifted register
 542     IT EQ
 543     ADCEQ    r1, r1, r1, lsr #1
 544 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 545 // CHECK: adceq.w  r1, r2, r3             @ encoding: [0x42,0xeb,0x03,0x01]
 546 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 547 // CHECK: adceq    r1, r1                 @ encoding: [0x49,0x41]
 548 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 549 // CHECK: adceq    r3, r1                 @ encoding: [0x4b,0x41]
 550 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 551 // CHECK: adceq.w  r3, r3, r1             @ encoding: [0x43,0xeb,0x01,0x03]
 552 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 553 // CHECK: adceq.w  r0, r1, r0             @ encoding: [0x41,0xeb,0x00,0x00]
 554 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 555 // CHECK: adcseq.w r3, r1, r3             @ encoding: [0x51,0xeb,0x03,0x03]
 556 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 557 // CHECK: adceq    r7, r1                 @ encoding: [0x4f,0x41]
 558 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 559 // CHECK: adceq    r7, r1                 @ encoding: [0x4f,0x41]
 560 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 561 // CHECK: adceq.w  r8, r1, r8             @ encoding: [0x41,0xeb,0x08,0x08]
 562 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 563 // CHECK: adceq.w  r8, r8, r1             @ encoding: [0x48,0xeb,0x01,0x08]
 564 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 565 // CHECK: adceq.w  r3, r8, r3             @ encoding: [0x48,0xeb,0x03,0x03]
 566 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 567 // CHECK: adceq.w  r1, r1, r8             @ encoding: [0x41,0xeb,0x08,0x01]
 568 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 569 // CHECK: adceq.w  r2, r2, r1, lsl #1     @ encoding: [0x42,0xeb,0x41,0x02]
 570 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 571 // CHECK: adceq.w  r1, r1, r1, lsr #1     @ encoding: [0x41,0xeb,0x51,0x01]
 572
 573 // SBC
 574     SBCS     r3, r2, r1          // Must be wide - 3 distinct registers
 575     SBCS     r4, r4, r1          // Should choose narrow
 576     SBCS     r1, r4, r1          // Should choose wide - not commutative
 577     SBCS.W   r4, r4, r1          // Explicitly wide
 578     SBCS.W   r2, r1, r2
 579     SBC      r0, r1, r0          // Must use wide encoding as not flag-setting
 580     SBCS     r7, r7, r1          // Should use narrow
 581     SBCS     r8, r1, r8          // high registers so must use wide encoding
 582     SBCS     r8, r8, r1
 583     SBCS     r4, r8, r4
 584     SBCS     r3, r3, r8
 585     SBCS     r2, r2, r1, lsl #1  // Must use wide - shifted register
 586     SBCS     r5, r1, r5, lsr #1
 587 // CHECK: sbcs.w  r3, r2, r1              @ encoding: [0x72,0xeb,0x01,0x03]
 588 // CHECK: sbcs    r4, r1                  @ encoding: [0x8c,0x41]
 589 // CHECK: sbcs.w  r1, r4, r1              @ encoding: [0x74,0xeb,0x01,0x01]
 590 // CHECK: sbcs.w  r4, r4, r1              @ encoding: [0x74,0xeb,0x01,0x04]
 591 // CHECK: sbcs.w  r2, r1, r2              @ encoding: [0x71,0xeb,0x02,0x02]
 592 // CHECK: sbc.w   r0, r1, r0              @ encoding: [0x61,0xeb,0x00,0x00]
 593 // CHECK: sbcs    r7, r1                  @ encoding: [0x8f,0x41]
 594 // CHECK: sbcs.w  r8, r1, r8              @ encoding: [0x71,0xeb,0x08,0x08]
 595 // CHECK: sbcs.w  r8, r8, r1              @ encoding: [0x78,0xeb,0x01,0x08]
 596 // CHECK: sbcs.w  r4, r8, r4              @ encoding: [0x78,0xeb,0x04,0x04]
 597 // CHECK: sbcs.w  r3, r3, r8              @ encoding: [0x73,0xeb,0x08,0x03]
 598 // CHECK: sbcs.w  r2, r2, r1, lsl #1      @ encoding: [0x72,0xeb,0x41,0x02]
 599 // CHECK: sbcs.w  r5, r1, r5, lsr #1      @ encoding: [0x71,0xeb,0x55,0x05]
 600
 601     IT EQ
 602     SBCEQ    r5, r2, r1          // Must be wide - 3 distinct registers
 603     IT EQ
 604     SBCEQ    r5, r5, r1          // Should choose narrow
 605     IT EQ
 606     SBCEQ    r1, r5, r1          // Should choose narrow
 607     IT EQ
 608     SBCEQ.W  r5, r5, r1          // Explicitly wide
 609     IT EQ
 610     SBCEQ.W  r0, r1, r0
 611     IT EQ
 612     SBCSEQ   r2, r1, r2          // Must use wide encoding as flag-setting
 613     IT EQ
 614     SBCEQ    r7, r7, r1          // Should use narrow
 615     IT EQ
 616     SBCEQ    r8, r1, r8          // high registers so must use wide encoding
 617     IT EQ
 618     SBCEQ    r8, r8, r1
 619     IT EQ
 620     SBCEQ    r7, r8, r7
 621     IT EQ
 622     SBCEQ    r7, r7, r8
 623     IT EQ
 624     SBCEQ    r2, r2, r1, lsl #1  // Must use wide - shifted register
 625     IT EQ
 626     SBCEQ    r5, r1, r5, lsr #1
 627 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 628 // CHECK: sbceq.w  r5, r2, r1             @ encoding: [0x62,0xeb,0x01,0x05]
 629 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 630 // CHECK: sbceq    r5, r1                 @ encoding: [0x8d,0x41]
 631 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 632 // CHECK: sbceq.w  r1, r5, r1             @ encoding: [0x65,0xeb,0x01,0x01]
 633 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 634 // CHECK: sbceq.w  r5, r5, r1             @ encoding: [0x65,0xeb,0x01,0x05]
 635 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 636 // CHECK: sbceq.w  r0, r1, r0             @ encoding: [0x61,0xeb,0x00,0x00]
 637 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 638 // CHECK: sbcseq.w r2, r1, r2             @ encoding: [0x71,0xeb,0x02,0x02]
 639 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 640 // CHECK: sbceq    r7, r1                 @ encoding: [0x8f,0x41]
 641 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 642 // CHECK: sbceq.w  r8, r1, r8             @ encoding: [0x61,0xeb,0x08,0x08]
 643 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 644 // CHECK: sbceq.w  r8, r8, r1             @ encoding: [0x68,0xeb,0x01,0x08]
 645 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 646 // CHECK: sbceq.w  r7, r8, r7             @ encoding: [0x68,0xeb,0x07,0x07]
 647 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 648 // CHECK: sbceq.w  r7, r7, r8             @ encoding: [0x67,0xeb,0x08,0x07]
 649 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 650 // CHECK: sbceq.w  r2, r2, r1, lsl #1     @ encoding: [0x62,0xeb,0x41,0x02]
 651 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 652 // CHECK: sbceq.w  r5, r1, r5, lsr #1     @ encoding: [0x61,0xeb,0x55,0x05]
 653
 654 // ROR
 655     RORS     r3, r2, r1          // Must be wide - 3 distinct registers
 656     RORS     r0, r0, r1          // Should choose narrow
 657     RORS     r1, r0, r1          // Should choose wide - not commutative
 658     RORS.W   r2, r2, r1          // Explicitly wide
 659     RORS.W   r2, r1, r2
 660     ROR      r5, r1, r5          // Must use wide encoding as not flag-setting
 661     RORS     r7, r7, r1          // Should use narrow
 662     RORS     r8, r1, r8          // high registers so must use wide encoding
 663     RORS     r8, r8, r1
 664     RORS     r6, r8, r6
 665     RORS     r6, r6, r8
 666 // CHECK: rors.w  r3, r2, r1              @ encoding: [0x72,0xfa,0x01,0xf3]
 667 // CHECK: rors    r0, r1                  @ encoding: [0xc8,0x41]
 668 // CHECK: rors.w  r1, r0, r1              @ encoding: [0x70,0xfa,0x01,0xf1]
 669 // CHECK: rors.w  r2, r2, r1              @ encoding: [0x72,0xfa,0x01,0xf2]
 670 // CHECK: rors.w  r2, r1, r2              @ encoding: [0x71,0xfa,0x02,0xf2]
 671 // CHECK: ror.w   r5, r1, r5              @ encoding: [0x61,0xfa,0x05,0xf5]
 672 // CHECK: rors    r7, r1                  @ encoding: [0xcf,0x41]
 673 // CHECK: rors.w  r8, r1, r8              @ encoding: [0x71,0xfa,0x08,0xf8]
 674 // CHECK: rors.w  r8, r8, r1              @ encoding: [0x78,0xfa,0x01,0xf8]
 675 // CHECK: rors.w  r6, r8, r6              @ encoding: [0x78,0xfa,0x06,0xf6]
 676 // CHECK: rors.w  r6, r6, r8              @ encoding: [0x76,0xfa,0x08,0xf6]
 677
 678     IT EQ
 679     ROREQ    r4, r2, r1          // Must be wide - 3 distinct registers
 680     IT EQ
 681     ROREQ    r4, r4, r1          // Should choose narrow
 682     IT EQ
 683     ROREQ    r1, r4, r1          // Should choose wide - not commutative
 684     IT EQ
 685     ROREQ.W  r4, r4, r1          // Explicitly wide
 686     IT EQ
 687     ROREQ.W  r0, r1, r0
 688     IT EQ
 689     RORSEQ   r0, r1, r0          // Must use wide encoding as flag-setting
 690     IT EQ
 691     ROREQ    r7, r7, r1          // Should use narrow
 692     IT EQ
 693     ROREQ    r8, r1, r8          // high registers so must use wide encoding
 694     IT EQ
 695     ROREQ    r8, r8, r1
 696     IT EQ
 697     ROREQ    r3, r8, r3
 698     IT EQ
 699     ROREQ    r1, r1, r8
 700 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 701 // CHECK: roreq.w  r4, r2, r1             @ encoding: [0x62,0xfa,0x01,0xf4]
 702 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 703 // CHECK: roreq    r4, r1                 @ encoding: [0xcc,0x41]
 704 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 705 // CHECK: roreq.w  r1, r4, r1             @ encoding: [0x64,0xfa,0x01,0xf1]
 706 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 707 // CHECK: roreq.w  r4, r4, r1             @ encoding: [0x64,0xfa,0x01,0xf4]
 708 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 709 // CHECK: roreq.w  r0, r1, r0             @ encoding: [0x61,0xfa,0x00,0xf0]
 710 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 711 // CHECK: rorseq.w r0, r1, r0             @ encoding: [0x71,0xfa,0x00,0xf0]
 712 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 713 // CHECK: roreq    r7, r1                 @ encoding: [0xcf,0x41]
 714 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 715 // CHECK: roreq.w  r8, r1, r8             @ encoding: [0x61,0xfa,0x08,0xf8]
 716 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 717 // CHECK: roreq.w  r8, r8, r1             @ encoding: [0x68,0xfa,0x01,0xf8]
 718 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 719 // CHECK: roreq.w  r3, r8, r3             @ encoding: [0x68,0xfa,0x03,0xf3]
 720 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 721 // CHECK: roreq.w  r1, r1, r8             @ encoding: [0x61,0xfa,0x08,0xf1]
 722
 723 // TST - only two register version available
 724 // RSB - only two register version available
 725 // CMP - only two register version available
 726 // CMN - only two register version available
 727
 728 // ORR (commutative)
 729     ORRS     r7, r2, r1          // Must be wide - 3 distinct registers
 730     ORRS     r2, r2, r1          // Should choose narrow
 731     ORRS     r3, r1, r3          // Should choose narrow - commutative
 732     ORRS.W   r4, r4, r1          // Explicitly wide
 733     ORRS.W   r5, r1, r5
 734     ORR      r2, r1, r2          // Must use wide encoding as not flag-setting
 735     ORRS     r7, r7, r1          // Should use narrow
 736     ORRS     r7, r1, r7          // Commutative
 737     ORRS     r8, r1, r8          // high registers so must use wide encoding
 738     ORRS     r8, r8, r1
 739     ORRS     r1, r8, r1
 740     ORRS     r0, r0, r8
 741     ORRS     r1, r1, r1, lsl #1  // Must use wide - shifted register
 742     ORRS     r0, r1, r0, lsr #1
 743 // CHECK: orrs.w  r7, r2, r1              @ encoding: [0x52,0xea,0x01,0x07]
 744 // CHECK: orrs    r2, r1                  @ encoding: [0x0a,0x43]
 745 // CHECK: orrs    r3, r1                  @ encoding: [0x0b,0x43]
 746 // CHECK: orrs.w  r4, r4, r1              @ encoding: [0x54,0xea,0x01,0x04]
 747 // CHECK: orrs.w  r5, r1, r5              @ encoding: [0x51,0xea,0x05,0x05]
 748 // CHECK: orr.w   r2, r1, r2              @ encoding: [0x41,0xea,0x02,0x02]
 749 // CHECK: orrs    r7, r1                  @ encoding: [0x0f,0x43]
 750 // CHECK: orrs    r7, r1                  @ encoding: [0x0f,0x43]
 751 // CHECK: orrs.w  r8, r1, r8              @ encoding: [0x51,0xea,0x08,0x08]
 752 // CHECK: orrs.w  r8, r8, r1              @ encoding: [0x58,0xea,0x01,0x08]
 753 // CHECK: orrs.w  r1, r8, r1              @ encoding: [0x58,0xea,0x01,0x01]
 754 // CHECK: orrs.w  r0, r0, r8              @ encoding: [0x50,0xea,0x08,0x00]
 755 // CHECK: orrs.w  r1, r1, r1, lsl #1      @ encoding: [0x51,0xea,0x41,0x01]
 756 // CHECK: orrs.w  r0, r1, r0, lsr #1      @ encoding: [0x51,0xea,0x50,0x00]
 757
 758     IT EQ
 759     ORREQ    r0, r2, r1          // Must be wide - 3 distinct registers
 760     IT EQ
 761     ORREQ    r5, r5, r1          // Should choose narrow
 762     IT EQ
 763     ORREQ    r5, r1, r5          // Should choose narrow - commutative
 764     IT EQ
 765     ORREQ.W  r2, r2, r1          // Explicitly wide
 766     IT EQ
 767     ORREQ.W  r3, r1, r3
 768     IT EQ
 769     ORRSEQ   r4, r1, r4          // Must use wide encoding as flag-setting
 770     IT EQ
 771     ORREQ    r7, r7, r1          // Should use narrow
 772     IT EQ
 773     ORREQ    r7, r1, r7          // Commutative
 774     IT EQ
 775     ORREQ    r8, r1, r8          // high registers so must use wide encoding
 776     IT EQ
 777     ORREQ    r8, r8, r1
 778     IT EQ
 779     ORREQ    r0, r8, r0
 780     IT EQ
 781     ORREQ    r0, r0, r8
 782     IT EQ
 783     ORREQ    r2, r2, r1, lsl #1  // Must use wide - shifted register
 784     IT EQ
 785     ORREQ    r2, r1, r2, lsr #1
 786 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 787 // CHECK: orreq.w  r0, r2, r1             @ encoding: [0x42,0xea,0x01,0x00]
 788 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 789 // CHECK: orreq    r5, r1                 @ encoding: [0x0d,0x43]
 790 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 791 // CHECK: orreq    r5, r1                 @ encoding: [0x0d,0x43]
 792 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 793 // CHECK: orreq.w  r2, r2, r1             @ encoding: [0x42,0xea,0x01,0x02]
 794 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 795 // CHECK: orreq.w  r3, r1, r3             @ encoding: [0x41,0xea,0x03,0x03]
 796 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 797 // CHECK: orrseq.w r4, r1, r4             @ encoding: [0x51,0xea,0x04,0x04]
 798 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 799 // CHECK: orreq    r7, r1                 @ encoding: [0x0f,0x43]
 800 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 801 // CHECK: orreq    r7, r1                 @ encoding: [0x0f,0x43]
 802 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 803 // CHECK: orreq.w  r8, r1, r8             @ encoding: [0x41,0xea,0x08,0x08]
 804 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 805 // CHECK: orreq.w  r8, r8, r1             @ encoding: [0x48,0xea,0x01,0x08]
 806 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 807 // CHECK: orreq.w  r0, r8, r0             @ encoding: [0x48,0xea,0x00,0x00]
 808 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 809 // CHECK: orreq.w  r0, r0, r8             @ encoding: [0x40,0xea,0x08,0x00]
 810 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 811 // CHECK: orreq.w  r2, r2, r1, lsl #1     @ encoding: [0x42,0xea,0x41,0x02]
 812 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 813 // CHECK: orreq.w  r2, r1, r2, lsr #1     @ encoding: [0x41,0xea,0x52,0x02]
 814
 815 // MUL - not affected by this change
 816
 817 // BIC
 818     BICS     r3, r2, r1          // Must be wide - 3 distinct registers
 819     BICS     r2, r2, r1          // Should choose narrow
 820     BICS     r1, r2, r1          // Should choose wide - not commutative
 821     BICS.W   r2, r2, r1          // Explicitly wide
 822     BICS.W   r0, r1, r0
 823     BIC      r0, r1, r0          // Must use wide encoding as not flag-setting
 824     BICS     r7, r7, r1          // Should use narrow
 825     BICS     r8, r1, r8          // high registers so must use wide encoding
 826     BICS     r8, r8, r1
 827     BICS     r7, r8, r7
 828     BICS     r5, r5, r8
 829     BICS     r3, r3, r1, lsl #1  // Must use wide - shifted register
 830     BICS     r4, r1, r4, lsr #1
 831 // CHECK: bics.w  r3, r2, r1              @ encoding: [0x32,0xea,0x01,0x03]
 832 // CHECK: bics    r2, r1                  @ encoding: [0x8a,0x43]
 833 // CHECK: bics.w  r1, r2, r1              @ encoding: [0x32,0xea,0x01,0x01]
 834 // CHECK: bics.w  r2, r2, r1              @ encoding: [0x32,0xea,0x01,0x02]
 835 // CHECK: bics.w  r0, r1, r0              @ encoding: [0x31,0xea,0x00,0x00]
 836 // CHECK: bic.w   r0, r1, r0              @ encoding: [0x21,0xea,0x00,0x00]
 837 // CHECK: bics    r7, r1                  @ encoding: [0x8f,0x43]
 838 // CHECK: bics.w  r8, r1, r8              @ encoding: [0x31,0xea,0x08,0x08]
 839 // CHECK: bics.w  r8, r8, r1              @ encoding: [0x38,0xea,0x01,0x08]
 840 // CHECK: bics.w  r7, r8, r7              @ encoding: [0x38,0xea,0x07,0x07]
 841 // CHECK: bics.w  r5, r5, r8              @ encoding: [0x35,0xea,0x08,0x05]
 842 // CHECK: bics.w  r3, r3, r1, lsl #1      @ encoding: [0x33,0xea,0x41,0x03]
 843 // CHECK: bics.w  r4, r1, r4, lsr #1      @ encoding: [0x31,0xea,0x54,0x04]
 844
 845     IT EQ
 846     BICEQ    r0, r2, r1          // Must be wide - 3 distinct registers
 847     IT EQ
 848     BICEQ    r5, r5, r1          // Should choose narrow
 849     IT EQ
 850     BICEQ    r1, r5, r1          // Should choose wide - not commutative
 851     IT EQ
 852     BICEQ.W  r4, r4, r1          // Explicitly wide
 853     IT EQ
 854     BICEQ.W  r2, r1, r2
 855     IT EQ
 856     BICSEQ   r5, r1, r5          // Must use wide encoding as flag-setting
 857     IT EQ
 858     BICEQ    r7, r7, r1          // Should use narrow
 859     IT EQ
 860     BICEQ    r8, r1, r8          // high registers so must use wide encoding
 861     IT EQ
 862     BICEQ    r8, r8, r1
 863     IT EQ
 864     BICEQ    r0, r8, r0
 865     IT EQ
 866     BICEQ    r2, r2, r8
 867     IT EQ
 868     BICEQ    r4, r4, r1, lsl #1  // Must use wide - shifted register
 869     IT EQ
 870     BICEQ    r5, r1, r5, lsr #1
 871 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 872 // CHECK: biceq.w  r0, r2, r1             @ encoding: [0x22,0xea,0x01,0x00]
 873 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 874 // CHECK: biceq    r5, r1                 @ encoding: [0x8d,0x43]
 875 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 876 // CHECK: biceq.w  r1, r5, r1             @ encoding: [0x25,0xea,0x01,0x01]
 877 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 878 // CHECK: biceq.w  r4, r4, r1             @ encoding: [0x24,0xea,0x01,0x04]
 879 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 880 // CHECK: biceq.w  r2, r1, r2             @ encoding: [0x21,0xea,0x02,0x02]
 881 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 882 // CHECK: bicseq.w r5, r1, r5             @ encoding: [0x31,0xea,0x05,0x05]
 883 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 884 // CHECK: biceq    r7, r1                 @ encoding: [0x8f,0x43]
 885 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 886 // CHECK: biceq.w  r8, r1, r8             @ encoding: [0x21,0xea,0x08,0x08]
 887 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 888 // CHECK: biceq.w  r8, r8, r1             @ encoding: [0x28,0xea,0x01,0x08]
 889 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 890 // CHECK: biceq.w  r0, r8, r0             @ encoding: [0x28,0xea,0x00,0x00]
 891 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 892 // CHECK: biceq.w  r2, r2, r8             @ encoding: [0x22,0xea,0x08,0x02]
 893 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 894 // CHECK: biceq.w  r4, r4, r1, lsl #1     @ encoding: [0x24,0xea,0x41,0x04]
 895 // CHECK: it eq                           @ encoding: [0x08,0xbf]
 896 // CHECK: biceq.w  r5, r1, r5, lsr #1     @ encoding: [0x21,0xea,0x55,0x05]
 897
 898 // CMN - only two register version available