lib/Target/ARM/AsmParser/ARMAsmParser.cpp

   1 //===- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions -------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 #include "ARMFeatures.h"
  11 #include "Utils/ARMBaseInfo.h"
  12 #include "MCTargetDesc/ARMAddressingModes.h"
  13 #include "MCTargetDesc/ARMBaseInfo.h"
  14 #include "MCTargetDesc/ARMMCExpr.h"
  15 #include "MCTargetDesc/ARMMCTargetDesc.h"
  16 #include "llvm/ADT/APFloat.h"
  17 #include "llvm/ADT/APInt.h"
  18 #include "llvm/ADT/None.h"
  19 #include "llvm/ADT/STLExtras.h"
  20 #include "llvm/ADT/SmallSet.h"
  21 #include "llvm/ADT/SmallVector.h"
  22 #include "llvm/ADT/StringMap.h"
  23 #include "llvm/ADT/StringRef.h"
  24 #include "llvm/ADT/StringSwitch.h"
  25 #include "llvm/ADT/Triple.h"
  26 #include "llvm/ADT/Twine.h"
  27 #include "llvm/MC/MCContext.h"
  28 #include "llvm/MC/MCExpr.h"
  29 #include "llvm/MC/MCInst.h"
  30 #include "llvm/MC/MCInstrDesc.h"
  31 #include "llvm/MC/MCInstrInfo.h"
  32 #include "llvm/MC/MCObjectFileInfo.h"
  33 #include "llvm/MC/MCParser/MCAsmLexer.h"
  34 #include "llvm/MC/MCParser/MCAsmParser.h"
  35 #include "llvm/MC/MCParser/MCAsmParserExtension.h"
  36 #include "llvm/MC/MCParser/MCAsmParserUtils.h"
  37 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
  38 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
  39 #include "llvm/MC/MCRegisterInfo.h"
  40 #include "llvm/MC/MCSection.h"
  41 #include "llvm/MC/MCStreamer.h"
  42 #include "llvm/MC/MCSubtargetInfo.h"
  43 #include "llvm/MC/MCSymbol.h"
  44 #include "llvm/MC/SubtargetFeature.h"
  45 #include "llvm/Support/ARMBuildAttributes.h"
  46 #include "llvm/Support/ARMEHABI.h"
  47 #include "llvm/Support/Casting.h"
  48 #include "llvm/Support/CommandLine.h"
  49 #include "llvm/Support/Compiler.h"
  50 #include "llvm/Support/ErrorHandling.h"
  51 #include "llvm/Support/MathExtras.h"
  52 #include "llvm/Support/SMLoc.h"
  53 #include "llvm/Support/TargetParser.h"
  54 #include "llvm/Support/TargetRegistry.h"
  55 #include "llvm/Support/raw_ostream.h"
  56 #include <algorithm>
  57 #include <cassert>
  58 #include <cstddef>
  59 #include <cstdint>
  60 #include <iterator>
  61 #include <limits>
  62 #include <memory>
  63 #include <string>
  64 #include <utility>
  65 #include <vector>
  66
  67 #define DEBUG_TYPE "asm-parser"
  68
  69 using namespace llvm;
  70
  71 namespace {
  72
  73 enum class ImplicitItModeTy { Always, Never, ARMOnly, ThumbOnly };
  74
  75 static cl::opt<ImplicitItModeTy> ImplicitItMode(
  76     "arm-implicit-it", cl::init(ImplicitItModeTy::ARMOnly),
  77     cl::desc("Allow conditional instructions outdside of an IT block"),
  78     cl::values(clEnumValN(ImplicitItModeTy::Always, "always",
  79                           "Accept in both ISAs, emit implicit ITs in Thumb"),
  80                clEnumValN(ImplicitItModeTy::Never, "never",
  81                           "Warn in ARM, reject in Thumb"),
  82                clEnumValN(ImplicitItModeTy::ARMOnly, "arm",
  83                           "Accept in ARM, reject in Thumb"),
  84                clEnumValN(ImplicitItModeTy::ThumbOnly, "thumb",
  85                           "Warn in ARM, emit implicit ITs in Thumb")));
  86
  87 static cl::opt<bool> AddBuildAttributes("arm-add-build-attributes",
  88                                         cl::init(false));
  89
  90 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
  91
  92 class UnwindContext {
  93   using Locs = SmallVector<SMLoc, 4>;
  94
  95   MCAsmParser &Parser;
  96   Locs FnStartLocs;
  97   Locs CantUnwindLocs;
  98   Locs PersonalityLocs;
  99   Locs PersonalityIndexLocs;
 100   Locs HandlerDataLocs;
 101   int FPReg;
 102
 103 public:
 104   UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
 105
 106   bool hasFnStart() const { return !FnStartLocs.empty(); }
 107   bool cantUnwind() const { return !CantUnwindLocs.empty(); }
 108   bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
 109
 110   bool hasPersonality() const {
 111     return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
 112   }
 113
 114   void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
 115   void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
 116   void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
 117   void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
 118   void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
 119
 120   void saveFPReg(int Reg) { FPReg = Reg; }
 121   int getFPReg() const { return FPReg; }
 122
 123   void emitFnStartLocNotes() const {
 124     for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
 125          FI != FE; ++FI)
 126       Parser.Note(*FI, ".fnstart was specified here");
 127   }
 128
 129   void emitCantUnwindLocNotes() const {
 130     for (Locs::const_iterator UI = CantUnwindLocs.begin(),
 131                               UE = CantUnwindLocs.end(); UI != UE; ++UI)
 132       Parser.Note(*UI, ".cantunwind was specified here");
 133   }
 134
 135   void emitHandlerDataLocNotes() const {
 136     for (Locs::const_iterator HI = HandlerDataLocs.begin(),
 137                               HE = HandlerDataLocs.end(); HI != HE; ++HI)
 138       Parser.Note(*HI, ".handlerdata was specified here");
 139   }
 140
 141   void emitPersonalityLocNotes() const {
 142     for (Locs::const_iterator PI = PersonalityLocs.begin(),
 143                               PE = PersonalityLocs.end(),
 144                               PII = PersonalityIndexLocs.begin(),
 145                               PIE = PersonalityIndexLocs.end();
 146          PI != PE || PII != PIE;) {
 147       if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
 148         Parser.Note(*PI++, ".personality was specified here");
 149       else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
 150         Parser.Note(*PII++, ".personalityindex was specified here");
 151       else
 152         llvm_unreachable(".personality and .personalityindex cannot be "
 153                          "at the same location");
 154     }
 155   }
 156
 157   void reset() {
 158     FnStartLocs = Locs();
 159     CantUnwindLocs = Locs();
 160     PersonalityLocs = Locs();
 161     HandlerDataLocs = Locs();
 162     PersonalityIndexLocs = Locs();
 163     FPReg = ARM::SP;
 164   }
 165 };
 166
 167 class ARMAsmParser : public MCTargetAsmParser {
 168   const MCRegisterInfo *MRI;
 169   UnwindContext UC;
 170
 171   ARMTargetStreamer &getTargetStreamer() {
 172     assert(getParser().getStreamer().getTargetStreamer() &&
 173            "do not have a target streamer");
 174     MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
 175     return static_cast<ARMTargetStreamer &>(TS);
 176   }
 177
 178   // Map of register aliases registers via the .req directive.
 179   StringMap<unsigned> RegisterReqs;
 180
 181   bool NextSymbolIsThumb;
 182
 183   bool useImplicitITThumb() const {
 184     return ImplicitItMode == ImplicitItModeTy::Always ||
 185            ImplicitItMode == ImplicitItModeTy::ThumbOnly;
 186   }
 187
 188   bool useImplicitITARM() const {
 189     return ImplicitItMode == ImplicitItModeTy::Always ||
 190            ImplicitItMode == ImplicitItModeTy::ARMOnly;
 191   }
 192
 193   struct {
 194     ARMCC::CondCodes Cond;    // Condition for IT block.
 195     unsigned Mask:4;          // Condition mask for instructions.
 196                               // Starting at first 1 (from lsb).
 197                               //   '1'  condition as indicated in IT.
 198                               //   '0'  inverse of condition (else).
 199                               // Count of instructions in IT block is
 200                               // 4 - trailingzeroes(mask)
 201                               // Note that this does not have the same encoding
 202                               // as in the IT instruction, which also depends
 203                               // on the low bit of the condition code.
 204
 205     unsigned CurPosition;     // Current position in parsing of IT
 206                               // block. In range [0,4], with 0 being the IT
 207                               // instruction itself. Initialized according to
 208                               // count of instructions in block.  ~0U if no
 209                               // active IT block.
 210
 211     bool IsExplicit;          // true  - The IT instruction was present in the
 212                               //         input, we should not modify it.
 213                               // false - The IT instruction was added
 214                               //         implicitly, we can extend it if that
 215                               //         would be legal.
 216   } ITState;
 217
 218   SmallVector<MCInst, 4> PendingConditionalInsts;
 219
 220   void flushPendingInstructions(MCStreamer &Out) override {
 221     if (!inImplicitITBlock()) {
 222       assert(PendingConditionalInsts.size() == 0);
 223       return;
 224     }
 225
 226     // Emit the IT instruction
 227     unsigned Mask = getITMaskEncoding();
 228     MCInst ITInst;
 229     ITInst.setOpcode(ARM::t2IT);
 230     ITInst.addOperand(MCOperand::createImm(ITState.Cond));
 231     ITInst.addOperand(MCOperand::createImm(Mask));
 232     Out.EmitInstruction(ITInst, getSTI());
 233
 234     // Emit the conditonal instructions
 235     assert(PendingConditionalInsts.size() <= 4);
 236     for (const MCInst &Inst : PendingConditionalInsts) {
 237       Out.EmitInstruction(Inst, getSTI());
 238     }
 239     PendingConditionalInsts.clear();
 240
 241     // Clear the IT state
 242     ITState.Mask = 0;
 243     ITState.CurPosition = ~0U;
 244   }
 245
 246   bool inITBlock() { return ITState.CurPosition != ~0U; }
 247   bool inExplicitITBlock() { return inITBlock() && ITState.IsExplicit; }
 248   bool inImplicitITBlock() { return inITBlock() && !ITState.IsExplicit; }
 249
 250   bool lastInITBlock() {
 251     return ITState.CurPosition == 4 - countTrailingZeros(ITState.Mask);
 252   }
 253
 254   void forwardITPosition() {
 255     if (!inITBlock()) return;
 256     // Move to the next instruction in the IT block, if there is one. If not,
 257     // mark the block as done, except for implicit IT blocks, which we leave
 258     // open until we find an instruction that can't be added to it.
 259     unsigned TZ = countTrailingZeros(ITState.Mask);
 260     if (++ITState.CurPosition == 5 - TZ && ITState.IsExplicit)
 261       ITState.CurPosition = ~0U; // Done with the IT block after this.
 262   }
 263
 264   // Rewind the state of the current IT block, removing the last slot from it.
 265   void rewindImplicitITPosition() {
 266     assert(inImplicitITBlock());
 267     assert(ITState.CurPosition > 1);
 268     ITState.CurPosition--;
 269     unsigned TZ = countTrailingZeros(ITState.Mask);
 270     unsigned NewMask = 0;
 271     NewMask |= ITState.Mask & (0xC << TZ);
 272     NewMask |= 0x2 << TZ;
 273     ITState.Mask = NewMask;
 274   }
 275
 276   // Rewind the state of the current IT block, removing the last slot from it.
 277   // If we were at the first slot, this closes the IT block.
 278   void discardImplicitITBlock() {
 279     assert(inImplicitITBlock());
 280     assert(ITState.CurPosition == 1);
 281     ITState.CurPosition = ~0U;
 282   }
 283
 284   // Return the low-subreg of a given Q register.
 285   unsigned getDRegFromQReg(unsigned QReg) const {
 286     return MRI->getSubReg(QReg, ARM::dsub_0);
 287   }
 288
 289   // Get the encoding of the IT mask, as it will appear in an IT instruction.
 290   unsigned getITMaskEncoding() {
 291     assert(inITBlock());
 292     unsigned Mask = ITState.Mask;
 293     unsigned TZ = countTrailingZeros(Mask);
 294     if ((ITState.Cond & 1) == 0) {
 295       assert(Mask && TZ <= 3 && "illegal IT mask value!");
 296       Mask ^= (0xE << TZ) & 0xF;
 297     }
 298     return Mask;
 299   }
 300
 301   // Get the condition code corresponding to the current IT block slot.
 302   ARMCC::CondCodes currentITCond() {
 303     unsigned MaskBit;
 304     if (ITState.CurPosition == 1)
 305       MaskBit = 1;
 306     else
 307       MaskBit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
 308
 309     return MaskBit ? ITState.Cond : ARMCC::getOppositeCondition(ITState.Cond);
 310   }
 311
 312   // Invert the condition of the current IT block slot without changing any
 313   // other slots in the same block.
 314   void invertCurrentITCondition() {
 315     if (ITState.CurPosition == 1) {
 316       ITState.Cond = ARMCC::getOppositeCondition(ITState.Cond);
 317     } else {
 318       ITState.Mask ^= 1 << (5 - ITState.CurPosition);
 319     }
 320   }
 321
 322   // Returns true if the current IT block is full (all 4 slots used).
 323   bool isITBlockFull() {
 324     return inITBlock() && (ITState.Mask & 1);
 325   }
 326
 327   // Extend the current implicit IT block to have one more slot with the given
 328   // condition code.
 329   void extendImplicitITBlock(ARMCC::CondCodes Cond) {
 330     assert(inImplicitITBlock());
 331     assert(!isITBlockFull());
 332     assert(Cond == ITState.Cond ||
 333            Cond == ARMCC::getOppositeCondition(ITState.Cond));
 334     unsigned TZ = countTrailingZeros(ITState.Mask);
 335     unsigned NewMask = 0;
 336     // Keep any existing condition bits.
 337     NewMask |= ITState.Mask & (0xE << TZ);
 338     // Insert the new condition bit.
 339     NewMask |= (Cond == ITState.Cond) << TZ;
 340     // Move the trailing 1 down one bit.
 341     NewMask |= 1 << (TZ - 1);
 342     ITState.Mask = NewMask;
 343   }
 344
 345   // Create a new implicit IT block with a dummy condition code.
 346   void startImplicitITBlock() {
 347     assert(!inITBlock());
 348     ITState.Cond = ARMCC::AL;
 349     ITState.Mask = 8;
 350     ITState.CurPosition = 1;
 351     ITState.IsExplicit = false;
 352   }
 353
 354   // Create a new explicit IT block with the given condition and mask. The mask
 355   // should be in the parsed format, with a 1 implying 't', regardless of the
 356   // low bit of the condition.
 357   void startExplicitITBlock(ARMCC::CondCodes Cond, unsigned Mask) {
 358     assert(!inITBlock());
 359     ITState.Cond = Cond;
 360     ITState.Mask = Mask;
 361     ITState.CurPosition = 0;
 362     ITState.IsExplicit = true;
 363   }
 364
 365   void Note(SMLoc L, const Twine &Msg, SMRange Range = None) {
 366     return getParser().Note(L, Msg, Range);
 367   }
 368
 369   bool Warning(SMLoc L, const Twine &Msg, SMRange Range = None) {
 370     return getParser().Warning(L, Msg, Range);
 371   }
 372
 373   bool Error(SMLoc L, const Twine &Msg, SMRange Range = None) {
 374     return getParser().Error(L, Msg, Range);
 375   }
 376
 377   bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
 378                            unsigned ListNo, bool IsARPop = false);
 379   bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
 380                            unsigned ListNo);
 381
 382   int tryParseRegister();
 383   bool tryParseRegisterWithWriteBack(OperandVector &);
 384   int tryParseShiftRegister(OperandVector &);
 385   bool parseRegisterList(OperandVector &);
 386   bool parseMemory(OperandVector &);
 387   bool parseOperand(OperandVector &, StringRef Mnemonic);
 388   bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
 389   bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
 390                               unsigned &ShiftAmount);
 391   bool parseLiteralValues(unsigned Size, SMLoc L);
 392   bool parseDirectiveThumb(SMLoc L);
 393   bool parseDirectiveARM(SMLoc L);
 394   bool parseDirectiveThumbFunc(SMLoc L);
 395   bool parseDirectiveCode(SMLoc L);
 396   bool parseDirectiveSyntax(SMLoc L);
 397   bool parseDirectiveReq(StringRef Name, SMLoc L);
 398   bool parseDirectiveUnreq(SMLoc L);
 399   bool parseDirectiveArch(SMLoc L);
 400   bool parseDirectiveEabiAttr(SMLoc L);
 401   bool parseDirectiveCPU(SMLoc L);
 402   bool parseDirectiveFPU(SMLoc L);
 403   bool parseDirectiveFnStart(SMLoc L);
 404   bool parseDirectiveFnEnd(SMLoc L);
 405   bool parseDirectiveCantUnwind(SMLoc L);
 406   bool parseDirectivePersonality(SMLoc L);
 407   bool parseDirectiveHandlerData(SMLoc L);
 408   bool parseDirectiveSetFP(SMLoc L);
 409   bool parseDirectivePad(SMLoc L);
 410   bool parseDirectiveRegSave(SMLoc L, bool IsVector);
 411   bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
 412   bool parseDirectiveLtorg(SMLoc L);
 413   bool parseDirectiveEven(SMLoc L);
 414   bool parseDirectivePersonalityIndex(SMLoc L);
 415   bool parseDirectiveUnwindRaw(SMLoc L);
 416   bool parseDirectiveTLSDescSeq(SMLoc L);
 417   bool parseDirectiveMovSP(SMLoc L);
 418   bool parseDirectiveObjectArch(SMLoc L);
 419   bool parseDirectiveArchExtension(SMLoc L);
 420   bool parseDirectiveAlign(SMLoc L);
 421   bool parseDirectiveThumbSet(SMLoc L);
 422
 423   StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
 424                           bool &CarrySetting, unsigned &ProcessorIMod,
 425                           StringRef &ITMask);
 426   void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
 427                              bool &CanAcceptCarrySet,
 428                              bool &CanAcceptPredicationCode);
 429
 430   void tryConvertingToTwoOperandForm(StringRef Mnemonic, bool CarrySetting,
 431                                      OperandVector &Operands);
 432   bool isThumb() const {
 433     // FIXME: Can tablegen auto-generate this?
 434     return getSTI().getFeatureBits()[ARM::ModeThumb];
 435   }
 436
 437   bool isThumbOne() const {
 438     return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2];
 439   }
 440
 441   bool isThumbTwo() const {
 442     return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2];
 443   }
 444
 445   bool hasThumb() const {
 446     return getSTI().getFeatureBits()[ARM::HasV4TOps];
 447   }
 448
 449   bool hasThumb2() const {
 450     return getSTI().getFeatureBits()[ARM::FeatureThumb2];
 451   }
 452
 453   bool hasV6Ops() const {
 454     return getSTI().getFeatureBits()[ARM::HasV6Ops];
 455   }
 456
 457   bool hasV6T2Ops() const {
 458     return getSTI().getFeatureBits()[ARM::HasV6T2Ops];
 459   }
 460
 461   bool hasV6MOps() const {
 462     return getSTI().getFeatureBits()[ARM::HasV6MOps];
 463   }
 464
 465   bool hasV7Ops() const {
 466     return getSTI().getFeatureBits()[ARM::HasV7Ops];
 467   }
 468
 469   bool hasV8Ops() const {
 470     return getSTI().getFeatureBits()[ARM::HasV8Ops];
 471   }
 472
 473   bool hasV8MBaseline() const {
 474     return getSTI().getFeatureBits()[ARM::HasV8MBaselineOps];
 475   }
 476
 477   bool hasV8MMainline() const {
 478     return getSTI().getFeatureBits()[ARM::HasV8MMainlineOps];
 479   }
 480
 481   bool has8MSecExt() const {
 482     return getSTI().getFeatureBits()[ARM::Feature8MSecExt];
 483   }
 484
 485   bool hasARM() const {
 486     return !getSTI().getFeatureBits()[ARM::FeatureNoARM];
 487   }
 488
 489   bool hasDSP() const {
 490     return getSTI().getFeatureBits()[ARM::FeatureDSP];
 491   }
 492
 493   bool hasD16() const {
 494     return getSTI().getFeatureBits()[ARM::FeatureD16];
 495   }
 496
 497   bool hasV8_1aOps() const {
 498     return getSTI().getFeatureBits()[ARM::HasV8_1aOps];
 499   }
 500
 501   bool hasRAS() const {
 502     return getSTI().getFeatureBits()[ARM::FeatureRAS];
 503   }
 504
 505   void SwitchMode() {
 506     MCSubtargetInfo &STI = copySTI();
 507     uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
 508     setAvailableFeatures(FB);
 509   }
 510
 511   void FixModeAfterArchChange(bool WasThumb, SMLoc Loc);
 512
 513   bool isMClass() const {
 514     return getSTI().getFeatureBits()[ARM::FeatureMClass];
 515   }
 516
 517   /// @name Auto-generated Match Functions
 518   /// {
 519
 520 #define GET_ASSEMBLER_HEADER
 521 #include "ARMGenAsmMatcher.inc"
 522
 523   /// }
 524
 525   OperandMatchResultTy parseITCondCode(OperandVector &);
 526   OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
 527   OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
 528   OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
 529   OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
 530   OperandMatchResultTy parseTraceSyncBarrierOptOperand(OperandVector &);
 531   OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
 532   OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
 533   OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
 534   OperandMatchResultTy parseBankedRegOperand(OperandVector &);
 535   OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
 536                                    int High);
 537   OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
 538     return parsePKHImm(O, "lsl", 0, 31);
 539   }
 540   OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
 541     return parsePKHImm(O, "asr", 1, 32);
 542   }
 543   OperandMatchResultTy parseSetEndImm(OperandVector &);
 544   OperandMatchResultTy parseShifterImm(OperandVector &);
 545   OperandMatchResultTy parseRotImm(OperandVector &);
 546   OperandMatchResultTy parseModImm(OperandVector &);
 547   OperandMatchResultTy parseBitfield(OperandVector &);
 548   OperandMatchResultTy parsePostIdxReg(OperandVector &);
 549   OperandMatchResultTy parseAM3Offset(OperandVector &);
 550   OperandMatchResultTy parseFPImm(OperandVector &);
 551   OperandMatchResultTy parseVectorList(OperandVector &);
 552   OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
 553                                        SMLoc &EndLoc);
 554
 555   // Asm Match Converter Methods
 556   void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
 557   void cvtThumbBranches(MCInst &Inst, const OperandVector &);
 558
 559   bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
 560   bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
 561   bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
 562   bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
 563   bool isITBlockTerminator(MCInst &Inst) const;
 564   void fixupGNULDRDAlias(StringRef Mnemonic, OperandVector &Operands);
 565   bool validateLDRDSTRD(MCInst &Inst, const OperandVector &Operands,
 566                         bool Load, bool ARMMode, bool Writeback);
 567
 568 public:
 569   enum ARMMatchResultTy {
 570     Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
 571     Match_RequiresNotITBlock,
 572     Match_RequiresV6,
 573     Match_RequiresThumb2,
 574     Match_RequiresV8,
 575     Match_RequiresFlagSetting,
 576 #define GET_OPERAND_DIAGNOSTIC_TYPES
 577 #include "ARMGenAsmMatcher.inc"
 578
 579   };
 580
 581   ARMAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
 582                const MCInstrInfo &MII, const MCTargetOptions &Options)
 583     : MCTargetAsmParser(Options, STI, MII), UC(Parser) {
 584     MCAsmParserExtension::Initialize(Parser);
 585
 586     // Cache the MCRegisterInfo.
 587     MRI = getContext().getRegisterInfo();
 588
 589     // Initialize the set of available features.
 590     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
 591
 592     // Add build attributes based on the selected target.
 593     if (AddBuildAttributes)
 594       getTargetStreamer().emitTargetAttributes(STI);
 595
 596     // Not in an ITBlock to start with.
 597     ITState.CurPosition = ~0U;
 598
 599     NextSymbolIsThumb = false;
 600   }
 601
 602   // Implementation of the MCTargetAsmParser interface:
 603   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
 604   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
 605                         SMLoc NameLoc, OperandVector &Operands) override;
 606   bool ParseDirective(AsmToken DirectiveID) override;
 607
 608   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
 609                                       unsigned Kind) override;
 610   unsigned checkTargetMatchPredicate(MCInst &Inst) override;
 611
 612   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
 613                                OperandVector &Operands, MCStreamer &Out,
 614                                uint64_t &ErrorInfo,
 615                                bool MatchingInlineAsm) override;
 616   unsigned MatchInstruction(OperandVector &Operands, MCInst &Inst,
 617                             SmallVectorImpl<NearMissInfo> &NearMisses,
 618                             bool MatchingInlineAsm, bool &EmitInITBlock,
 619                             MCStreamer &Out);
 620
 621   struct NearMissMessage {
 622     SMLoc Loc;
 623     SmallString<128> Message;
 624   };
 625
 626   const char *getCustomOperandDiag(ARMMatchResultTy MatchError);
 627
 628   void FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn,
 629                         SmallVectorImpl<NearMissMessage> &NearMissesOut,
 630                         SMLoc IDLoc, OperandVector &Operands);
 631   void ReportNearMisses(SmallVectorImpl<NearMissInfo> &NearMisses, SMLoc IDLoc,
 632                         OperandVector &Operands);
 633
 634   void onLabelParsed(MCSymbol *Symbol) override;
 635 };
 636
 637 /// ARMOperand - Instances of this class represent a parsed ARM machine
 638 /// operand.
 639 class ARMOperand : public MCParsedAsmOperand {
 640   enum KindTy {
 641     k_CondCode,
 642     k_CCOut,
 643     k_ITCondMask,
 644     k_CoprocNum,
 645     k_CoprocReg,
 646     k_CoprocOption,
 647     k_Immediate,
 648     k_MemBarrierOpt,
 649     k_InstSyncBarrierOpt,
 650     k_TraceSyncBarrierOpt,
 651     k_Memory,
 652     k_PostIndexRegister,
 653     k_MSRMask,
 654     k_BankedReg,
 655     k_ProcIFlags,
 656     k_VectorIndex,
 657     k_Register,
 658     k_RegisterList,
 659     k_DPRRegisterList,
 660     k_SPRRegisterList,
 661     k_VectorList,
 662     k_VectorListAllLanes,
 663     k_VectorListIndexed,
 664     k_ShiftedRegister,
 665     k_ShiftedImmediate,
 666     k_ShifterImmediate,
 667     k_RotateImmediate,
 668     k_ModifiedImmediate,
 669     k_ConstantPoolImmediate,
 670     k_BitfieldDescriptor,
 671     k_Token,
 672   } Kind;
 673
 674   SMLoc StartLoc, EndLoc, AlignmentLoc;
 675   SmallVector<unsigned, 8> Registers;
 676
 677   struct CCOp {
 678     ARMCC::CondCodes Val;
 679   };
 680
 681   struct CopOp {
 682     unsigned Val;
 683   };
 684
 685   struct CoprocOptionOp {
 686     unsigned Val;
 687   };
 688
 689   struct ITMaskOp {
 690     unsigned Mask:4;
 691   };
 692
 693   struct MBOptOp {
 694     ARM_MB::MemBOpt Val;
 695   };
 696
 697   struct ISBOptOp {
 698     ARM_ISB::InstSyncBOpt Val;
 699   };
 700
 701   struct TSBOptOp {
 702     ARM_TSB::TraceSyncBOpt Val;
 703   };
 704
 705   struct IFlagsOp {
 706     ARM_PROC::IFlags Val;
 707   };
 708
 709   struct MMaskOp {
 710     unsigned Val;
 711   };
 712
 713   struct BankedRegOp {
 714     unsigned Val;
 715   };
 716
 717   struct TokOp {
 718     const char *Data;
 719     unsigned Length;
 720   };
 721
 722   struct RegOp {
 723     unsigned RegNum;
 724   };
 725
 726   // A vector register list is a sequential list of 1 to 4 registers.
 727   struct VectorListOp {
 728     unsigned RegNum;
 729     unsigned Count;
 730     unsigned LaneIndex;
 731     bool isDoubleSpaced;
 732   };
 733
 734   struct VectorIndexOp {
 735     unsigned Val;
 736   };
 737
 738   struct ImmOp {
 739     const MCExpr *Val;
 740   };
 741
 742   /// Combined record for all forms of ARM address expressions.
 743   struct MemoryOp {
 744     unsigned BaseRegNum;
 745     // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
 746     // was specified.
 747     const MCConstantExpr *OffsetImm;  // Offset immediate value
 748     unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
 749     ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
 750     unsigned ShiftImm;        // shift for OffsetReg.
 751     unsigned Alignment;       // 0 = no alignment specified
 752     // n = alignment in bytes (2, 4, 8, 16, or 32)
 753     unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
 754   };
 755
 756   struct PostIdxRegOp {
 757     unsigned RegNum;
 758     bool isAdd;
 759     ARM_AM::ShiftOpc ShiftTy;
 760     unsigned ShiftImm;
 761   };
 762
 763   struct ShifterImmOp {
 764     bool isASR;
 765     unsigned Imm;
 766   };
 767
 768   struct RegShiftedRegOp {
 769     ARM_AM::ShiftOpc ShiftTy;
 770     unsigned SrcReg;
 771     unsigned ShiftReg;
 772     unsigned ShiftImm;
 773   };
 774
 775   struct RegShiftedImmOp {
 776     ARM_AM::ShiftOpc ShiftTy;
 777     unsigned SrcReg;
 778     unsigned ShiftImm;
 779   };
 780
 781   struct RotImmOp {
 782     unsigned Imm;
 783   };
 784
 785   struct ModImmOp {
 786     unsigned Bits;
 787     unsigned Rot;
 788   };
 789
 790   struct BitfieldOp {
 791     unsigned LSB;
 792     unsigned Width;
 793   };
 794
 795   union {
 796     struct CCOp CC;
 797     struct CopOp Cop;
 798     struct CoprocOptionOp CoprocOption;
 799     struct MBOptOp MBOpt;
 800     struct ISBOptOp ISBOpt;
 801     struct TSBOptOp TSBOpt;
 802     struct ITMaskOp ITMask;
 803     struct IFlagsOp IFlags;
 804     struct MMaskOp MMask;
 805     struct BankedRegOp BankedReg;
 806     struct TokOp Tok;
 807     struct RegOp Reg;
 808     struct VectorListOp VectorList;
 809     struct VectorIndexOp VectorIndex;
 810     struct ImmOp Imm;
 811     struct MemoryOp Memory;
 812     struct PostIdxRegOp PostIdxReg;
 813     struct ShifterImmOp ShifterImm;
 814     struct RegShiftedRegOp RegShiftedReg;
 815     struct RegShiftedImmOp RegShiftedImm;
 816     struct RotImmOp RotImm;
 817     struct ModImmOp ModImm;
 818     struct BitfieldOp Bitfield;
 819   };
 820
 821 public:
 822   ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
 823
 824   /// getStartLoc - Get the location of the first token of this operand.
 825   SMLoc getStartLoc() const override { return StartLoc; }
 826
 827   /// getEndLoc - Get the location of the last token of this operand.
 828   SMLoc getEndLoc() const override { return EndLoc; }
 829
 830   /// getLocRange - Get the range between the first and last token of this
 831   /// operand.
 832   SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
 833
 834   /// getAlignmentLoc - Get the location of the Alignment token of this operand.
 835   SMLoc getAlignmentLoc() const {
 836     assert(Kind == k_Memory && "Invalid access!");
 837     return AlignmentLoc;
 838   }
 839
 840   ARMCC::CondCodes getCondCode() const {
 841     assert(Kind == k_CondCode && "Invalid access!");
 842     return CC.Val;
 843   }
 844
 845   unsigned getCoproc() const {
 846     assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
 847     return Cop.Val;
 848   }
 849
 850   StringRef getToken() const {
 851     assert(Kind == k_Token && "Invalid access!");
 852     return StringRef(Tok.Data, Tok.Length);
 853   }
 854
 855   unsigned getReg() const override {
 856     assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
 857     return Reg.RegNum;
 858   }
 859
 860   const SmallVectorImpl<unsigned> &getRegList() const {
 861     assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
 862             Kind == k_SPRRegisterList) && "Invalid access!");
 863     return Registers;
 864   }
 865
 866   const MCExpr *getImm() const {
 867     assert(isImm() && "Invalid access!");
 868     return Imm.Val;
 869   }
 870
 871   const MCExpr *getConstantPoolImm() const {
 872     assert(isConstantPoolImm() && "Invalid access!");
 873     return Imm.Val;
 874   }
 875
 876   unsigned getVectorIndex() const {
 877     assert(Kind == k_VectorIndex && "Invalid access!");
 878     return VectorIndex.Val;
 879   }
 880
 881   ARM_MB::MemBOpt getMemBarrierOpt() const {
 882     assert(Kind == k_MemBarrierOpt && "Invalid access!");
 883     return MBOpt.Val;
 884   }
 885
 886   ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
 887     assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
 888     return ISBOpt.Val;
 889   }
 890
 891   ARM_TSB::TraceSyncBOpt getTraceSyncBarrierOpt() const {
 892     assert(Kind == k_TraceSyncBarrierOpt && "Invalid access!");
 893     return TSBOpt.Val;
 894   }
 895
 896   ARM_PROC::IFlags getProcIFlags() const {
 897     assert(Kind == k_ProcIFlags && "Invalid access!");
 898     return IFlags.Val;
 899   }
 900
 901   unsigned getMSRMask() const {
 902     assert(Kind == k_MSRMask && "Invalid access!");
 903     return MMask.Val;
 904   }
 905
 906   unsigned getBankedReg() const {
 907     assert(Kind == k_BankedReg && "Invalid access!");
 908     return BankedReg.Val;
 909   }
 910
 911   bool isCoprocNum() const { return Kind == k_CoprocNum; }
 912   bool isCoprocReg() const { return Kind == k_CoprocReg; }
 913   bool isCoprocOption() const { return Kind == k_CoprocOption; }
 914   bool isCondCode() const { return Kind == k_CondCode; }
 915   bool isCCOut() const { return Kind == k_CCOut; }
 916   bool isITMask() const { return Kind == k_ITCondMask; }
 917   bool isITCondCode() const { return Kind == k_CondCode; }
 918   bool isImm() const override {
 919     return Kind == k_Immediate;
 920   }
 921
 922   bool isARMBranchTarget() const {
 923     if (!isImm()) return false;
 924
 925     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()))
 926       return CE->getValue() % 4 == 0;
 927     return true;
 928   }
 929
 930
 931   bool isThumbBranchTarget() const {
 932     if (!isImm()) return false;
 933
 934     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()))
 935       return CE->getValue() % 2 == 0;
 936     return true;
 937   }
 938
 939   // checks whether this operand is an unsigned offset which fits is a field
 940   // of specified width and scaled by a specific number of bits
 941   template<unsigned width, unsigned scale>
 942   bool isUnsignedOffset() const {
 943     if (!isImm()) return false;
 944     if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
 945     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
 946       int64_t Val = CE->getValue();
 947       int64_t Align = 1LL << scale;
 948       int64_t Max = Align * ((1LL << width) - 1);
 949       return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
 950     }
 951     return false;
 952   }
 953
 954   // checks whether this operand is an signed offset which fits is a field
 955   // of specified width and scaled by a specific number of bits
 956   template<unsigned width, unsigned scale>
 957   bool isSignedOffset() const {
 958     if (!isImm()) return false;
 959     if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
 960     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
 961       int64_t Val = CE->getValue();
 962       int64_t Align = 1LL << scale;
 963       int64_t Max = Align * ((1LL << (width-1)) - 1);
 964       int64_t Min = -Align * (1LL << (width-1));
 965       return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
 966     }
 967     return false;
 968   }
 969
 970   // checks whether this operand is a memory operand computed as an offset
 971   // applied to PC. the offset may have 8 bits of magnitude and is represented
 972   // with two bits of shift. textually it may be either [pc, #imm], #imm or
 973   // relocable expression...
 974   bool isThumbMemPC() const {
 975     int64_t Val = 0;
 976     if (isImm()) {
 977       if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
 978       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
 979       if (!CE) return false;
 980       Val = CE->getValue();
 981     }
 982     else if (isMem()) {
 983       if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
 984       if(Memory.BaseRegNum != ARM::PC) return false;
 985       Val = Memory.OffsetImm->getValue();
 986     }
 987     else return false;
 988     return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
 989   }
 990
 991   bool isFPImm() const {
 992     if (!isImm()) return false;
 993     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
 994     if (!CE) return false;
 995     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
 996     return Val != -1;
 997   }
 998
 999   template<int64_t N, int64_t M>
1000   bool isImmediate() const {
1001     if (!isImm()) return false;
1002     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1003     if (!CE) return false;
1004     int64_t Value = CE->getValue();
1005     return Value >= N && Value <= M;
1006   }
1007
1008   template<int64_t N, int64_t M>
1009   bool isImmediateS4() const {
1010     if (!isImm()) return false;
1011     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1012     if (!CE) return false;
1013     int64_t Value = CE->getValue();
1014     return ((Value & 3) == 0) && Value >= N && Value <= M;
1015   }
1016
1017   bool isFBits16() const {
1018     return isImmediate<0, 17>();
1019   }
1020   bool isFBits32() const {
1021     return isImmediate<1, 33>();
1022   }
1023   bool isImm8s4() const {
1024     return isImmediateS4<-1020, 1020>();
1025   }
1026   bool isImm0_1020s4() const {
1027     return isImmediateS4<0, 1020>();
1028   }
1029   bool isImm0_508s4() const {
1030     return isImmediateS4<0, 508>();
1031   }
1032   bool isImm0_508s4Neg() const {
1033     if (!isImm()) return false;
1034     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1035     if (!CE) return false;
1036     int64_t Value = -CE->getValue();
1037     // explicitly exclude zero. we want that to use the normal 0_508 version.
1038     return ((Value & 3) == 0) && Value > 0 && Value <= 508;
1039   }
1040
1041   bool isImm0_4095Neg() const {
1042     if (!isImm()) return false;
1043     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1044     if (!CE) return false;
1045     // isImm0_4095Neg is used with 32-bit immediates only.
1046     // 32-bit immediates are zero extended to 64-bit when parsed,
1047     // thus simple -CE->getValue() results in a big negative number,
1048     // not a small positive number as intended
1049     if ((CE->getValue() >> 32) > 0) return false;
1050     uint32_t Value = -static_cast<uint32_t>(CE->getValue());
1051     return Value > 0 && Value < 4096;
1052   }
1053
1054   bool isImm0_7() const {
1055     return isImmediate<0, 7>();
1056   }
1057
1058   bool isImm1_16() const {
1059     return isImmediate<1, 16>();
1060   }
1061
1062   bool isImm1_32() const {
1063     return isImmediate<1, 32>();
1064   }
1065
1066   bool isImm8_255() const {
1067     return isImmediate<8, 255>();
1068   }
1069
1070   bool isImm256_65535Expr() const {
1071     if (!isImm()) return false;
1072     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1073     // If it's not a constant expression, it'll generate a fixup and be
1074     // handled later.
1075     if (!CE) return true;
1076     int64_t Value = CE->getValue();
1077     return Value >= 256 && Value < 65536;
1078   }
1079
1080   bool isImm0_65535Expr() const {
1081     if (!isImm()) return false;
1082     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1083     // If it's not a constant expression, it'll generate a fixup and be
1084     // handled later.
1085     if (!CE) return true;
1086     int64_t Value = CE->getValue();
1087     return Value >= 0 && Value < 65536;
1088   }
1089
1090   bool isImm24bit() const {
1091     return isImmediate<0, 0xffffff + 1>();
1092   }
1093
1094   bool isImmThumbSR() const {
1095     return isImmediate<1, 33>();
1096   }
1097
1098   bool isPKHLSLImm() const {
1099     return isImmediate<0, 32>();
1100   }
1101
1102   bool isPKHASRImm() const {
1103     return isImmediate<0, 33>();
1104   }
1105
1106   bool isAdrLabel() const {
1107     // If we have an immediate that's not a constant, treat it as a label
1108     // reference needing a fixup.
1109     if (isImm() && !isa<MCConstantExpr>(getImm()))
1110       return true;
1111
1112     // If it is a constant, it must fit into a modified immediate encoding.
1113     if (!isImm()) return false;
1114     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1115     if (!CE) return false;
1116     int64_t Value = CE->getValue();
1117     return (ARM_AM::getSOImmVal(Value) != -1 ||
1118             ARM_AM::getSOImmVal(-Value) != -1);
1119   }
1120
1121   bool isT2SOImm() const {
1122     // If we have an immediate that's not a constant, treat it as an expression
1123     // needing a fixup.
1124     if (isImm() && !isa<MCConstantExpr>(getImm())) {
1125       // We want to avoid matching :upper16: and :lower16: as we want these
1126       // expressions to match in isImm0_65535Expr()
1127       const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(getImm());
1128       return (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
1129                              ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16));
1130     }
1131     if (!isImm()) return false;
1132     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1133     if (!CE) return false;
1134     int64_t Value = CE->getValue();
1135     return ARM_AM::getT2SOImmVal(Value) != -1;
1136   }
1137
1138   bool isT2SOImmNot() const {
1139     if (!isImm()) return false;
1140     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1141     if (!CE) return false;
1142     int64_t Value = CE->getValue();
1143     return ARM_AM::getT2SOImmVal(Value) == -1 &&
1144       ARM_AM::getT2SOImmVal(~Value) != -1;
1145   }
1146
1147   bool isT2SOImmNeg() const {
1148     if (!isImm()) return false;
1149     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1150     if (!CE) return false;
1151     int64_t Value = CE->getValue();
1152     // Only use this when not representable as a plain so_imm.
1153     return ARM_AM::getT2SOImmVal(Value) == -1 &&
1154       ARM_AM::getT2SOImmVal(-Value) != -1;
1155   }
1156
1157   bool isSetEndImm() const {
1158     if (!isImm()) return false;
1159     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1160     if (!CE) return false;
1161     int64_t Value = CE->getValue();
1162     return Value == 1 || Value == 0;
1163   }
1164
1165   bool isReg() const override { return Kind == k_Register; }
1166   bool isRegList() const { return Kind == k_RegisterList; }
1167   bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1168   bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1169   bool isToken() const override { return Kind == k_Token; }
1170   bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1171   bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1172   bool isTraceSyncBarrierOpt() const { return Kind == k_TraceSyncBarrierOpt; }
1173   bool isMem() const override {
1174     if (Kind != k_Memory)
1175       return false;
1176     if (Memory.BaseRegNum &&
1177         !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum))
1178       return false;
1179     if (Memory.OffsetRegNum &&
1180         !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.OffsetRegNum))
1181       return false;
1182     return true;
1183   }
1184   bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1185   bool isRegShiftedReg() const {
1186     return Kind == k_ShiftedRegister &&
1187            ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1188                RegShiftedReg.SrcReg) &&
1189            ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1190                RegShiftedReg.ShiftReg);
1191   }
1192   bool isRegShiftedImm() const {
1193     return Kind == k_ShiftedImmediate &&
1194            ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1195                RegShiftedImm.SrcReg);
1196   }
1197   bool isRotImm() const { return Kind == k_RotateImmediate; }
1198   bool isModImm() const { return Kind == k_ModifiedImmediate; }
1199
1200   bool isModImmNot() const {
1201     if (!isImm()) return false;
1202     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1203     if (!CE) return false;
1204     int64_t Value = CE->getValue();
1205     return ARM_AM::getSOImmVal(~Value) != -1;
1206   }
1207
1208   bool isModImmNeg() const {
1209     if (!isImm()) return false;
1210     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1211     if (!CE) return false;
1212     int64_t Value = CE->getValue();
1213     return ARM_AM::getSOImmVal(Value) == -1 &&
1214       ARM_AM::getSOImmVal(-Value) != -1;
1215   }
1216
1217   bool isThumbModImmNeg1_7() const {
1218     if (!isImm()) return false;
1219     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1220     if (!CE) return false;
1221     int32_t Value = -(int32_t)CE->getValue();
1222     return 0 < Value && Value < 8;
1223   }
1224
1225   bool isThumbModImmNeg8_255() const {
1226     if (!isImm()) return false;
1227     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1228     if (!CE) return false;
1229     int32_t Value = -(int32_t)CE->getValue();
1230     return 7 < Value && Value < 256;
1231   }
1232
1233   bool isConstantPoolImm() const { return Kind == k_ConstantPoolImmediate; }
1234   bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1235   bool isPostIdxRegShifted() const {
1236     return Kind == k_PostIndexRegister &&
1237            ARMMCRegisterClasses[ARM::GPRRegClassID].contains(PostIdxReg.RegNum);
1238   }
1239   bool isPostIdxReg() const {
1240     return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift;
1241   }
1242   bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1243     if (!isMem())
1244       return false;
1245     // No offset of any kind.
1246     return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1247      (alignOK || Memory.Alignment == Alignment);
1248   }
1249   bool isMemPCRelImm12() const {
1250     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1251       return false;
1252     // Base register must be PC.
1253     if (Memory.BaseRegNum != ARM::PC)
1254       return false;
1255     // Immediate offset in range [-4095, 4095].
1256     if (!Memory.OffsetImm) return true;
1257     int64_t Val = Memory.OffsetImm->getValue();
1258     return (Val > -4096 && Val < 4096) ||
1259            (Val == std::numeric_limits<int32_t>::min());
1260   }
1261
1262   bool isAlignedMemory() const {
1263     return isMemNoOffset(true);
1264   }
1265
1266   bool isAlignedMemoryNone() const {
1267     return isMemNoOffset(false, 0);
1268   }
1269
1270   bool isDupAlignedMemoryNone() const {
1271     return isMemNoOffset(false, 0);
1272   }
1273
1274   bool isAlignedMemory16() const {
1275     if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1276       return true;
1277     return isMemNoOffset(false, 0);
1278   }
1279
1280   bool isDupAlignedMemory16() const {
1281     if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1282       return true;
1283     return isMemNoOffset(false, 0);
1284   }
1285
1286   bool isAlignedMemory32() const {
1287     if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1288       return true;
1289     return isMemNoOffset(false, 0);
1290   }
1291
1292   bool isDupAlignedMemory32() const {
1293     if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1294       return true;
1295     return isMemNoOffset(false, 0);
1296   }
1297
1298   bool isAlignedMemory64() const {
1299     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1300       return true;
1301     return isMemNoOffset(false, 0);
1302   }
1303
1304   bool isDupAlignedMemory64() const {
1305     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1306       return true;
1307     return isMemNoOffset(false, 0);
1308   }
1309
1310   bool isAlignedMemory64or128() const {
1311     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1312       return true;
1313     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1314       return true;
1315     return isMemNoOffset(false, 0);
1316   }
1317
1318   bool isDupAlignedMemory64or128() const {
1319     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1320       return true;
1321     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1322       return true;
1323     return isMemNoOffset(false, 0);
1324   }
1325
1326   bool isAlignedMemory64or128or256() const {
1327     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1328       return true;
1329     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1330       return true;
1331     if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1332       return true;
1333     return isMemNoOffset(false, 0);
1334   }
1335
1336   bool isAddrMode2() const {
1337     if (!isMem() || Memory.Alignment != 0) return false;
1338     // Check for register offset.
1339     if (Memory.OffsetRegNum) return true;
1340     // Immediate offset in range [-4095, 4095].
1341     if (!Memory.OffsetImm) return true;
1342     int64_t Val = Memory.OffsetImm->getValue();
1343     return Val > -4096 && Val < 4096;
1344   }
1345
1346   bool isAM2OffsetImm() const {
1347     if (!isImm()) return false;
1348     // Immediate offset in range [-4095, 4095].
1349     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1350     if (!CE) return false;
1351     int64_t Val = CE->getValue();
1352     return (Val == std::numeric_limits<int32_t>::min()) ||
1353            (Val > -4096 && Val < 4096);
1354   }
1355
1356   bool isAddrMode3() const {
1357     // If we have an immediate that's not a constant, treat it as a label
1358     // reference needing a fixup. If it is a constant, it's something else
1359     // and we reject it.
1360     if (isImm() && !isa<MCConstantExpr>(getImm()))
1361       return true;
1362     if (!isMem() || Memory.Alignment != 0) return false;
1363     // No shifts are legal for AM3.
1364     if (Memory.ShiftType != ARM_AM::no_shift) return false;
1365     // Check for register offset.
1366     if (Memory.OffsetRegNum) return true;
1367     // Immediate offset in range [-255, 255].
1368     if (!Memory.OffsetImm) return true;
1369     int64_t Val = Memory.OffsetImm->getValue();
1370     // The #-0 offset is encoded as std::numeric_limits<int32_t>::min(), and we
1371     // have to check for this too.
1372     return (Val > -256 && Val < 256) ||
1373            Val == std::numeric_limits<int32_t>::min();
1374   }
1375
1376   bool isAM3Offset() const {
1377     if (isPostIdxReg())
1378       return true;
1379     if (!isImm())
1380       return false;
1381     // Immediate offset in range [-255, 255].
1382     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1383     if (!CE) return false;
1384     int64_t Val = CE->getValue();
1385     // Special case, #-0 is std::numeric_limits<int32_t>::min().
1386     return (Val > -256 && Val < 256) ||
1387            Val == std::numeric_limits<int32_t>::min();
1388   }
1389
1390   bool isAddrMode5() const {
1391     // If we have an immediate that's not a constant, treat it as a label
1392     // reference needing a fixup. If it is a constant, it's something else
1393     // and we reject it.
1394     if (isImm() && !isa<MCConstantExpr>(getImm()))
1395       return true;
1396     if (!isMem() || Memory.Alignment != 0) return false;
1397     // Check for register offset.
1398     if (Memory.OffsetRegNum) return false;
1399     // Immediate offset in range [-1020, 1020] and a multiple of 4.
1400     if (!Memory.OffsetImm) return true;
1401     int64_t Val = Memory.OffsetImm->getValue();
1402     return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1403       Val == std::numeric_limits<int32_t>::min();
1404   }
1405
1406   bool isAddrMode5FP16() const {
1407     // If we have an immediate that's not a constant, treat it as a label
1408     // reference needing a fixup. If it is a constant, it's something else
1409     // and we reject it.
1410     if (isImm() && !isa<MCConstantExpr>(getImm()))
1411       return true;
1412     if (!isMem() || Memory.Alignment != 0) return false;
1413     // Check for register offset.
1414     if (Memory.OffsetRegNum) return false;
1415     // Immediate offset in range [-510, 510] and a multiple of 2.
1416     if (!Memory.OffsetImm) return true;
1417     int64_t Val = Memory.OffsetImm->getValue();
1418     return (Val >= -510 && Val <= 510 && ((Val & 1) == 0)) ||
1419            Val == std::numeric_limits<int32_t>::min();
1420   }
1421
1422   bool isMemTBB() const {
1423     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1424         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1425       return false;
1426     return true;
1427   }
1428
1429   bool isMemTBH() const {
1430     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1431         Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1432         Memory.Alignment != 0 )
1433       return false;
1434     return true;
1435   }
1436
1437   bool isMemRegOffset() const {
1438     if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1439       return false;
1440     return true;
1441   }
1442
1443   bool isT2MemRegOffset() const {
1444     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1445         Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC)
1446       return false;
1447     // Only lsl #{0, 1, 2, 3} allowed.
1448     if (Memory.ShiftType == ARM_AM::no_shift)
1449       return true;
1450     if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1451       return false;
1452     return true;
1453   }
1454
1455   bool isMemThumbRR() const {
1456     // Thumb reg+reg addressing is simple. Just two registers, a base and
1457     // an offset. No shifts, negations or any other complicating factors.
1458     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1459         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1460       return false;
1461     return isARMLowRegister(Memory.BaseRegNum) &&
1462       (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1463   }
1464
1465   bool isMemThumbRIs4() const {
1466     if (!isMem() || Memory.OffsetRegNum != 0 ||
1467         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1468       return false;
1469     // Immediate offset, multiple of 4 in range [0, 124].
1470     if (!Memory.OffsetImm) return true;
1471     int64_t Val = Memory.OffsetImm->getValue();
1472     return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1473   }
1474
1475   bool isMemThumbRIs2() const {
1476     if (!isMem() || Memory.OffsetRegNum != 0 ||
1477         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1478       return false;
1479     // Immediate offset, multiple of 4 in range [0, 62].
1480     if (!Memory.OffsetImm) return true;
1481     int64_t Val = Memory.OffsetImm->getValue();
1482     return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1483   }
1484
1485   bool isMemThumbRIs1() const {
1486     if (!isMem() || Memory.OffsetRegNum != 0 ||
1487         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1488       return false;
1489     // Immediate offset in range [0, 31].
1490     if (!Memory.OffsetImm) return true;
1491     int64_t Val = Memory.OffsetImm->getValue();
1492     return Val >= 0 && Val <= 31;
1493   }
1494
1495   bool isMemThumbSPI() const {
1496     if (!isMem() || Memory.OffsetRegNum != 0 ||
1497         Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1498       return false;
1499     // Immediate offset, multiple of 4 in range [0, 1020].
1500     if (!Memory.OffsetImm) return true;
1501     int64_t Val = Memory.OffsetImm->getValue();
1502     return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1503   }
1504
1505   bool isMemImm8s4Offset() const {
1506     // If we have an immediate that's not a constant, treat it as a label
1507     // reference needing a fixup. If it is a constant, it's something else
1508     // and we reject it.
1509     if (isImm() && !isa<MCConstantExpr>(getImm()))
1510       return true;
1511     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1512       return false;
1513     // Immediate offset a multiple of 4 in range [-1020, 1020].
1514     if (!Memory.OffsetImm) return true;
1515     int64_t Val = Memory.OffsetImm->getValue();
1516     // Special case, #-0 is std::numeric_limits<int32_t>::min().
1517     return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) ||
1518            Val == std::numeric_limits<int32_t>::min();
1519   }
1520
1521   bool isMemImm0_1020s4Offset() const {
1522     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1523       return false;
1524     // Immediate offset a multiple of 4 in range [0, 1020].
1525     if (!Memory.OffsetImm) return true;
1526     int64_t Val = Memory.OffsetImm->getValue();
1527     return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1528   }
1529
1530   bool isMemImm8Offset() const {
1531     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1532       return false;
1533     // Base reg of PC isn't allowed for these encodings.
1534     if (Memory.BaseRegNum == ARM::PC) return false;
1535     // Immediate offset in range [-255, 255].
1536     if (!Memory.OffsetImm) return true;
1537     int64_t Val = Memory.OffsetImm->getValue();
1538     return (Val == std::numeric_limits<int32_t>::min()) ||
1539            (Val > -256 && Val < 256);
1540   }
1541
1542   bool isMemPosImm8Offset() const {
1543     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1544       return false;
1545     // Immediate offset in range [0, 255].
1546     if (!Memory.OffsetImm) return true;
1547     int64_t Val = Memory.OffsetImm->getValue();
1548     return Val >= 0 && Val < 256;
1549   }
1550
1551   bool isMemNegImm8Offset() const {
1552     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1553       return false;
1554     // Base reg of PC isn't allowed for these encodings.
1555     if (Memory.BaseRegNum == ARM::PC) return false;
1556     // Immediate offset in range [-255, -1].
1557     if (!Memory.OffsetImm) return false;
1558     int64_t Val = Memory.OffsetImm->getValue();
1559     return (Val == std::numeric_limits<int32_t>::min()) ||
1560            (Val > -256 && Val < 0);
1561   }
1562
1563   bool isMemUImm12Offset() const {
1564     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1565       return false;
1566     // Immediate offset in range [0, 4095].
1567     if (!Memory.OffsetImm) return true;
1568     int64_t Val = Memory.OffsetImm->getValue();
1569     return (Val >= 0 && Val < 4096);
1570   }
1571
1572   bool isMemImm12Offset() const {
1573     // If we have an immediate that's not a constant, treat it as a label
1574     // reference needing a fixup. If it is a constant, it's something else
1575     // and we reject it.
1576
1577     if (isImm() && !isa<MCConstantExpr>(getImm()))
1578       return true;
1579
1580     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1581       return false;
1582     // Immediate offset in range [-4095, 4095].
1583     if (!Memory.OffsetImm) return true;
1584     int64_t Val = Memory.OffsetImm->getValue();
1585     return (Val > -4096 && Val < 4096) ||
1586            (Val == std::numeric_limits<int32_t>::min());
1587   }
1588
1589   bool isConstPoolAsmImm() const {
1590     // Delay processing of Constant Pool Immediate, this will turn into
1591     // a constant. Match no other operand
1592     return (isConstantPoolImm());
1593   }
1594
1595   bool isPostIdxImm8() const {
1596     if (!isImm()) return false;
1597     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1598     if (!CE) return false;
1599     int64_t Val = CE->getValue();
1600     return (Val > -256 && Val < 256) ||
1601            (Val == std::numeric_limits<int32_t>::min());
1602   }
1603
1604   bool isPostIdxImm8s4() const {
1605     if (!isImm()) return false;
1606     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1607     if (!CE) return false;
1608     int64_t Val = CE->getValue();
1609     return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1610            (Val == std::numeric_limits<int32_t>::min());
1611   }
1612
1613   bool isMSRMask() const { return Kind == k_MSRMask; }
1614   bool isBankedReg() const { return Kind == k_BankedReg; }
1615   bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1616
1617   // NEON operands.
1618   bool isSingleSpacedVectorList() const {
1619     return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1620   }
1621
1622   bool isDoubleSpacedVectorList() const {
1623     return Kind == k_VectorList && VectorList.isDoubleSpaced;
1624   }
1625
1626   bool isVecListOneD() const {
1627     if (!isSingleSpacedVectorList()) return false;
1628     return VectorList.Count == 1;
1629   }
1630
1631   bool isVecListDPair() const {
1632     if (!isSingleSpacedVectorList()) return false;
1633     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1634               .contains(VectorList.RegNum));
1635   }
1636
1637   bool isVecListThreeD() const {
1638     if (!isSingleSpacedVectorList()) return false;
1639     return VectorList.Count == 3;
1640   }
1641
1642   bool isVecListFourD() const {
1643     if (!isSingleSpacedVectorList()) return false;
1644     return VectorList.Count == 4;
1645   }
1646
1647   bool isVecListDPairSpaced() const {
1648     if (Kind != k_VectorList) return false;
1649     if (isSingleSpacedVectorList()) return false;
1650     return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1651               .contains(VectorList.RegNum));
1652   }
1653
1654   bool isVecListThreeQ() const {
1655     if (!isDoubleSpacedVectorList()) return false;
1656     return VectorList.Count == 3;
1657   }
1658
1659   bool isVecListFourQ() const {
1660     if (!isDoubleSpacedVectorList()) return false;
1661     return VectorList.Count == 4;
1662   }
1663
1664   bool isSingleSpacedVectorAllLanes() const {
1665     return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1666   }
1667
1668   bool isDoubleSpacedVectorAllLanes() const {
1669     return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1670   }
1671
1672   bool isVecListOneDAllLanes() const {
1673     if (!isSingleSpacedVectorAllLanes()) return false;
1674     return VectorList.Count == 1;
1675   }
1676
1677   bool isVecListDPairAllLanes() const {
1678     if (!isSingleSpacedVectorAllLanes()) return false;
1679     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1680               .contains(VectorList.RegNum));
1681   }
1682
1683   bool isVecListDPairSpacedAllLanes() const {
1684     if (!isDoubleSpacedVectorAllLanes()) return false;
1685     return VectorList.Count == 2;
1686   }
1687
1688   bool isVecListThreeDAllLanes() const {
1689     if (!isSingleSpacedVectorAllLanes()) return false;
1690     return VectorList.Count == 3;
1691   }
1692
1693   bool isVecListThreeQAllLanes() const {
1694     if (!isDoubleSpacedVectorAllLanes()) return false;
1695     return VectorList.Count == 3;
1696   }
1697
1698   bool isVecListFourDAllLanes() const {
1699     if (!isSingleSpacedVectorAllLanes()) return false;
1700     return VectorList.Count == 4;
1701   }
1702
1703   bool isVecListFourQAllLanes() const {
1704     if (!isDoubleSpacedVectorAllLanes()) return false;
1705     return VectorList.Count == 4;
1706   }
1707
1708   bool isSingleSpacedVectorIndexed() const {
1709     return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1710   }
1711
1712   bool isDoubleSpacedVectorIndexed() const {
1713     return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1714   }
1715
1716   bool isVecListOneDByteIndexed() const {
1717     if (!isSingleSpacedVectorIndexed()) return false;
1718     return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1719   }
1720
1721   bool isVecListOneDHWordIndexed() const {
1722     if (!isSingleSpacedVectorIndexed()) return false;
1723     return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1724   }
1725
1726   bool isVecListOneDWordIndexed() const {
1727     if (!isSingleSpacedVectorIndexed()) return false;
1728     return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1729   }
1730
1731   bool isVecListTwoDByteIndexed() const {
1732     if (!isSingleSpacedVectorIndexed()) return false;
1733     return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1734   }
1735
1736   bool isVecListTwoDHWordIndexed() const {
1737     if (!isSingleSpacedVectorIndexed()) return false;
1738     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1739   }
1740
1741   bool isVecListTwoQWordIndexed() const {
1742     if (!isDoubleSpacedVectorIndexed()) return false;
1743     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1744   }
1745
1746   bool isVecListTwoQHWordIndexed() const {
1747     if (!isDoubleSpacedVectorIndexed()) return false;
1748     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1749   }
1750
1751   bool isVecListTwoDWordIndexed() const {
1752     if (!isSingleSpacedVectorIndexed()) return false;
1753     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1754   }
1755
1756   bool isVecListThreeDByteIndexed() const {
1757     if (!isSingleSpacedVectorIndexed()) return false;
1758     return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1759   }
1760
1761   bool isVecListThreeDHWordIndexed() const {
1762     if (!isSingleSpacedVectorIndexed()) return false;
1763     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1764   }
1765
1766   bool isVecListThreeQWordIndexed() const {
1767     if (!isDoubleSpacedVectorIndexed()) return false;
1768     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1769   }
1770
1771   bool isVecListThreeQHWordIndexed() const {
1772     if (!isDoubleSpacedVectorIndexed()) return false;
1773     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1774   }
1775
1776   bool isVecListThreeDWordIndexed() const {
1777     if (!isSingleSpacedVectorIndexed()) return false;
1778     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1779   }
1780
1781   bool isVecListFourDByteIndexed() const {
1782     if (!isSingleSpacedVectorIndexed()) return false;
1783     return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1784   }
1785
1786   bool isVecListFourDHWordIndexed() const {
1787     if (!isSingleSpacedVectorIndexed()) return false;
1788     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1789   }
1790
1791   bool isVecListFourQWordIndexed() const {
1792     if (!isDoubleSpacedVectorIndexed()) return false;
1793     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1794   }
1795
1796   bool isVecListFourQHWordIndexed() const {
1797     if (!isDoubleSpacedVectorIndexed()) return false;
1798     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1799   }
1800
1801   bool isVecListFourDWordIndexed() const {
1802     if (!isSingleSpacedVectorIndexed()) return false;
1803     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1804   }
1805
1806   bool isVectorIndex8() const {
1807     if (Kind != k_VectorIndex) return false;
1808     return VectorIndex.Val < 8;
1809   }
1810
1811   bool isVectorIndex16() const {
1812     if (Kind != k_VectorIndex) return false;
1813     return VectorIndex.Val < 4;
1814   }
1815
1816   bool isVectorIndex32() const {
1817     if (Kind != k_VectorIndex) return false;
1818     return VectorIndex.Val < 2;
1819   }
1820   bool isVectorIndex64() const {
1821     if (Kind != k_VectorIndex) return false;
1822     return VectorIndex.Val < 1;
1823   }
1824
1825   bool isNEONi8splat() const {
1826     if (!isImm()) return false;
1827     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1828     // Must be a constant.
1829     if (!CE) return false;
1830     int64_t Value = CE->getValue();
1831     // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1832     // value.
1833     return Value >= 0 && Value < 256;
1834   }
1835
1836   bool isNEONi16splat() const {
1837     if (isNEONByteReplicate(2))
1838       return false; // Leave that for bytes replication and forbid by default.
1839     if (!isImm())
1840       return false;
1841     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1842     // Must be a constant.
1843     if (!CE) return false;
1844     unsigned Value = CE->getValue();
1845     return ARM_AM::isNEONi16splat(Value);
1846   }
1847
1848   bool isNEONi16splatNot() const {
1849     if (!isImm())
1850       return false;
1851     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1852     // Must be a constant.
1853     if (!CE) return false;
1854     unsigned Value = CE->getValue();
1855     return ARM_AM::isNEONi16splat(~Value & 0xffff);
1856   }
1857
1858   bool isNEONi32splat() const {
1859     if (isNEONByteReplicate(4))
1860       return false; // Leave that for bytes replication and forbid by default.
1861     if (!isImm())
1862       return false;
1863     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1864     // Must be a constant.
1865     if (!CE) return false;
1866     unsigned Value = CE->getValue();
1867     return ARM_AM::isNEONi32splat(Value);
1868   }
1869
1870   bool isNEONi32splatNot() const {
1871     if (!isImm())
1872       return false;
1873     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1874     // Must be a constant.
1875     if (!CE) return false;
1876     unsigned Value = CE->getValue();
1877     return ARM_AM::isNEONi32splat(~Value);
1878   }
1879
1880   static bool isValidNEONi32vmovImm(int64_t Value) {
1881     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1882     // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1883     return ((Value & 0xffffffffffffff00) == 0) ||
1884            ((Value & 0xffffffffffff00ff) == 0) ||
1885            ((Value & 0xffffffffff00ffff) == 0) ||
1886            ((Value & 0xffffffff00ffffff) == 0) ||
1887            ((Value & 0xffffffffffff00ff) == 0xff) ||
1888            ((Value & 0xffffffffff00ffff) == 0xffff);
1889   }
1890
1891   bool isNEONReplicate(unsigned Width, unsigned NumElems, bool Inv) const {
1892     assert((Width == 8 || Width == 16 || Width == 32) &&
1893            "Invalid element width");
1894     assert(NumElems * Width <= 64 && "Invalid result width");
1895
1896     if (!isImm())
1897       return false;
1898     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1899     // Must be a constant.
1900     if (!CE)
1901       return false;
1902     int64_t Value = CE->getValue();
1903     if (!Value)
1904       return false; // Don't bother with zero.
1905     if (Inv)
1906       Value = ~Value;
1907
1908     uint64_t Mask = (1ull << Width) - 1;
1909     uint64_t Elem = Value & Mask;
1910     if (Width == 16 && (Elem & 0x00ff) != 0 && (Elem & 0xff00) != 0)
1911       return false;
1912     if (Width == 32 && !isValidNEONi32vmovImm(Elem))
1913       return false;
1914
1915     for (unsigned i = 1; i < NumElems; ++i) {
1916       Value >>= Width;
1917       if ((Value & Mask) != Elem)
1918         return false;
1919     }
1920     return true;
1921   }
1922
1923   bool isNEONByteReplicate(unsigned NumBytes) const {
1924     return isNEONReplicate(8, NumBytes, false);
1925   }
1926
1927   static void checkNeonReplicateArgs(unsigned FromW, unsigned ToW) {
1928     assert((FromW == 8 || FromW == 16 || FromW == 32) &&
1929            "Invalid source width");
1930     assert((ToW == 16 || ToW == 32 || ToW == 64) &&
1931            "Invalid destination width");
1932     assert(FromW < ToW && "ToW is not less than FromW");
1933   }
1934
1935   template<unsigned FromW, unsigned ToW>
1936   bool isNEONmovReplicate() const {
1937     checkNeonReplicateArgs(FromW, ToW);
1938     if (ToW == 64 && isNEONi64splat())
1939       return false;
1940     return isNEONReplicate(FromW, ToW / FromW, false);
1941   }
1942
1943   template<unsigned FromW, unsigned ToW>
1944   bool isNEONinvReplicate() const {
1945     checkNeonReplicateArgs(FromW, ToW);
1946     return isNEONReplicate(FromW, ToW / FromW, true);
1947   }
1948
1949   bool isNEONi32vmov() const {
1950     if (isNEONByteReplicate(4))
1951       return false; // Let it to be classified as byte-replicate case.
1952     if (!isImm())
1953       return false;
1954     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1955     // Must be a constant.
1956     if (!CE)
1957       return false;
1958     return isValidNEONi32vmovImm(CE->getValue());
1959   }
1960
1961   bool isNEONi32vmovNeg() const {
1962     if (!isImm()) return false;
1963     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1964     // Must be a constant.
1965     if (!CE) return false;
1966     return isValidNEONi32vmovImm(~CE->getValue());
1967   }
1968
1969   bool isNEONi64splat() const {
1970     if (!isImm()) return false;
1971     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1972     // Must be a constant.
1973     if (!CE) return false;
1974     uint64_t Value = CE->getValue();
1975     // i64 value with each byte being either 0 or 0xff.
1976     for (unsigned i = 0; i < 8; ++i, Value >>= 8)
1977       if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1978     return true;
1979   }
1980
1981   template<int64_t Angle, int64_t Remainder>
1982   bool isComplexRotation() const {
1983     if (!isImm()) return false;
1984
1985     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1986     if (!CE) return false;
1987     uint64_t Value = CE->getValue();
1988
1989     return (Value % Angle == Remainder && Value <= 270);
1990   }
1991
1992   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1993     // Add as immediates when possible.  Null MCExpr = 0.
1994     if (!Expr)
1995       Inst.addOperand(MCOperand::createImm(0));
1996     else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1997       Inst.addOperand(MCOperand::createImm(CE->getValue()));
1998     else
1999       Inst.addOperand(MCOperand::createExpr(Expr));
2000   }
2001
2002   void addARMBranchTargetOperands(MCInst &Inst, unsigned N) const {
2003     assert(N == 1 && "Invalid number of operands!");
2004     addExpr(Inst, getImm());
2005   }
2006
2007   void addThumbBranchTargetOperands(MCInst &Inst, unsigned N) const {
2008     assert(N == 1 && "Invalid number of operands!");
2009     addExpr(Inst, getImm());
2010   }
2011
2012   void addCondCodeOperands(MCInst &Inst, unsigned N) const {
2013     assert(N == 2 && "Invalid number of operands!");
2014     Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
2015     unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
2016     Inst.addOperand(MCOperand::createReg(RegNum));
2017   }
2018
2019   void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
2020     assert(N == 1 && "Invalid number of operands!");
2021     Inst.addOperand(MCOperand::createImm(getCoproc()));
2022   }
2023
2024   void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
2025     assert(N == 1 && "Invalid number of operands!");
2026     Inst.addOperand(MCOperand::createImm(getCoproc()));
2027   }
2028
2029   void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
2030     assert(N == 1 && "Invalid number of operands!");
2031     Inst.addOperand(MCOperand::createImm(CoprocOption.Val));
2032   }
2033
2034   void addITMaskOperands(MCInst &Inst, unsigned N) const {
2035     assert(N == 1 && "Invalid number of operands!");
2036     Inst.addOperand(MCOperand::createImm(ITMask.Mask));
2037   }
2038
2039   void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
2040     assert(N == 1 && "Invalid number of operands!");
2041     Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
2042   }
2043
2044   void addCCOutOperands(MCInst &Inst, unsigned N) const {
2045     assert(N == 1 && "Invalid number of operands!");
2046     Inst.addOperand(MCOperand::createReg(getReg()));
2047   }
2048
2049   void addRegOperands(MCInst &Inst, unsigned N) const {
2050     assert(N == 1 && "Invalid number of operands!");
2051     Inst.addOperand(MCOperand::createReg(getReg()));
2052   }
2053
2054   void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
2055     assert(N == 3 && "Invalid number of operands!");
2056     assert(isRegShiftedReg() &&
2057            "addRegShiftedRegOperands() on non-RegShiftedReg!");
2058     Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg));
2059     Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg));
2060     Inst.addOperand(MCOperand::createImm(
2061       ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
2062   }
2063
2064   void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
2065     assert(N == 2 && "Invalid number of operands!");
2066     assert(isRegShiftedImm() &&
2067            "addRegShiftedImmOperands() on non-RegShiftedImm!");
2068     Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg));
2069     // Shift of #32 is encoded as 0 where permitted
2070     unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
2071     Inst.addOperand(MCOperand::createImm(
2072       ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
2073   }
2074
2075   void addShifterImmOperands(MCInst &Inst, unsigned N) const {
2076     assert(N == 1 && "Invalid number of operands!");
2077     Inst.addOperand(MCOperand::createImm((ShifterImm.isASR << 5) |
2078                                          ShifterImm.Imm));
2079   }
2080
2081   void addRegListOperands(MCInst &Inst, unsigned N) const {
2082     assert(N == 1 && "Invalid number of operands!");
2083     const SmallVectorImpl<unsigned> &RegList = getRegList();
2084     for (SmallVectorImpl<unsigned>::const_iterator
2085            I = RegList.begin(), E = RegList.end(); I != E; ++I)
2086       Inst.addOperand(MCOperand::createReg(*I));
2087   }
2088
2089   void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
2090     addRegListOperands(Inst, N);
2091   }
2092
2093   void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
2094     addRegListOperands(Inst, N);
2095   }
2096
2097   void addRotImmOperands(MCInst &Inst, unsigned N) const {
2098     assert(N == 1 && "Invalid number of operands!");
2099     // Encoded as val>>3. The printer handles display as 8, 16, 24.
2100     Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3));
2101   }
2102
2103   void addModImmOperands(MCInst &Inst, unsigned N) const {
2104     assert(N == 1 && "Invalid number of operands!");
2105
2106     // Support for fixups (MCFixup)
2107     if (isImm())
2108       return addImmOperands(Inst, N);
2109
2110     Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7)));
2111   }
2112
2113   void addModImmNotOperands(MCInst &Inst, unsigned N) const {
2114     assert(N == 1 && "Invalid number of operands!");
2115     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2116     uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue());
2117     Inst.addOperand(MCOperand::createImm(Enc));
2118   }
2119
2120   void addModImmNegOperands(MCInst &Inst, unsigned N) const {
2121     assert(N == 1 && "Invalid number of operands!");
2122     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2123     uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue());
2124     Inst.addOperand(MCOperand::createImm(Enc));
2125   }
2126
2127   void addThumbModImmNeg8_255Operands(MCInst &Inst, unsigned N) const {
2128     assert(N == 1 && "Invalid number of operands!");
2129     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2130     uint32_t Val = -CE->getValue();
2131     Inst.addOperand(MCOperand::createImm(Val));
2132   }
2133
2134   void addThumbModImmNeg1_7Operands(MCInst &Inst, unsigned N) const {
2135     assert(N == 1 && "Invalid number of operands!");
2136     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2137     uint32_t Val = -CE->getValue();
2138     Inst.addOperand(MCOperand::createImm(Val));
2139   }
2140
2141   void addBitfieldOperands(MCInst &Inst, unsigned N) const {
2142     assert(N == 1 && "Invalid number of operands!");
2143     // Munge the lsb/width into a bitfield mask.
2144     unsigned lsb = Bitfield.LSB;
2145     unsigned width = Bitfield.Width;
2146     // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
2147     uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
2148                       (32 - (lsb + width)));
2149     Inst.addOperand(MCOperand::createImm(Mask));
2150   }
2151
2152   void addImmOperands(MCInst &Inst, unsigned N) const {
2153     assert(N == 1 && "Invalid number of operands!");
2154     addExpr(Inst, getImm());
2155   }
2156
2157   void addFBits16Operands(MCInst &Inst, unsigned N) const {
2158     assert(N == 1 && "Invalid number of operands!");
2159     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2160     Inst.addOperand(MCOperand::createImm(16 - CE->getValue()));
2161   }
2162
2163   void addFBits32Operands(MCInst &Inst, unsigned N) const {
2164     assert(N == 1 && "Invalid number of operands!");
2165     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2166     Inst.addOperand(MCOperand::createImm(32 - CE->getValue()));
2167   }
2168
2169   void addFPImmOperands(MCInst &Inst, unsigned N) const {
2170     assert(N == 1 && "Invalid number of operands!");
2171     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2172     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
2173     Inst.addOperand(MCOperand::createImm(Val));
2174   }
2175
2176   void addImm8s4Operands(MCInst &Inst, unsigned N) const {
2177     assert(N == 1 && "Invalid number of operands!");
2178     // FIXME: We really want to scale the value here, but the LDRD/STRD
2179     // instruction don't encode operands that way yet.
2180     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2181     Inst.addOperand(MCOperand::createImm(CE->getValue()));
2182   }
2183
2184   void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
2185     assert(N == 1 && "Invalid number of operands!");
2186     // The immediate is scaled by four in the encoding and is stored
2187     // in the MCInst as such. Lop off the low two bits here.
2188     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2189     Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
2190   }
2191
2192   void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
2193     assert(N == 1 && "Invalid number of operands!");
2194     // The immediate is scaled by four in the encoding and is stored
2195     // in the MCInst as such. Lop off the low two bits here.
2196     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2197     Inst.addOperand(MCOperand::createImm(-(CE->getValue() / 4)));
2198   }
2199
2200   void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
2201     assert(N == 1 && "Invalid number of operands!");
2202     // The immediate is scaled by four in the encoding and is stored
2203     // in the MCInst as such. Lop off the low two bits here.
2204     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2205     Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
2206   }
2207
2208   void addImm1_16Operands(MCInst &Inst, unsigned N) const {
2209     assert(N == 1 && "Invalid number of operands!");
2210     // The constant encodes as the immediate-1, and we store in the instruction
2211     // the bits as encoded, so subtract off one here.
2212     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2213     Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
2214   }
2215
2216   void addImm1_32Operands(MCInst &Inst, unsigned N) const {
2217     assert(N == 1 && "Invalid number of operands!");
2218     // The constant encodes as the immediate-1, and we store in the instruction
2219     // the bits as encoded, so subtract off one here.
2220     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2221     Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
2222   }
2223
2224   void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
2225     assert(N == 1 && "Invalid number of operands!");
2226     // The constant encodes as the immediate, except for 32, which encodes as
2227     // zero.
2228     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2229     unsigned Imm = CE->getValue();
2230     Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm)));
2231   }
2232
2233   void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
2234     assert(N == 1 && "Invalid number of operands!");
2235     // An ASR value of 32 encodes as 0, so that's how we want to add it to
2236     // the instruction as well.
2237     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2238     int Val = CE->getValue();
2239     Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val));
2240   }
2241
2242   void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
2243     assert(N == 1 && "Invalid number of operands!");
2244     // The operand is actually a t2_so_imm, but we have its bitwise
2245     // negation in the assembly source, so twiddle it here.
2246     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2247     Inst.addOperand(MCOperand::createImm(~(uint32_t)CE->getValue()));
2248   }
2249
2250   void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
2251     assert(N == 1 && "Invalid number of operands!");
2252     // The operand is actually a t2_so_imm, but we have its
2253     // negation in the assembly source, so twiddle it here.
2254     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2255     Inst.addOperand(MCOperand::createImm(-(uint32_t)CE->getValue()));
2256   }
2257
2258   void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
2259     assert(N == 1 && "Invalid number of operands!");
2260     // The operand is actually an imm0_4095, but we have its
2261     // negation in the assembly source, so twiddle it here.
2262     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2263     Inst.addOperand(MCOperand::createImm(-(uint32_t)CE->getValue()));
2264   }
2265
2266   void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
2267     if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
2268       Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2));
2269       return;
2270     }
2271
2272     const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
2273     assert(SR && "Unknown value type!");
2274     Inst.addOperand(MCOperand::createExpr(SR));
2275   }
2276
2277   void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
2278     assert(N == 1 && "Invalid number of operands!");
2279     if (isImm()) {
2280       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2281       if (CE) {
2282         Inst.addOperand(MCOperand::createImm(CE->getValue()));
2283         return;
2284       }
2285
2286       const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
2287
2288       assert(SR && "Unknown value type!");
2289       Inst.addOperand(MCOperand::createExpr(SR));
2290       return;
2291     }
2292
2293     assert(isMem()  && "Unknown value type!");
2294     assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
2295     Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue()));
2296   }
2297
2298   void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
2299     assert(N == 1 && "Invalid number of operands!");
2300     Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt())));
2301   }
2302
2303   void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2304     assert(N == 1 && "Invalid number of operands!");
2305     Inst.addOperand(MCOperand::createImm(unsigned(getInstSyncBarrierOpt())));
2306   }
2307
2308   void addTraceSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2309     assert(N == 1 && "Invalid number of operands!");
2310     Inst.addOperand(MCOperand::createImm(unsigned(getTraceSyncBarrierOpt())));
2311   }
2312
2313   void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
2314     assert(N == 1 && "Invalid number of operands!");
2315     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2316   }
2317
2318   void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
2319     assert(N == 1 && "Invalid number of operands!");
2320     int32_t Imm = Memory.OffsetImm->getValue();
2321     Inst.addOperand(MCOperand::createImm(Imm));
2322   }
2323
2324   void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
2325     assert(N == 1 && "Invalid number of operands!");
2326     assert(isImm() && "Not an immediate!");
2327
2328     // If we have an immediate that's not a constant, treat it as a label
2329     // reference needing a fixup.
2330     if (!isa<MCConstantExpr>(getImm())) {
2331       Inst.addOperand(MCOperand::createExpr(getImm()));
2332       return;
2333     }
2334
2335     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2336     int Val = CE->getValue();
2337     Inst.addOperand(MCOperand::createImm(Val));
2338   }
2339
2340   void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2341     assert(N == 2 && "Invalid number of operands!");
2342     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2343     Inst.addOperand(MCOperand::createImm(Memory.Alignment));
2344   }
2345
2346   void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2347     addAlignedMemoryOperands(Inst, N);
2348   }
2349
2350   void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2351     addAlignedMemoryOperands(Inst, N);
2352   }
2353
2354   void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2355     addAlignedMemoryOperands(Inst, N);
2356   }
2357
2358   void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2359     addAlignedMemoryOperands(Inst, N);
2360   }
2361
2362   void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2363     addAlignedMemoryOperands(Inst, N);
2364   }
2365
2366   void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2367     addAlignedMemoryOperands(Inst, N);
2368   }
2369
2370   void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2371     addAlignedMemoryOperands(Inst, N);
2372   }
2373
2374   void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2375     addAlignedMemoryOperands(Inst, N);
2376   }
2377
2378   void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2379     addAlignedMemoryOperands(Inst, N);
2380   }
2381
2382   void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2383     addAlignedMemoryOperands(Inst, N);
2384   }
2385
2386   void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2387     addAlignedMemoryOperands(Inst, N);
2388   }
2389
2390   void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2391     assert(N == 3 && "Invalid number of operands!");
2392     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2393     if (!Memory.OffsetRegNum) {
2394       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2395       // Special case for #-0
2396       if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2397       if (Val < 0) Val = -Val;
2398       Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2399     } else {
2400       // For register offset, we encode the shift type and negation flag
2401       // here.
2402       Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2403                               Memory.ShiftImm, Memory.ShiftType);
2404     }
2405     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2406     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2407     Inst.addOperand(MCOperand::createImm(Val));
2408   }
2409
2410   void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2411     assert(N == 2 && "Invalid number of operands!");
2412     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2413     assert(CE && "non-constant AM2OffsetImm operand!");
2414     int32_t Val = CE->getValue();
2415     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2416     // Special case for #-0
2417     if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2418     if (Val < 0) Val = -Val;
2419     Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2420     Inst.addOperand(MCOperand::createReg(0));
2421     Inst.addOperand(MCOperand::createImm(Val));
2422   }
2423
2424   void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2425     assert(N == 3 && "Invalid number of operands!");
2426     // If we have an immediate that's not a constant, treat it as a label
2427     // reference needing a fixup. If it is a constant, it's something else
2428     // and we reject it.
2429     if (isImm()) {
2430       Inst.addOperand(MCOperand::createExpr(getImm()));
2431       Inst.addOperand(MCOperand::createReg(0));
2432       Inst.addOperand(MCOperand::createImm(0));
2433       return;
2434     }
2435
2436     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2437     if (!Memory.OffsetRegNum) {
2438       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2439       // Special case for #-0
2440       if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2441       if (Val < 0) Val = -Val;
2442       Val = ARM_AM::getAM3Opc(AddSub, Val);
2443     } else {
2444       // For register offset, we encode the shift type and negation flag
2445       // here.
2446       Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2447     }
2448     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2449     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2450     Inst.addOperand(MCOperand::createImm(Val));
2451   }
2452
2453   void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2454     assert(N == 2 && "Invalid number of operands!");
2455     if (Kind == k_PostIndexRegister) {
2456       int32_t Val =
2457         ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2458       Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2459       Inst.addOperand(MCOperand::createImm(Val));
2460       return;
2461     }
2462
2463     // Constant offset.
2464     const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2465     int32_t Val = CE->getValue();
2466     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2467     // Special case for #-0
2468     if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2469     if (Val < 0) Val = -Val;
2470     Val = ARM_AM::getAM3Opc(AddSub, Val);
2471     Inst.addOperand(MCOperand::createReg(0));
2472     Inst.addOperand(MCOperand::createImm(Val));
2473   }
2474
2475   void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2476     assert(N == 2 && "Invalid number of operands!");
2477     // If we have an immediate that's not a constant, treat it as a label
2478     // reference needing a fixup. If it is a constant, it's something else
2479     // and we reject it.
2480     if (isImm()) {
2481       Inst.addOperand(MCOperand::createExpr(getImm()));
2482       Inst.addOperand(MCOperand::createImm(0));
2483       return;
2484     }
2485
2486     // The lower two bits are always zero and as such are not encoded.
2487     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2488     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2489     // Special case for #-0
2490     if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2491     if (Val < 0) Val = -Val;
2492     Val = ARM_AM::getAM5Opc(AddSub, Val);
2493     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2494     Inst.addOperand(MCOperand::createImm(Val));
2495   }
2496
2497   void addAddrMode5FP16Operands(MCInst &Inst, unsigned N) const {
2498     assert(N == 2 && "Invalid number of operands!");
2499     // If we have an immediate that's not a constant, treat it as a label
2500     // reference needing a fixup. If it is a constant, it's something else
2501     // and we reject it.
2502     if (isImm()) {
2503       Inst.addOperand(MCOperand::createExpr(getImm()));
2504       Inst.addOperand(MCOperand::createImm(0));
2505       return;
2506     }
2507
2508     // The lower bit is always zero and as such is not encoded.
2509     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 2 : 0;
2510     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2511     // Special case for #-0
2512     if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2513     if (Val < 0) Val = -Val;
2514     Val = ARM_AM::getAM5FP16Opc(AddSub, Val);
2515     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2516     Inst.addOperand(MCOperand::createImm(Val));
2517   }
2518
2519   void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2520     assert(N == 2 && "Invalid number of operands!");
2521     // If we have an immediate that's not a constant, treat it as a label
2522     // reference needing a fixup. If it is a constant, it's something else
2523     // and we reject it.
2524     if (isImm()) {
2525       Inst.addOperand(MCOperand::createExpr(getImm()));
2526       Inst.addOperand(MCOperand::createImm(0));
2527       return;
2528     }
2529
2530     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2531     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2532     Inst.addOperand(MCOperand::createImm(Val));
2533   }
2534
2535   void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2536     assert(N == 2 && "Invalid number of operands!");
2537     // The lower two bits are always zero and as such are not encoded.
2538     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2539     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2540     Inst.addOperand(MCOperand::createImm(Val));
2541   }
2542
2543   void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2544     assert(N == 2 && "Invalid number of operands!");
2545     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2546     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2547     Inst.addOperand(MCOperand::createImm(Val));
2548   }
2549
2550   void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2551     addMemImm8OffsetOperands(Inst, N);
2552   }
2553
2554   void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2555     addMemImm8OffsetOperands(Inst, N);
2556   }
2557
2558   void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2559     assert(N == 2 && "Invalid number of operands!");
2560     // If this is an immediate, it's a label reference.
2561     if (isImm()) {
2562       addExpr(Inst, getImm());
2563       Inst.addOperand(MCOperand::createImm(0));
2564       return;
2565     }
2566
2567     // Otherwise, it's a normal memory reg+offset.
2568     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2569     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2570     Inst.addOperand(MCOperand::createImm(Val));
2571   }
2572
2573   void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2574     assert(N == 2 && "Invalid number of operands!");
2575     // If this is an immediate, it's a label reference.
2576     if (isImm()) {
2577       addExpr(Inst, getImm());
2578       Inst.addOperand(MCOperand::createImm(0));
2579       return;
2580     }
2581
2582     // Otherwise, it's a normal memory reg+offset.
2583     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2584     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2585     Inst.addOperand(MCOperand::createImm(Val));
2586   }
2587
2588   void addConstPoolAsmImmOperands(MCInst &Inst, unsigned N) const {
2589     assert(N == 1 && "Invalid number of operands!");
2590     // This is container for the immediate that we will create the constant
2591     // pool from
2592     addExpr(Inst, getConstantPoolImm());
2593     return;
2594   }
2595
2596   void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2597     assert(N == 2 && "Invalid number of operands!");
2598     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2599     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2600   }
2601
2602   void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2603     assert(N == 2 && "Invalid number of operands!");
2604     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2605     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2606   }
2607
2608   void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2609     assert(N == 3 && "Invalid number of operands!");
2610     unsigned Val =
2611       ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2612                         Memory.ShiftImm, Memory.ShiftType);
2613     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2614     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2615     Inst.addOperand(MCOperand::createImm(Val));
2616   }
2617
2618   void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2619     assert(N == 3 && "Invalid number of operands!");
2620     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2621     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2622     Inst.addOperand(MCOperand::createImm(Memory.ShiftImm));
2623   }
2624
2625   void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2626     assert(N == 2 && "Invalid number of operands!");
2627     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2628     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2629   }
2630
2631   void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2632     assert(N == 2 && "Invalid number of operands!");
2633     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2634     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2635     Inst.addOperand(MCOperand::createImm(Val));
2636   }
2637
2638   void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2639     assert(N == 2 && "Invalid number of operands!");
2640     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2641     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2642     Inst.addOperand(MCOperand::createImm(Val));
2643   }
2644
2645   void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2646     assert(N == 2 && "Invalid number of operands!");
2647     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2648     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2649     Inst.addOperand(MCOperand::createImm(Val));
2650   }
2651
2652   void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2653     assert(N == 2 && "Invalid number of operands!");
2654     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2655     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2656     Inst.addOperand(MCOperand::createImm(Val));
2657   }
2658
2659   void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2660     assert(N == 1 && "Invalid number of operands!");
2661     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2662     assert(CE && "non-constant post-idx-imm8 operand!");
2663     int Imm = CE->getValue();
2664     bool isAdd = Imm >= 0;
2665     if (Imm == std::numeric_limits<int32_t>::min()) Imm = 0;
2666     Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2667     Inst.addOperand(MCOperand::createImm(Imm));
2668   }
2669
2670   void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2671     assert(N == 1 && "Invalid number of operands!");
2672     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2673     assert(CE && "non-constant post-idx-imm8s4 operand!");
2674     int Imm = CE->getValue();
2675     bool isAdd = Imm >= 0;
2676     if (Imm == std::numeric_limits<int32_t>::min()) Imm = 0;
2677     // Immediate is scaled by 4.
2678     Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2679     Inst.addOperand(MCOperand::createImm(Imm));
2680   }
2681
2682   void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2683     assert(N == 2 && "Invalid number of operands!");
2684     Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2685     Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd));
2686   }
2687
2688   void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2689     assert(N == 2 && "Invalid number of operands!");
2690     Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2691     // The sign, shift type, and shift amount are encoded in a single operand
2692     // using the AM2 encoding helpers.
2693     ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2694     unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2695                                      PostIdxReg.ShiftTy);
2696     Inst.addOperand(MCOperand::createImm(Imm));
2697   }
2698
2699   void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2700     assert(N == 1 && "Invalid number of operands!");
2701     Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask())));
2702   }
2703
2704   void addBankedRegOperands(MCInst &Inst, unsigned N) const {
2705     assert(N == 1 && "Invalid number of operands!");
2706     Inst.addOperand(MCOperand::createImm(unsigned(getBankedReg())));
2707   }
2708
2709   void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2710     assert(N == 1 && "Invalid number of operands!");
2711     Inst.addOperand(MCOperand::createImm(unsigned(getProcIFlags())));
2712   }
2713
2714   void addVecListOperands(MCInst &Inst, unsigned N) const {
2715     assert(N == 1 && "Invalid number of operands!");
2716     Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
2717   }
2718
2719   void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2720     assert(N == 2 && "Invalid number of operands!");
2721     Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
2722     Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex));
2723   }
2724
2725   void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2726     assert(N == 1 && "Invalid number of operands!");
2727     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2728   }
2729
2730   void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2731     assert(N == 1 && "Invalid number of operands!");
2732     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2733   }
2734
2735   void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2736     assert(N == 1 && "Invalid number of operands!");
2737     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2738   }
2739
2740   void addVectorIndex64Operands(MCInst &Inst, unsigned N) const {
2741     assert(N == 1 && "Invalid number of operands!");
2742     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2743   }
2744
2745   void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2746     assert(N == 1 && "Invalid number of operands!");
2747     // The immediate encodes the type of constant as well as the value.
2748     // Mask in that this is an i8 splat.
2749     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2750     Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00));
2751   }
2752
2753   void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2754     assert(N == 1 && "Invalid number of operands!");
2755     // The immediate encodes the type of constant as well as the value.
2756     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2757     unsigned Value = CE->getValue();
2758     Value = ARM_AM::encodeNEONi16splat(Value);
2759     Inst.addOperand(MCOperand::createImm(Value));
2760   }
2761
2762   void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const {
2763     assert(N == 1 && "Invalid number of operands!");
2764     // The immediate encodes the type of constant as well as the value.
2765     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2766     unsigned Value = CE->getValue();
2767     Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff);
2768     Inst.addOperand(MCOperand::createImm(Value));
2769   }
2770
2771   void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2772     assert(N == 1 && "Invalid number of operands!");
2773     // The immediate encodes the type of constant as well as the value.
2774     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2775     unsigned Value = CE->getValue();
2776     Value = ARM_AM::encodeNEONi32splat(Value);
2777     Inst.addOperand(MCOperand::createImm(Value));
2778   }
2779
2780   void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const {
2781     assert(N == 1 && "Invalid number of operands!");
2782     // The immediate encodes the type of constant as well as the value.
2783     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2784     unsigned Value = CE->getValue();
2785     Value = ARM_AM::encodeNEONi32splat(~Value);
2786     Inst.addOperand(MCOperand::createImm(Value));
2787   }
2788
2789   void addNEONi8ReplicateOperands(MCInst &Inst, bool Inv) const {
2790     // The immediate encodes the type of constant as well as the value.
2791     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2792     assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2793             Inst.getOpcode() == ARM::VMOVv16i8) &&
2794           "All instructions that wants to replicate non-zero byte "
2795           "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2796     unsigned Value = CE->getValue();
2797     if (Inv)
2798       Value = ~Value;
2799     unsigned B = Value & 0xff;
2800     B |= 0xe00; // cmode = 0b1110
2801     Inst.addOperand(MCOperand::createImm(B));
2802   }
2803
2804   void addNEONinvi8ReplicateOperands(MCInst &Inst, unsigned N) const {
2805     assert(N == 1 && "Invalid number of operands!");
2806     addNEONi8ReplicateOperands(Inst, true);
2807   }
2808
2809   static unsigned encodeNeonVMOVImmediate(unsigned Value) {
2810     if (Value >= 256 && Value <= 0xffff)
2811       Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2812     else if (Value > 0xffff && Value <= 0xffffff)
2813       Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2814     else if (Value > 0xffffff)
2815       Value = (Value >> 24) | 0x600;
2816     return Value;
2817   }
2818
2819   void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2820     assert(N == 1 && "Invalid number of operands!");
2821     // The immediate encodes the type of constant as well as the value.
2822     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2823     unsigned Value = encodeNeonVMOVImmediate(CE->getValue());
2824     Inst.addOperand(MCOperand::createImm(Value));
2825   }
2826
2827   void addNEONvmovi8ReplicateOperands(MCInst &Inst, unsigned N) const {
2828     assert(N == 1 && "Invalid number of operands!");
2829     addNEONi8ReplicateOperands(Inst, false);
2830   }
2831
2832   void addNEONvmovi16ReplicateOperands(MCInst &Inst, unsigned N) const {
2833     assert(N == 1 && "Invalid number of operands!");
2834     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2835     assert((Inst.getOpcode() == ARM::VMOVv4i16 ||
2836             Inst.getOpcode() == ARM::VMOVv8i16 ||
2837             Inst.getOpcode() == ARM::VMVNv4i16 ||
2838             Inst.getOpcode() == ARM::VMVNv8i16) &&
2839           "All instructions that want to replicate non-zero half-word "
2840           "always must be replaced with V{MOV,MVN}v{4,8}i16.");
2841     uint64_t Value = CE->getValue();
2842     unsigned Elem = Value & 0xffff;
2843     if (Elem >= 256)
2844       Elem = (Elem >> 8) | 0x200;
2845     Inst.addOperand(MCOperand::createImm(Elem));
2846   }
2847
2848   void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2849     assert(N == 1 && "Invalid number of operands!");
2850     // The immediate encodes the type of constant as well as the value.
2851     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2852     unsigned Value = encodeNeonVMOVImmediate(~CE->getValue());
2853     Inst.addOperand(MCOperand::createImm(Value));
2854   }
2855
2856   void addNEONvmovi32ReplicateOperands(MCInst &Inst, unsigned N) const {
2857     assert(N == 1 && "Invalid number of operands!");
2858     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2859     assert((Inst.getOpcode() == ARM::VMOVv2i32 ||
2860             Inst.getOpcode() == ARM::VMOVv4i32 ||
2861             Inst.getOpcode() == ARM::VMVNv2i32 ||
2862             Inst.getOpcode() == ARM::VMVNv4i32) &&
2863           "All instructions that want to replicate non-zero word "
2864           "always must be replaced with V{MOV,MVN}v{2,4}i32.");
2865     uint64_t Value = CE->getValue();
2866     unsigned Elem = encodeNeonVMOVImmediate(Value & 0xffffffff);
2867     Inst.addOperand(MCOperand::createImm(Elem));
2868   }
2869
2870   void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2871     assert(N == 1 && "Invalid number of operands!");
2872     // The immediate encodes the type of constant as well as the value.
2873     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2874     uint64_t Value = CE->getValue();
2875     unsigned Imm = 0;
2876     for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2877       Imm |= (Value & 1) << i;
2878     }
2879     Inst.addOperand(MCOperand::createImm(Imm | 0x1e00));
2880   }
2881
2882   void addComplexRotationEvenOperands(MCInst &Inst, unsigned N) const {
2883     assert(N == 1 && "Invalid number of operands!");
2884     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2885     Inst.addOperand(MCOperand::createImm(CE->getValue() / 90));
2886   }
2887
2888   void addComplexRotationOddOperands(MCInst &Inst, unsigned N) const {
2889     assert(N == 1 && "Invalid number of operands!");
2890     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2891     Inst.addOperand(MCOperand::createImm((CE->getValue() - 90) / 180));
2892   }
2893
2894   void print(raw_ostream &OS) const override;
2895
2896   static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
2897     auto Op = make_unique<ARMOperand>(k_ITCondMask);
2898     Op->ITMask.Mask = Mask;
2899     Op->StartLoc = S;
2900     Op->EndLoc = S;
2901     return Op;
2902   }
2903
2904   static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC,
2905                                                     SMLoc S) {
2906     auto Op = make_unique<ARMOperand>(k_CondCode);
2907     Op->CC.Val = CC;
2908     Op->StartLoc = S;
2909     Op->EndLoc = S;
2910     return Op;
2911   }
2912
2913   static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) {
2914     auto Op = make_unique<ARMOperand>(k_CoprocNum);
2915     Op->Cop.Val = CopVal;
2916     Op->StartLoc = S;
2917     Op->EndLoc = S;
2918     return Op;
2919   }
2920
2921   static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) {
2922     auto Op = make_unique<ARMOperand>(k_CoprocReg);
2923     Op->Cop.Val = CopVal;
2924     Op->StartLoc = S;
2925     Op->EndLoc = S;
2926     return Op;
2927   }
2928
2929   static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S,
2930                                                         SMLoc E) {
2931     auto Op = make_unique<ARMOperand>(k_CoprocOption);
2932     Op->Cop.Val = Val;
2933     Op->StartLoc = S;
2934     Op->EndLoc = E;
2935     return Op;
2936   }
2937
2938   static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {
2939     auto Op = make_unique<ARMOperand>(k_CCOut);
2940     Op->Reg.RegNum = RegNum;
2941     Op->StartLoc = S;
2942     Op->EndLoc = S;
2943     return Op;
2944   }
2945
2946   static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) {
2947     auto Op = make_unique<ARMOperand>(k_Token);
2948     Op->Tok.Data = Str.data();
2949     Op->Tok.Length = Str.size();
2950     Op->StartLoc = S;
2951     Op->EndLoc = S;
2952     return Op;
2953   }
2954
2955   static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
2956                                                SMLoc E) {
2957     auto Op = make_unique<ARMOperand>(k_Register);
2958     Op->Reg.RegNum = RegNum;
2959     Op->StartLoc = S;
2960     Op->EndLoc = E;
2961     return Op;
2962   }
2963
2964   static std::unique_ptr<ARMOperand>
2965   CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2966                         unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
2967                         SMLoc E) {
2968     auto Op = make_unique<ARMOperand>(k_ShiftedRegister);
2969     Op->RegShiftedReg.ShiftTy = ShTy;
2970     Op->RegShiftedReg.SrcReg = SrcReg;
2971     Op->RegShiftedReg.ShiftReg = ShiftReg;
2972     Op->RegShiftedReg.ShiftImm = ShiftImm;
2973     Op->StartLoc = S;
2974     Op->EndLoc = E;
2975     return Op;
2976   }
2977
2978   static std::unique_ptr<ARMOperand>
2979   CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2980                          unsigned ShiftImm, SMLoc S, SMLoc E) {
2981     auto Op = make_unique<ARMOperand>(k_ShiftedImmediate);
2982     Op->RegShiftedImm.ShiftTy = ShTy;
2983     Op->RegShiftedImm.SrcReg = SrcReg;
2984     Op->RegShiftedImm.ShiftImm = ShiftImm;
2985     Op->StartLoc = S;
2986     Op->EndLoc = E;
2987     return Op;
2988   }
2989
2990   static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
2991                                                       SMLoc S, SMLoc E) {
2992     auto Op = make_unique<ARMOperand>(k_ShifterImmediate);
2993     Op->ShifterImm.isASR = isASR;
2994     Op->ShifterImm.Imm = Imm;
2995     Op->StartLoc = S;
2996     Op->EndLoc = E;
2997     return Op;
2998   }
2999
3000   static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S,
3001                                                   SMLoc E) {
3002     auto Op = make_unique<ARMOperand>(k_RotateImmediate);
3003     Op->RotImm.Imm = Imm;
3004     Op->StartLoc = S;
3005     Op->EndLoc = E;
3006     return Op;
3007   }
3008
3009   static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot,
3010                                                   SMLoc S, SMLoc E) {
3011     auto Op = make_unique<ARMOperand>(k_ModifiedImmediate);
3012     Op->ModImm.Bits = Bits;
3013     Op->ModImm.Rot = Rot;
3014     Op->StartLoc = S;
3015     Op->EndLoc = E;
3016     return Op;
3017   }
3018
3019   static std::unique_ptr<ARMOperand>
3020   CreateConstantPoolImm(const MCExpr *Val, SMLoc S, SMLoc E) {
3021     auto Op = make_unique<ARMOperand>(k_ConstantPoolImmediate);
3022     Op->Imm.Val = Val;
3023     Op->StartLoc = S;
3024     Op->EndLoc = E;
3025     return Op;
3026   }
3027
3028   static std::unique_ptr<ARMOperand>
3029   CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
3030     auto Op = make_unique<ARMOperand>(k_BitfieldDescriptor);
3031     Op->Bitfield.LSB = LSB;
3032     Op->Bitfield.Width = Width;
3033     Op->StartLoc = S;
3034     Op->EndLoc = E;
3035     return Op;
3036   }
3037
3038   static std::unique_ptr<ARMOperand>
3039   CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
3040                 SMLoc StartLoc, SMLoc EndLoc) {
3041     assert(Regs.size() > 0 && "RegList contains no registers?");
3042     KindTy Kind = k_RegisterList;
3043
3044     if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
3045       Kind = k_DPRRegisterList;
3046     else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
3047              contains(Regs.front().second))
3048       Kind = k_SPRRegisterList;
3049
3050     // Sort based on the register encoding values.
3051     array_pod_sort(Regs.begin(), Regs.end());
3052
3053     auto Op = make_unique<ARMOperand>(Kind);
3054     for (SmallVectorImpl<std::pair<unsigned, unsigned>>::const_iterator
3055            I = Regs.begin(), E = Regs.end(); I != E; ++I)
3056       Op->Registers.push_back(I->second);
3057     Op->StartLoc = StartLoc;
3058     Op->EndLoc = EndLoc;
3059     return Op;
3060   }
3061
3062   static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,
3063                                                       unsigned Count,
3064                                                       bool isDoubleSpaced,
3065                                                       SMLoc S, SMLoc E) {
3066     auto Op = make_unique<ARMOperand>(k_VectorList);
3067     Op->VectorList.RegNum = RegNum;
3068     Op->VectorList.Count = Count;
3069     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3070     Op->StartLoc = S;
3071     Op->EndLoc = E;
3072     return Op;
3073   }
3074
3075   static std::unique_ptr<ARMOperand>
3076   CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
3077                            SMLoc S, SMLoc E) {
3078     auto Op = make_unique<ARMOperand>(k_VectorListAllLanes);
3079     Op->VectorList.RegNum = RegNum;
3080     Op->VectorList.Count = Count;
3081     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3082     Op->StartLoc = S;
3083     Op->EndLoc = E;
3084     return Op;
3085   }
3086
3087   static std::unique_ptr<ARMOperand>
3088   CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
3089                           bool isDoubleSpaced, SMLoc S, SMLoc E) {
3090     auto Op = make_unique<ARMOperand>(k_VectorListIndexed);
3091     Op->VectorList.RegNum = RegNum;
3092     Op->VectorList.Count = Count;
3093     Op->VectorList.LaneIndex = Index;
3094     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3095     Op->StartLoc = S;
3096     Op->EndLoc = E;
3097     return Op;
3098   }
3099
3100   static std::unique_ptr<ARMOperand>
3101   CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
3102     auto Op = make_unique<ARMOperand>(k_VectorIndex);
3103     Op->VectorIndex.Val = Idx;
3104     Op->StartLoc = S;
3105     Op->EndLoc = E;
3106     return Op;
3107   }
3108
3109   static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
3110                                                SMLoc E) {
3111     auto Op = make_unique<ARMOperand>(k_Immediate);
3112     Op->Imm.Val = Val;
3113     Op->StartLoc = S;
3114     Op->EndLoc = E;
3115     return Op;
3116   }
3117
3118   static std::unique_ptr<ARMOperand>
3119   CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
3120             unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
3121             unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
3122             SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
3123     auto Op = make_unique<ARMOperand>(k_Memory);
3124     Op->Memory.BaseRegNum = BaseRegNum;
3125     Op->Memory.OffsetImm = OffsetImm;
3126     Op->Memory.OffsetRegNum = OffsetRegNum;
3127     Op->Memory.ShiftType = ShiftType;
3128     Op->Memory.ShiftImm = ShiftImm;
3129     Op->Memory.Alignment = Alignment;
3130     Op->Memory.isNegative = isNegative;
3131     Op->StartLoc = S;
3132     Op->EndLoc = E;
3133     Op->AlignmentLoc = AlignmentLoc;
3134     return Op;
3135   }
3136
3137   static std::unique_ptr<ARMOperand>
3138   CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
3139                    unsigned ShiftImm, SMLoc S, SMLoc E) {
3140     auto Op = make_unique<ARMOperand>(k_PostIndexRegister);
3141     Op->PostIdxReg.RegNum = RegNum;
3142     Op->PostIdxReg.isAdd = isAdd;
3143     Op->PostIdxReg.ShiftTy = ShiftTy;
3144     Op->PostIdxReg.ShiftImm = ShiftImm;
3145     Op->StartLoc = S;
3146     Op->EndLoc = E;
3147     return Op;
3148   }
3149
3150   static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt,
3151                                                          SMLoc S) {
3152     auto Op = make_unique<ARMOperand>(k_MemBarrierOpt);
3153     Op->MBOpt.Val = Opt;
3154     Op->StartLoc = S;
3155     Op->EndLoc = S;
3156     return Op;
3157   }
3158
3159   static std::unique_ptr<ARMOperand>
3160   CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) {
3161     auto Op = make_unique<ARMOperand>(k_InstSyncBarrierOpt);
3162     Op->ISBOpt.Val = Opt;
3163     Op->StartLoc = S;
3164     Op->EndLoc = S;
3165     return Op;
3166   }
3167
3168   static std::unique_ptr<ARMOperand>
3169   CreateTraceSyncBarrierOpt(ARM_TSB::TraceSyncBOpt Opt, SMLoc S) {
3170     auto Op = make_unique<ARMOperand>(k_TraceSyncBarrierOpt);
3171     Op->TSBOpt.Val = Opt;
3172     Op->StartLoc = S;
3173     Op->EndLoc = S;
3174     return Op;
3175   }
3176
3177   static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags,
3178                                                       SMLoc S) {
3179     auto Op = make_unique<ARMOperand>(k_ProcIFlags);
3180     Op->IFlags.Val = IFlags;
3181     Op->StartLoc = S;
3182     Op->EndLoc = S;
3183     return Op;
3184   }
3185
3186   static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) {
3187     auto Op = make_unique<ARMOperand>(k_MSRMask);
3188     Op->MMask.Val = MMask;
3189     Op->StartLoc = S;
3190     Op->EndLoc = S;
3191     return Op;
3192   }
3193
3194   static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) {
3195     auto Op = make_unique<ARMOperand>(k_BankedReg);
3196     Op->BankedReg.Val = Reg;
3197     Op->StartLoc = S;
3198     Op->EndLoc = S;
3199     return Op;
3200   }
3201 };
3202
3203 } // end anonymous namespace.
3204
3205 void ARMOperand::print(raw_ostream &OS) const {
3206   switch (Kind) {
3207   case k_CondCode:
3208     OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
3209     break;
3210   case k_CCOut:
3211     OS << "<ccout " << getReg() << ">";
3212     break;
3213   case k_ITCondMask: {
3214     static const char *const MaskStr[] = {
3215       "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
3216       "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
3217     };
3218     assert((ITMask.Mask & 0xf) == ITMask.Mask);
3219     OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
3220     break;
3221   }
3222   case k_CoprocNum:
3223     OS << "<coprocessor number: " << getCoproc() << ">";
3224     break;
3225   case k_CoprocReg:
3226     OS << "<coprocessor register: " << getCoproc() << ">";
3227     break;
3228   case k_CoprocOption:
3229     OS << "<coprocessor option: " << CoprocOption.Val << ">";
3230     break;
3231   case k_MSRMask:
3232     OS << "<mask: " << getMSRMask() << ">";
3233     break;
3234   case k_BankedReg:
3235     OS << "<banked reg: " << getBankedReg() << ">";
3236     break;
3237   case k_Immediate:
3238     OS << *getImm();
3239     break;
3240   case k_MemBarrierOpt:
3241     OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
3242     break;
3243   case k_InstSyncBarrierOpt:
3244     OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
3245     break;
3246   case k_TraceSyncBarrierOpt:
3247     OS << "<ARM_TSB::" << TraceSyncBOptToString(getTraceSyncBarrierOpt()) << ">";
3248     break;
3249   case k_Memory:
3250     OS << "<memory "
3251        << " base:" << Memory.BaseRegNum;
3252     OS << ">";
3253     break;
3254   case k_PostIndexRegister:
3255     OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
3256        << PostIdxReg.RegNum;
3257     if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
3258       OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
3259          << PostIdxReg.ShiftImm;
3260     OS << ">";
3261     break;
3262   case k_ProcIFlags: {
3263     OS << "<ARM_PROC::";
3264     unsigned IFlags = getProcIFlags();
3265     for (int i=2; i >= 0; --i)
3266       if (IFlags & (1 << i))
3267         OS << ARM_PROC::IFlagsToString(1 << i);
3268     OS << ">";
3269     break;
3270   }
3271   case k_Register:
3272     OS << "<register " << getReg() << ">";
3273     break;
3274   case k_ShifterImmediate:
3275     OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
3276        << " #" << ShifterImm.Imm << ">";
3277     break;
3278   case k_ShiftedRegister:
3279     OS << "<so_reg_reg "
3280        << RegShiftedReg.SrcReg << " "
3281        << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
3282        << " " << RegShiftedReg.ShiftReg << ">";
3283     break;
3284   case k_ShiftedImmediate:
3285     OS << "<so_reg_imm "
3286        << RegShiftedImm.SrcReg << " "
3287        << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
3288        << " #" << RegShiftedImm.ShiftImm << ">";
3289     break;
3290   case k_RotateImmediate:
3291     OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
3292     break;
3293   case k_ModifiedImmediate:
3294     OS << "<mod_imm #" << ModImm.Bits << ", #"
3295        <<  ModImm.Rot << ")>";
3296     break;
3297   case k_ConstantPoolImmediate:
3298     OS << "<constant_pool_imm #" << *getConstantPoolImm();
3299     break;
3300   case k_BitfieldDescriptor:
3301     OS << "<bitfield " << "lsb: " << Bitfield.LSB
3302        << ", width: " << Bitfield.Width << ">";
3303     break;
3304   case k_RegisterList:
3305   case k_DPRRegisterList:
3306   case k_SPRRegisterList: {
3307     OS << "<register_list ";
3308
3309     const SmallVectorImpl<unsigned> &RegList = getRegList();
3310     for (SmallVectorImpl<unsigned>::const_iterator
3311            I = RegList.begin(), E = RegList.end(); I != E; ) {
3312       OS << *I;
3313       if (++I < E) OS << ", ";
3314     }
3315
3316     OS << ">";
3317     break;
3318   }
3319   case k_VectorList:
3320     OS << "<vector_list " << VectorList.Count << " * "
3321        << VectorList.RegNum << ">";
3322     break;
3323   case k_VectorListAllLanes:
3324     OS << "<vector_list(all lanes) " << VectorList.Count << " * "
3325        << VectorList.RegNum << ">";
3326     break;
3327   case k_VectorListIndexed:
3328     OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
3329        << VectorList.Count << " * " << VectorList.RegNum << ">";
3330     break;
3331   case k_Token:
3332     OS << "'" << getToken() << "'";
3333     break;
3334   case k_VectorIndex:
3335     OS << "<vectorindex " << getVectorIndex() << ">";
3336     break;
3337   }
3338 }
3339
3340 /// @name Auto-generated Match Functions
3341 /// {
3342
3343 static unsigned MatchRegisterName(StringRef Name);
3344
3345 /// }
3346
3347 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
3348                                  SMLoc &StartLoc, SMLoc &EndLoc) {
3349   const AsmToken &Tok = getParser().getTok();
3350   StartLoc = Tok.getLoc();
3351   EndLoc = Tok.getEndLoc();
3352   RegNo = tryParseRegister();
3353
3354   return (RegNo == (unsigned)-1);
3355 }
3356
3357 /// Try to parse a register name.  The token must be an Identifier when called,
3358 /// and if it is a register name the token is eaten and the register number is
3359 /// returned.  Otherwise return -1.
3360 int ARMAsmParser::tryParseRegister() {
3361   MCAsmParser &Parser = getParser();
3362   const AsmToken &Tok = Parser.getTok();
3363   if (Tok.isNot(AsmToken::Identifier)) return -1;
3364
3365   std::string lowerCase = Tok.getString().lower();
3366   unsigned RegNum = MatchRegisterName(lowerCase);
3367   if (!RegNum) {
3368     RegNum = StringSwitch<unsigned>(lowerCase)
3369       .Case("r13", ARM::SP)
3370       .Case("r14", ARM::LR)
3371       .Case("r15", ARM::PC)
3372       .Case("ip", ARM::R12)
3373       // Additional register name aliases for 'gas' compatibility.
3374       .Case("a1", ARM::R0)
3375       .Case("a2", ARM::R1)
3376       .Case("a3", ARM::R2)
3377       .Case("a4", ARM::R3)
3378       .Case("v1", ARM::R4)
3379       .Case("v2", ARM::R5)
3380       .Case("v3", ARM::R6)
3381       .Case("v4", ARM::R7)
3382       .Case("v5", ARM::R8)
3383       .Case("v6", ARM::R9)
3384       .Case("v7", ARM::R10)
3385       .Case("v8", ARM::R11)
3386       .Case("sb", ARM::R9)
3387       .Case("sl", ARM::R10)
3388       .Case("fp", ARM::R11)
3389       .Default(0);
3390   }
3391   if (!RegNum) {
3392     // Check for aliases registered via .req. Canonicalize to lower case.
3393     // That's more consistent since register names are case insensitive, and
3394     // it's how the original entry was passed in from MC/MCParser/AsmParser.
3395     StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
3396     // If no match, return failure.
3397     if (Entry == RegisterReqs.end())
3398       return -1;
3399     Parser.Lex(); // Eat identifier token.
3400     return Entry->getValue();
3401   }
3402
3403   // Some FPUs only have 16 D registers, so D16-D31 are invalid
3404   if (hasD16() && RegNum >= ARM::D16 && RegNum <= ARM::D31)
3405     return -1;
3406
3407   Parser.Lex(); // Eat identifier token.
3408
3409   return RegNum;
3410 }
3411
3412 // Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
3413 // If a recoverable error occurs, return 1. If an irrecoverable error
3414 // occurs, return -1. An irrecoverable error is one where tokens have been
3415 // consumed in the process of trying to parse the shifter (i.e., when it is
3416 // indeed a shifter operand, but malformed).
3417 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
3418   MCAsmParser &Parser = getParser();
3419   SMLoc S = Parser.getTok().getLoc();
3420   const AsmToken &Tok = Parser.getTok();
3421   if (Tok.isNot(AsmToken::Identifier))
3422     return -1;
3423
3424   std::string lowerCase = Tok.getString().lower();
3425   ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
3426       .Case("asl", ARM_AM::lsl)
3427       .Case("lsl", ARM_AM::lsl)
3428       .Case("lsr", ARM_AM::lsr)
3429       .Case("asr", ARM_AM::asr)
3430       .Case("ror", ARM_AM::ror)
3431       .Case("rrx", ARM_AM::rrx)
3432       .Default(ARM_AM::no_shift);
3433
3434   if (ShiftTy == ARM_AM::no_shift)
3435     return 1;
3436
3437   Parser.Lex(); // Eat the operator.
3438
3439   // The source register for the shift has already been added to the
3440   // operand list, so we need to pop it off and combine it into the shifted
3441   // register operand instead.
3442   std::unique_ptr<ARMOperand> PrevOp(
3443       (ARMOperand *)Operands.pop_back_val().release());
3444   if (!PrevOp->isReg())
3445     return Error(PrevOp->getStartLoc(), "shift must be of a register");
3446   int SrcReg = PrevOp->getReg();
3447
3448   SMLoc EndLoc;
3449   int64_t Imm = 0;
3450   int ShiftReg = 0;
3451   if (ShiftTy == ARM_AM::rrx) {
3452     // RRX Doesn't have an explicit shift amount. The encoder expects
3453     // the shift register to be the same as the source register. Seems odd,
3454     // but OK.
3455     ShiftReg = SrcReg;
3456   } else {
3457     // Figure out if this is shifted by a constant or a register (for non-RRX).
3458     if (Parser.getTok().is(AsmToken::Hash) ||
3459         Parser.getTok().is(AsmToken::Dollar)) {
3460       Parser.Lex(); // Eat hash.
3461       SMLoc ImmLoc = Parser.getTok().getLoc();
3462       const MCExpr *ShiftExpr = nullptr;
3463       if (getParser().parseExpression(ShiftExpr, EndLoc)) {
3464         Error(ImmLoc, "invalid immediate shift value");
3465         return -1;
3466       }
3467       // The expression must be evaluatable as an immediate.
3468       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
3469       if (!CE) {
3470         Error(ImmLoc, "invalid immediate shift value");
3471         return -1;
3472       }
3473       // Range check the immediate.
3474       // lsl, ror: 0 <= imm <= 31
3475       // lsr, asr: 0 <= imm <= 32
3476       Imm = CE->getValue();
3477       if (Imm < 0 ||
3478           ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
3479           ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
3480         Error(ImmLoc, "immediate shift value out of range");
3481         return -1;
3482       }
3483       // shift by zero is a nop. Always send it through as lsl.
3484       // ('as' compatibility)
3485       if (Imm == 0)
3486         ShiftTy = ARM_AM::lsl;
3487     } else if (Parser.getTok().is(AsmToken::Identifier)) {
3488       SMLoc L = Parser.getTok().getLoc();
3489       EndLoc = Parser.getTok().getEndLoc();
3490       ShiftReg = tryParseRegister();
3491       if (ShiftReg == -1) {
3492         Error(L, "expected immediate or register in shift operand");
3493         return -1;
3494       }
3495     } else {
3496       Error(Parser.getTok().getLoc(),
3497             "expected immediate or register in shift operand");
3498       return -1;
3499     }
3500   }
3501
3502   if (ShiftReg && ShiftTy != ARM_AM::rrx)
3503     Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
3504                                                          ShiftReg, Imm,
3505                                                          S, EndLoc));
3506   else
3507     Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
3508                                                           S, EndLoc));
3509
3510   return 0;
3511 }
3512
3513 /// Try to parse a register name.  The token must be an Identifier when called.
3514 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
3515 /// if there is a "writeback". 'true' if it's not a register.
3516 ///
3517 /// TODO this is likely to change to allow different register types and or to
3518 /// parse for a specific register type.
3519 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
3520   MCAsmParser &Parser = getParser();
3521   SMLoc RegStartLoc = Parser.getTok().getLoc();
3522   SMLoc RegEndLoc = Parser.getTok().getEndLoc();
3523   int RegNo = tryParseRegister();
3524   if (RegNo == -1)
3525     return true;
3526
3527   Operands.push_back(ARMOperand::CreateReg(RegNo, RegStartLoc, RegEndLoc));
3528
3529   const AsmToken &ExclaimTok = Parser.getTok();
3530   if (ExclaimTok.is(AsmToken::Exclaim)) {
3531     Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
3532                                                ExclaimTok.getLoc()));
3533     Parser.Lex(); // Eat exclaim token
3534     return false;
3535   }
3536
3537   // Also check for an index operand. This is only legal for vector registers,
3538   // but that'll get caught OK in operand matching, so we don't need to
3539   // explicitly filter everything else out here.
3540   if (Parser.getTok().is(AsmToken::LBrac)) {
3541     SMLoc SIdx = Parser.getTok().getLoc();
3542     Parser.Lex(); // Eat left bracket token.
3543
3544     const MCExpr *ImmVal;
3545     if (getParser().parseExpression(ImmVal))
3546       return true;
3547     const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
3548     if (!MCE)
3549       return TokError("immediate value expected for vector index");
3550
3551     if (Parser.getTok().isNot(AsmToken::RBrac))
3552       return Error(Parser.getTok().getLoc(), "']' expected");
3553
3554     SMLoc E = Parser.getTok().getEndLoc();
3555     Parser.Lex(); // Eat right bracket token.
3556
3557     Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
3558                                                      SIdx, E,
3559                                                      getContext()));
3560   }
3561
3562   return false;
3563 }
3564
3565 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
3566 /// instruction with a symbolic operand name.
3567 /// We accept "crN" syntax for GAS compatibility.
3568 /// <operand-name> ::= <prefix><number>
3569 /// If CoprocOp is 'c', then:
3570 ///   <prefix> ::= c | cr
3571 /// If CoprocOp is 'p', then :
3572 ///   <prefix> ::= p
3573 /// <number> ::= integer in range [0, 15]
3574 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
3575   // Use the same layout as the tablegen'erated register name matcher. Ugly,
3576   // but efficient.
3577   if (Name.size() < 2 || Name[0] != CoprocOp)
3578     return -1;
3579   Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front();
3580
3581   switch (Name.size()) {
3582   default: return -1;
3583   case 1:
3584     switch (Name[0]) {
3585     default:  return -1;
3586     case '0': return 0;
3587     case '1': return 1;
3588     case '2': return 2;
3589     case '3': return 3;
3590     case '4': return 4;
3591     case '5': return 5;
3592     case '6': return 6;
3593     case '7': return 7;
3594     case '8': return 8;
3595     case '9': return 9;
3596     }
3597   case 2:
3598     if (Name[0] != '1')
3599       return -1;
3600     switch (Name[1]) {
3601     default:  return -1;
3602     // CP10 and CP11 are VFP/NEON and so vector instructions should be used.
3603     // However, old cores (v5/v6) did use them in that way.
3604     case '0': return 10;
3605     case '1': return 11;
3606     case '2': return 12;
3607     case '3': return 13;
3608     case '4': return 14;
3609     case '5': return 15;
3610     }
3611   }
3612 }
3613
3614 /// parseITCondCode - Try to parse a condition code for an IT instruction.
3615 OperandMatchResultTy
3616 ARMAsmParser::parseITCondCode(OperandVector &Operands) {
3617   MCAsmParser &Parser = getParser();
3618   SMLoc S = Parser.getTok().getLoc();
3619   const AsmToken &Tok = Parser.getTok();
3620   if (!Tok.is(AsmToken::Identifier))
3621     return MatchOperand_NoMatch;
3622   unsigned CC = ARMCondCodeFromString(Tok.getString());
3623   if (CC == ~0U)
3624     return MatchOperand_NoMatch;
3625   Parser.Lex(); // Eat the token.
3626
3627   Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
3628
3629   return MatchOperand_Success;
3630 }
3631
3632 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3633 /// token must be an Identifier when called, and if it is a coprocessor
3634 /// number, the token is eaten and the operand is added to the operand list.
3635 OperandMatchResultTy
3636 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
3637   MCAsmParser &Parser = getParser();
3638   SMLoc S = Parser.getTok().getLoc();
3639   const AsmToken &Tok = Parser.getTok();
3640   if (Tok.isNot(AsmToken::Identifier))
3641     return MatchOperand_NoMatch;
3642
3643   int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3644   if (Num == -1)
3645     return MatchOperand_NoMatch;
3646   // ARMv7 and v8 don't allow cp10/cp11 due to VFP/NEON specific instructions
3647   if ((hasV7Ops() || hasV8Ops()) && (Num == 10 || Num == 11))
3648     return MatchOperand_NoMatch;
3649
3650   Parser.Lex(); // Eat identifier token.
3651   Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3652   return MatchOperand_Success;
3653 }
3654
3655 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3656 /// token must be an Identifier when called, and if it is a coprocessor
3657 /// number, the token is eaten and the operand is added to the operand list.
3658 OperandMatchResultTy
3659 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
3660   MCAsmParser &Parser = getParser();
3661   SMLoc S = Parser.getTok().getLoc();
3662   const AsmToken &Tok = Parser.getTok();
3663   if (Tok.isNot(AsmToken::Identifier))
3664     return MatchOperand_NoMatch;
3665
3666   int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3667   if (Reg == -1)
3668     return MatchOperand_NoMatch;
3669
3670   Parser.Lex(); // Eat identifier token.
3671   Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3672   return MatchOperand_Success;
3673 }
3674
3675 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3676 /// coproc_option : '{' imm0_255 '}'
3677 OperandMatchResultTy
3678 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
3679   MCAsmParser &Parser = getParser();
3680   SMLoc S = Parser.getTok().getLoc();
3681
3682   // If this isn't a '{', this isn't a coprocessor immediate operand.
3683   if (Parser.getTok().isNot(AsmToken::LCurly))
3684     return MatchOperand_NoMatch;
3685   Parser.Lex(); // Eat the '{'
3686
3687   const MCExpr *Expr;
3688   SMLoc Loc = Parser.getTok().getLoc();
3689   if (getParser().parseExpression(Expr)) {
3690     Error(Loc, "illegal expression");
3691     return MatchOperand_ParseFail;
3692   }
3693   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3694   if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3695     Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3696     return MatchOperand_ParseFail;
3697   }
3698   int Val = CE->getValue();
3699
3700   // Check for and consume the closing '}'
3701   if (Parser.getTok().isNot(AsmToken::RCurly))
3702     return MatchOperand_ParseFail;
3703   SMLoc E = Parser.getTok().getEndLoc();
3704   Parser.Lex(); // Eat the '}'
3705
3706   Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3707   return MatchOperand_Success;
3708 }
3709
3710 // For register list parsing, we need to map from raw GPR register numbering
3711 // to the enumeration values. The enumeration values aren't sorted by
3712 // register number due to our using "sp", "lr" and "pc" as canonical names.
3713 static unsigned getNextRegister(unsigned Reg) {
3714   // If this is a GPR, we need to do it manually, otherwise we can rely
3715   // on the sort ordering of the enumeration since the other reg-classes
3716   // are sane.
3717   if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3718     return Reg + 1;
3719   switch(Reg) {
3720   default: llvm_unreachable("Invalid GPR number!");
3721   case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
3722   case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
3723   case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
3724   case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
3725   case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
3726   case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3727   case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
3728   case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
3729   }
3730 }
3731
3732 /// Parse a register list.
3733 bool ARMAsmParser::parseRegisterList(OperandVector &Operands) {
3734   MCAsmParser &Parser = getParser();
3735   if (Parser.getTok().isNot(AsmToken::LCurly))
3736     return TokError("Token is not a Left Curly Brace");
3737   SMLoc S = Parser.getTok().getLoc();
3738   Parser.Lex(); // Eat '{' token.
3739   SMLoc RegLoc = Parser.getTok().getLoc();
3740
3741   // Check the first register in the list to see what register class
3742   // this is a list of.
3743   int Reg = tryParseRegister();
3744   if (Reg == -1)
3745     return Error(RegLoc, "register expected");
3746
3747   // The reglist instructions have at most 16 registers, so reserve
3748   // space for that many.
3749   int EReg = 0;
3750   SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3751
3752   // Allow Q regs and just interpret them as the two D sub-registers.
3753   if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3754     Reg = getDRegFromQReg(Reg);
3755     EReg = MRI->getEncodingValue(Reg);
3756     Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3757     ++Reg;
3758   }
3759   const MCRegisterClass *RC;
3760   if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3761     RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3762   else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3763     RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3764   else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3765     RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3766   else
3767     return Error(RegLoc, "invalid register in register list");
3768
3769   // Store the register.
3770   EReg = MRI->getEncodingValue(Reg);
3771   Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3772
3773   // This starts immediately after the first register token in the list,
3774   // so we can see either a comma or a minus (range separator) as a legal
3775   // next token.
3776   while (Parser.getTok().is(AsmToken::Comma) ||
3777          Parser.getTok().is(AsmToken::Minus)) {
3778     if (Parser.getTok().is(AsmToken::Minus)) {
3779       Parser.Lex(); // Eat the minus.
3780       SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3781       int EndReg = tryParseRegister();
3782       if (EndReg == -1)
3783         return Error(AfterMinusLoc, "register expected");
3784       // Allow Q regs and just interpret them as the two D sub-registers.
3785       if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3786         EndReg = getDRegFromQReg(EndReg) + 1;
3787       // If the register is the same as the start reg, there's nothing
3788       // more to do.
3789       if (Reg == EndReg)
3790         continue;
3791       // The register must be in the same register class as the first.
3792       if (!RC->contains(EndReg))
3793         return Error(AfterMinusLoc, "invalid register in register list");
3794       // Ranges must go from low to high.
3795       if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3796         return Error(AfterMinusLoc, "bad range in register list");
3797
3798       // Add all the registers in the range to the register list.
3799       while (Reg != EndReg) {
3800         Reg = getNextRegister(Reg);
3801         EReg = MRI->getEncodingValue(Reg);
3802         Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3803       }
3804       continue;
3805     }
3806     Parser.Lex(); // Eat the comma.
3807     RegLoc = Parser.getTok().getLoc();
3808     int OldReg = Reg;
3809     const AsmToken RegTok = Parser.getTok();
3810     Reg = tryParseRegister();
3811     if (Reg == -1)
3812       return Error(RegLoc, "register expected");
3813     // Allow Q regs and just interpret them as the two D sub-registers.
3814     bool isQReg = false;
3815     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3816       Reg = getDRegFromQReg(Reg);
3817       isQReg = true;
3818     }
3819     // The register must be in the same register class as the first.
3820     if (!RC->contains(Reg))
3821       return Error(RegLoc, "invalid register in register list");
3822     // List must be monotonically increasing.
3823     if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3824       if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3825         Warning(RegLoc, "register list not in ascending order");
3826       else
3827         return Error(RegLoc, "register list not in ascending order");
3828     }
3829     if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3830       Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3831               ") in register list");
3832       continue;
3833     }
3834     // VFP register lists must also be contiguous.
3835     if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3836         Reg != OldReg + 1)
3837       return Error(RegLoc, "non-contiguous register range");
3838     EReg = MRI->getEncodingValue(Reg);
3839     Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3840     if (isQReg) {
3841       EReg = MRI->getEncodingValue(++Reg);
3842       Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3843     }
3844   }
3845
3846   if (Parser.getTok().isNot(AsmToken::RCurly))
3847     return Error(Parser.getTok().getLoc(), "'}' expected");
3848   SMLoc E = Parser.getTok().getEndLoc();
3849   Parser.Lex(); // Eat '}' token.
3850
3851   // Push the register list operand.
3852   Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3853
3854   // The ARM system instruction variants for LDM/STM have a '^' token here.
3855   if (Parser.getTok().is(AsmToken::Caret)) {
3856     Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3857     Parser.Lex(); // Eat '^' token.
3858   }
3859
3860   return false;
3861 }
3862
3863 // Helper function to parse the lane index for vector lists.
3864 OperandMatchResultTy ARMAsmParser::
3865 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3866   MCAsmParser &Parser = getParser();
3867   Index = 0; // Always return a defined index value.
3868   if (Parser.getTok().is(AsmToken::LBrac)) {
3869     Parser.Lex(); // Eat the '['.
3870     if (Parser.getTok().is(AsmToken::RBrac)) {
3871       // "Dn[]" is the 'all lanes' syntax.
3872       LaneKind = AllLanes;
3873       EndLoc = Parser.getTok().getEndLoc();
3874       Parser.Lex(); // Eat the ']'.
3875       return MatchOperand_Success;
3876     }
3877
3878     // There's an optional '#' token here. Normally there wouldn't be, but
3879     // inline assemble puts one in, and it's friendly to accept that.
3880     if (Parser.getTok().is(AsmToken::Hash))
3881       Parser.Lex(); // Eat '#' or '$'.
3882
3883     const MCExpr *LaneIndex;
3884     SMLoc Loc = Parser.getTok().getLoc();
3885     if (getParser().parseExpression(LaneIndex)) {
3886       Error(Loc, "illegal expression");
3887       return MatchOperand_ParseFail;
3888     }
3889     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3890     if (!CE) {
3891       Error(Loc, "lane index must be empty or an integer");
3892       return MatchOperand_ParseFail;
3893     }
3894     if (Parser.getTok().isNot(AsmToken::RBrac)) {
3895       Error(Parser.getTok().getLoc(), "']' expected");
3896       return MatchOperand_ParseFail;
3897     }
3898     EndLoc = Parser.getTok().getEndLoc();
3899     Parser.Lex(); // Eat the ']'.
3900     int64_t Val = CE->getValue();
3901
3902     // FIXME: Make this range check context sensitive for .8, .16, .32.
3903     if (Val < 0 || Val > 7) {
3904       Error(Parser.getTok().getLoc(), "lane index out of range");
3905       return MatchOperand_ParseFail;
3906     }
3907     Index = Val;
3908     LaneKind = IndexedLane;
3909     return MatchOperand_Success;
3910   }
3911   LaneKind = NoLanes;
3912   return MatchOperand_Success;
3913 }
3914
3915 // parse a vector register list
3916 OperandMatchResultTy
3917 ARMAsmParser::parseVectorList(OperandVector &Operands) {
3918   MCAsmParser &Parser = getParser();
3919   VectorLaneTy LaneKind;
3920   unsigned LaneIndex;
3921   SMLoc S = Parser.getTok().getLoc();
3922   // As an extension (to match gas), support a plain D register or Q register
3923   // (without encosing curly braces) as a single or double entry list,
3924   // respectively.
3925   if (Parser.getTok().is(AsmToken::Identifier)) {
3926     SMLoc E = Parser.getTok().getEndLoc();
3927     int Reg = tryParseRegister();
3928     if (Reg == -1)
3929       return MatchOperand_NoMatch;
3930     if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3931       OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3932       if (Res != MatchOperand_Success)
3933         return Res;
3934       switch (LaneKind) {
3935       case NoLanes:
3936         Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3937         break;
3938       case AllLanes:
3939         Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3940                                                                 S, E));
3941         break;
3942       case IndexedLane:
3943         Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3944                                                                LaneIndex,
3945                                                                false, S, E));
3946         break;
3947       }
3948       return MatchOperand_Success;
3949     }
3950     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3951       Reg = getDRegFromQReg(Reg);
3952       OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3953       if (Res != MatchOperand_Success)
3954         return Res;
3955       switch (LaneKind) {
3956       case NoLanes:
3957         Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3958                                    &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3959         Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3960         break;
3961       case AllLanes:
3962         Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3963                                    &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3964         Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3965                                                                 S, E));
3966         break;
3967       case IndexedLane:
3968         Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3969                                                                LaneIndex,
3970                                                                false, S, E));
3971         break;
3972       }
3973       return MatchOperand_Success;
3974     }
3975     Error(S, "vector register expected");
3976     return MatchOperand_ParseFail;
3977   }
3978
3979   if (Parser.getTok().isNot(AsmToken::LCurly))
3980     return MatchOperand_NoMatch;
3981
3982   Parser.Lex(); // Eat '{' token.
3983   SMLoc RegLoc = Parser.getTok().getLoc();
3984
3985   int Reg = tryParseRegister();
3986   if (Reg == -1) {
3987     Error(RegLoc, "register expected");
3988     return MatchOperand_ParseFail;
3989   }
3990   unsigned Count = 1;
3991   int Spacing = 0;
3992   unsigned FirstReg = Reg;
3993   // The list is of D registers, but we also allow Q regs and just interpret
3994   // them as the two D sub-registers.
3995   if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3996     FirstReg = Reg = getDRegFromQReg(Reg);
3997     Spacing = 1; // double-spacing requires explicit D registers, otherwise
3998                  // it's ambiguous with four-register single spaced.
3999     ++Reg;
4000     ++Count;
4001   }
4002
4003   SMLoc E;
4004   if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
4005     return MatchOperand_ParseFail;
4006
4007   while (Parser.getTok().is(AsmToken::Comma) ||
4008          Parser.getTok().is(AsmToken::Minus)) {
4009     if (Parser.getTok().is(AsmToken::Minus)) {
4010       if (!Spacing)
4011         Spacing = 1; // Register range implies a single spaced list.
4012       else if (Spacing == 2) {
4013         Error(Parser.getTok().getLoc(),
4014               "sequential registers in double spaced list");
4015         return MatchOperand_ParseFail;
4016       }
4017       Parser.Lex(); // Eat the minus.
4018       SMLoc AfterMinusLoc = Parser.getTok().getLoc();
4019       int EndReg = tryParseRegister();
4020       if (EndReg == -1) {
4021         Error(AfterMinusLoc, "register expected");
4022         return MatchOperand_ParseFail;
4023       }
4024       // Allow Q regs and just interpret them as the two D sub-registers.
4025       if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
4026         EndReg = getDRegFromQReg(EndReg) + 1;
4027       // If the register is the same as the start reg, there's nothing
4028       // more to do.
4029       if (Reg == EndReg)
4030         continue;
4031       // The register must be in the same register class as the first.
4032       if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
4033         Error(AfterMinusLoc, "invalid register in register list");
4034         return MatchOperand_ParseFail;
4035       }
4036       // Ranges must go from low to high.
4037       if (Reg > EndReg) {
4038         Error(AfterMinusLoc, "bad range in register list");
4039         return MatchOperand_ParseFail;
4040       }
4041       // Parse the lane specifier if present.
4042       VectorLaneTy NextLaneKind;
4043       unsigned NextLaneIndex;
4044       if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
4045           MatchOperand_Success)
4046         return MatchOperand_ParseFail;
4047       if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4048         Error(AfterMinusLoc, "mismatched lane index in register list");
4049         return MatchOperand_ParseFail;
4050       }
4051
4052       // Add all the registers in the range to the register list.
4053       Count += EndReg - Reg;
4054       Reg = EndReg;
4055       continue;
4056     }
4057     Parser.Lex(); // Eat the comma.
4058     RegLoc = Parser.getTok().getLoc();
4059     int OldReg = Reg;
4060     Reg = tryParseRegister();
4061     if (Reg == -1) {
4062       Error(RegLoc, "register expected");
4063       return MatchOperand_ParseFail;
4064     }
4065     // vector register lists must be contiguous.
4066     // It's OK to use the enumeration values directly here rather, as the
4067     // VFP register classes have the enum sorted properly.
4068     //
4069     // The list is of D registers, but we also allow Q regs and just interpret
4070     // them as the two D sub-registers.
4071     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4072       if (!Spacing)
4073         Spacing = 1; // Register range implies a single spaced list.
4074       else if (Spacing == 2) {
4075         Error(RegLoc,
4076               "invalid register in double-spaced list (must be 'D' register')");
4077         return MatchOperand_ParseFail;
4078       }
4079       Reg = getDRegFromQReg(Reg);
4080       if (Reg != OldReg + 1) {
4081         Error(RegLoc, "non-contiguous register range");
4082         return MatchOperand_ParseFail;
4083       }
4084       ++Reg;
4085       Count += 2;
4086       // Parse the lane specifier if present.
4087       VectorLaneTy NextLaneKind;
4088       unsigned NextLaneIndex;
4089       SMLoc LaneLoc = Parser.getTok().getLoc();
4090       if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
4091           MatchOperand_Success)
4092         return MatchOperand_ParseFail;
4093       if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4094         Error(LaneLoc, "mismatched lane index in register list");
4095         return MatchOperand_ParseFail;
4096       }
4097       continue;
4098     }
4099     // Normal D register.
4100     // Figure out the register spacing (single or double) of the list if
4101     // we don't know it already.
4102     if (!Spacing)
4103       Spacing = 1 + (Reg == OldReg + 2);
4104
4105     // Just check that it's contiguous and keep going.
4106     if (Reg != OldReg + Spacing) {
4107       Error(RegLoc, "non-contiguous register range");
4108       return MatchOperand_ParseFail;
4109     }
4110     ++Count;
4111     // Parse the lane specifier if present.
4112     VectorLaneTy NextLaneKind;
4113     unsigned NextLaneIndex;
4114     SMLoc EndLoc = Parser.getTok().getLoc();
4115     if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
4116       return MatchOperand_ParseFail;
4117     if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4118       Error(EndLoc, "mismatched lane index in register list");
4119       return MatchOperand_ParseFail;
4120     }
4121   }
4122
4123   if (Parser.getTok().isNot(AsmToken::RCurly)) {
4124     Error(Parser.getTok().getLoc(), "'}' expected");
4125     return MatchOperand_ParseFail;
4126   }
4127   E = Parser.getTok().getEndLoc();
4128   Parser.Lex(); // Eat '}' token.
4129
4130   switch (LaneKind) {
4131   case NoLanes:
4132     // Two-register operands have been converted to the
4133     // composite register classes.
4134     if (Count == 2) {
4135       const MCRegisterClass *RC = (Spacing == 1) ?
4136         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
4137         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
4138       FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
4139     }
4140     Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
4141                                                     (Spacing == 2), S, E));
4142     break;
4143   case AllLanes:
4144     // Two-register operands have been converted to the
4145     // composite register classes.
4146     if (Count == 2) {
4147       const MCRegisterClass *RC = (Spacing == 1) ?
4148         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
4149         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
4150       FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
4151     }
4152     Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
4153                                                             (Spacing == 2),
4154                                                             S, E));
4155     break;
4156   case IndexedLane:
4157     Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
4158                                                            LaneIndex,
4159                                                            (Spacing == 2),
4160                                                            S, E));
4161     break;
4162   }
4163   return MatchOperand_Success;
4164 }
4165
4166 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
4167 OperandMatchResultTy
4168 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
4169   MCAsmParser &Parser = getParser();
4170   SMLoc S = Parser.getTok().getLoc();
4171   const AsmToken &Tok = Parser.getTok();
4172   unsigned Opt;
4173
4174   if (Tok.is(AsmToken::Identifier)) {
4175     StringRef OptStr = Tok.getString();
4176
4177     Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
4178       .Case("sy",    ARM_MB::SY)
4179       .Case("st",    ARM_MB::ST)
4180       .Case("ld",    ARM_MB::LD)
4181       .Case("sh",    ARM_MB::ISH)
4182       .Case("ish",   ARM_MB::ISH)
4183       .Case("shst",  ARM_MB::ISHST)
4184       .Case("ishst", ARM_MB::ISHST)
4185       .Case("ishld", ARM_MB::ISHLD)
4186       .Case("nsh",   ARM_MB::NSH)
4187       .Case("un",    ARM_MB::NSH)
4188       .Case("nshst", ARM_MB::NSHST)
4189       .Case("nshld", ARM_MB::NSHLD)
4190       .Case("unst",  ARM_MB::NSHST)
4191       .Case("osh",   ARM_MB::OSH)
4192       .Case("oshst", ARM_MB::OSHST)
4193       .Case("oshld", ARM_MB::OSHLD)
4194       .Default(~0U);
4195
4196     // ishld, oshld, nshld and ld are only available from ARMv8.
4197     if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
4198                         Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
4199       Opt = ~0U;
4200
4201     if (Opt == ~0U)
4202       return MatchOperand_NoMatch;
4203
4204     Parser.Lex(); // Eat identifier token.
4205   } else if (Tok.is(AsmToken::Hash) ||
4206              Tok.is(AsmToken::Dollar) ||
4207              Tok.is(AsmToken::Integer)) {
4208     if (Parser.getTok().isNot(AsmToken::Integer))
4209       Parser.Lex(); // Eat '#' or '$'.
4210     SMLoc Loc = Parser.getTok().getLoc();
4211
4212     const MCExpr *MemBarrierID;
4213     if (getParser().parseExpression(MemBarrierID)) {
4214       Error(Loc, "illegal expression");
4215       return MatchOperand_ParseFail;
4216     }
4217
4218     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
4219     if (!CE) {
4220       Error(Loc, "constant expression expected");
4221       return MatchOperand_ParseFail;
4222     }
4223
4224     int Val = CE->getValue();
4225     if (Val & ~0xf) {
4226       Error(Loc, "immediate value out of range");
4227       return MatchOperand_ParseFail;
4228     }
4229
4230     Opt = ARM_MB::RESERVED_0 + Val;
4231   } else
4232     return MatchOperand_ParseFail;
4233
4234   Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
4235   return MatchOperand_Success;
4236 }
4237
4238 OperandMatchResultTy
4239 ARMAsmParser::parseTraceSyncBarrierOptOperand(OperandVector &Operands) {
4240   MCAsmParser &Parser = getParser();
4241   SMLoc S = Parser.getTok().getLoc();
4242   const AsmToken &Tok = Parser.getTok();
4243
4244   if (Tok.isNot(AsmToken::Identifier))
4245      return MatchOperand_NoMatch;
4246
4247   if (!Tok.getString().equals_lower("csync"))
4248     return MatchOperand_NoMatch;
4249
4250   Parser.Lex(); // Eat identifier token.
4251
4252   Operands.push_back(ARMOperand::CreateTraceSyncBarrierOpt(ARM_TSB::CSYNC, S));
4253   return MatchOperand_Success;
4254 }
4255
4256 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
4257 OperandMatchResultTy
4258 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
4259   MCAsmParser &Parser = getParser();
4260   SMLoc S = Parser.getTok().getLoc();
4261   const AsmToken &Tok = Parser.getTok();
4262   unsigned Opt;
4263
4264   if (Tok.is(AsmToken::Identifier)) {
4265     StringRef OptStr = Tok.getString();
4266
4267     if (OptStr.equals_lower("sy"))
4268       Opt = ARM_ISB::SY;
4269     else
4270       return MatchOperand_NoMatch;
4271
4272     Parser.Lex(); // Eat identifier token.
4273   } else if (Tok.is(AsmToken::Hash) ||
4274              Tok.is(AsmToken::Dollar) ||
4275              Tok.is(AsmToken::Integer)) {
4276     if (Parser.getTok().isNot(AsmToken::Integer))
4277       Parser.Lex(); // Eat '#' or '$'.
4278     SMLoc Loc = Parser.getTok().getLoc();
4279
4280     const MCExpr *ISBarrierID;
4281     if (getParser().parseExpression(ISBarrierID)) {
4282       Error(Loc, "illegal expression");
4283       return MatchOperand_ParseFail;
4284     }
4285
4286     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
4287     if (!CE) {
4288       Error(Loc, "constant expression expected");
4289       return MatchOperand_ParseFail;
4290     }
4291
4292     int Val = CE->getValue();
4293     if (Val & ~0xf) {
4294       Error(Loc, "immediate value out of range");
4295       return MatchOperand_ParseFail;
4296     }
4297
4298     Opt = ARM_ISB::RESERVED_0 + Val;
4299   } else
4300     return MatchOperand_ParseFail;
4301
4302   Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
4303           (ARM_ISB::InstSyncBOpt)Opt, S));
4304   return MatchOperand_Success;
4305 }
4306
4307
4308 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
4309 OperandMatchResultTy
4310 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
4311   MCAsmParser &Parser = getParser();
4312   SMLoc S = Parser.getTok().getLoc();
4313   const AsmToken &Tok = Parser.getTok();
4314   if (!Tok.is(AsmToken::Identifier))
4315     return MatchOperand_NoMatch;
4316   StringRef IFlagsStr = Tok.getString();
4317
4318   // An iflags string of "none" is interpreted to mean that none of the AIF
4319   // bits are set.  Not a terribly useful instruction, but a valid encoding.
4320   unsigned IFlags = 0;
4321   if (IFlagsStr != "none") {
4322         for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
4323       unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1).lower())
4324         .Case("a", ARM_PROC::A)
4325         .Case("i", ARM_PROC::I)
4326         .Case("f", ARM_PROC::F)
4327         .Default(~0U);
4328
4329       // If some specific iflag is already set, it means that some letter is
4330       // present more than once, this is not acceptable.
4331       if (Flag == ~0U || (IFlags & Flag))
4332         return MatchOperand_NoMatch;
4333
4334       IFlags |= Flag;
4335     }
4336   }
4337
4338   Parser.Lex(); // Eat identifier token.
4339   Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
4340   return MatchOperand_Success;
4341 }
4342
4343 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
4344 OperandMatchResultTy
4345 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
4346   MCAsmParser &Parser = getParser();
4347   SMLoc S = Parser.getTok().getLoc();
4348   const AsmToken &Tok = Parser.getTok();
4349
4350   if (Tok.is(AsmToken::Integer)) {
4351     int64_t Val = Tok.getIntVal();
4352     if (Val > 255 || Val < 0) {
4353       return MatchOperand_NoMatch;
4354     }
4355     unsigned SYSmvalue = Val & 0xFF;
4356     Parser.Lex();
4357     Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S));
4358     return MatchOperand_Success;
4359   }
4360
4361   if (!Tok.is(AsmToken::Identifier))
4362     return MatchOperand_NoMatch;
4363   StringRef Mask = Tok.getString();
4364
4365   if (isMClass()) {
4366     auto TheReg = ARMSysReg::lookupMClassSysRegByName(Mask.lower());
4367     if (!TheReg || !TheReg->hasRequiredFeatures(getSTI().getFeatureBits()))
4368       return MatchOperand_NoMatch;
4369
4370     unsigned SYSmvalue = TheReg->Encoding & 0xFFF;
4371
4372     Parser.Lex(); // Eat identifier token.
4373     Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S));
4374     return MatchOperand_Success;
4375   }
4376
4377   // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
4378   size_t Start = 0, Next = Mask.find('_');
4379   StringRef Flags = "";
4380   std::string SpecReg = Mask.slice(Start, Next).lower();
4381   if (Next != StringRef::npos)
4382     Flags = Mask.slice(Next+1, Mask.size());
4383
4384   // FlagsVal contains the complete mask:
4385   // 3-0: Mask
4386   // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4387   unsigned FlagsVal = 0;
4388
4389   if (SpecReg == "apsr") {
4390     FlagsVal = StringSwitch<unsigned>(Flags)
4391     .Case("nzcvq",  0x8) // same as CPSR_f
4392     .Case("g",      0x4) // same as CPSR_s
4393     .Case("nzcvqg", 0xc) // same as CPSR_fs
4394     .Default(~0U);
4395
4396     if (FlagsVal == ~0U) {
4397       if (!Flags.empty())
4398         return MatchOperand_NoMatch;
4399       else
4400         FlagsVal = 8; // No flag
4401     }
4402   } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
4403     // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
4404     if (Flags == "all" || Flags == "")
4405       Flags = "fc";
4406     for (int i = 0, e = Flags.size(); i != e; ++i) {
4407       unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
4408       .Case("c", 1)
4409       .Case("x", 2)
4410       .Case("s", 4)
4411       .Case("f", 8)
4412       .Default(~0U);
4413
4414       // If some specific flag is already set, it means that some letter is
4415       // present more than once, this is not acceptable.
4416       if (Flag == ~0U || (FlagsVal & Flag))
4417         return MatchOperand_NoMatch;
4418       FlagsVal |= Flag;
4419     }
4420   } else // No match for special register.
4421     return MatchOperand_NoMatch;
4422
4423   // Special register without flags is NOT equivalent to "fc" flags.
4424   // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
4425   // two lines would enable gas compatibility at the expense of breaking
4426   // round-tripping.
4427   //
4428   // if (!FlagsVal)
4429   //  FlagsVal = 0x9;
4430
4431   // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4432   if (SpecReg == "spsr")
4433     FlagsVal |= 16;
4434
4435   Parser.Lex(); // Eat identifier token.
4436   Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4437   return MatchOperand_Success;
4438 }
4439
4440 /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for
4441 /// use in the MRS/MSR instructions added to support virtualization.
4442 OperandMatchResultTy
4443 ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
4444   MCAsmParser &Parser = getParser();
4445   SMLoc S = Parser.getTok().getLoc();
4446   const AsmToken &Tok = Parser.getTok();
4447   if (!Tok.is(AsmToken::Identifier))
4448     return MatchOperand_NoMatch;
4449   StringRef RegName = Tok.getString();
4450
4451   auto TheReg = ARMBankedReg::lookupBankedRegByName(RegName.lower());
4452   if (!TheReg)
4453     return MatchOperand_NoMatch;
4454   unsigned Encoding = TheReg->Encoding;
4455
4456   Parser.Lex(); // Eat identifier token.
4457   Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S));
4458   return MatchOperand_Success;
4459 }
4460
4461 OperandMatchResultTy
4462 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
4463                           int High) {
4464   MCAsmParser &Parser = getParser();
4465   const AsmToken &Tok = Parser.getTok();
4466   if (Tok.isNot(AsmToken::Identifier)) {
4467     Error(Parser.getTok().getLoc(), Op + " operand expected.");
4468     return MatchOperand_ParseFail;
4469   }
4470   StringRef ShiftName = Tok.getString();
4471   std::string LowerOp = Op.lower();
4472   std::string UpperOp = Op.upper();
4473   if (ShiftName != LowerOp && ShiftName != UpperOp) {
4474     Error(Parser.getTok().getLoc(), Op + " operand expected.");
4475     return MatchOperand_ParseFail;
4476   }
4477   Parser.Lex(); // Eat shift type token.
4478
4479   // There must be a '#' and a shift amount.
4480   if (Parser.getTok().isNot(AsmToken::Hash) &&
4481       Parser.getTok().isNot(AsmToken::Dollar)) {
4482     Error(Parser.getTok().getLoc(), "'#' expected");
4483     return MatchOperand_ParseFail;
4484   }
4485   Parser.Lex(); // Eat hash token.
4486
4487   const MCExpr *ShiftAmount;
4488   SMLoc Loc = Parser.getTok().getLoc();
4489   SMLoc EndLoc;
4490   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4491     Error(Loc, "illegal expression");
4492     return MatchOperand_ParseFail;
4493   }
4494   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4495   if (!CE) {
4496     Error(Loc, "constant expression expected");
4497     return MatchOperand_ParseFail;
4498   }
4499   int Val = CE->getValue();
4500   if (Val < Low || Val > High) {
4501     Error(Loc, "immediate value out of range");
4502     return MatchOperand_ParseFail;
4503   }
4504
4505   Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
4506
4507   return MatchOperand_Success;
4508 }
4509
4510 OperandMatchResultTy
4511 ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
4512   MCAsmParser &Parser = getParser();
4513   const AsmToken &Tok = Parser.getTok();
4514   SMLoc S = Tok.getLoc();
4515   if (Tok.isNot(AsmToken::Identifier)) {
4516     Error(S, "'be' or 'le' operand expected");
4517     return MatchOperand_ParseFail;
4518   }
4519   int Val = StringSwitch<int>(Tok.getString().lower())
4520     .Case("be", 1)
4521     .Case("le", 0)
4522     .Default(-1);
4523   Parser.Lex(); // Eat the token.
4524
4525   if (Val == -1) {
4526     Error(S, "'be' or 'le' operand expected");
4527     return MatchOperand_ParseFail;
4528   }
4529   Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::create(Val,
4530                                                                   getContext()),
4531                                            S, Tok.getEndLoc()));
4532   return MatchOperand_Success;
4533 }
4534
4535 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
4536 /// instructions. Legal values are:
4537 ///     lsl #n  'n' in [0,31]
4538 ///     asr #n  'n' in [1,32]
4539 ///             n == 32 encoded as n == 0.
4540 OperandMatchResultTy
4541 ARMAsmParser::parseShifterImm(OperandVector &Operands) {
4542   MCAsmParser &Parser = getParser();
4543   const AsmToken &Tok = Parser.getTok();
4544   SMLoc S = Tok.getLoc();
4545   if (Tok.isNot(AsmToken::Identifier)) {
4546     Error(S, "shift operator 'asr' or 'lsl' expected");
4547     return MatchOperand_ParseFail;
4548   }
4549   StringRef ShiftName = Tok.getString();
4550   bool isASR;
4551   if (ShiftName == "lsl" || ShiftName == "LSL")
4552     isASR = false;
4553   else if (ShiftName == "asr" || ShiftName == "ASR")
4554     isASR = true;
4555   else {
4556     Error(S, "shift operator 'asr' or 'lsl' expected");
4557     return MatchOperand_ParseFail;
4558   }
4559   Parser.Lex(); // Eat the operator.
4560
4561   // A '#' and a shift amount.
4562   if (Parser.getTok().isNot(AsmToken::Hash) &&
4563       Parser.getTok().isNot(AsmToken::Dollar)) {
4564     Error(Parser.getTok().getLoc(), "'#' expected");
4565     return MatchOperand_ParseFail;
4566   }
4567   Parser.Lex(); // Eat hash token.
4568   SMLoc ExLoc = Parser.getTok().getLoc();
4569
4570   const MCExpr *ShiftAmount;
4571   SMLoc EndLoc;
4572   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4573     Error(ExLoc, "malformed shift expression");
4574     return MatchOperand_ParseFail;
4575   }
4576   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4577   if (!CE) {
4578     Error(ExLoc, "shift amount must be an immediate");
4579     return MatchOperand_ParseFail;
4580   }
4581
4582   int64_t Val = CE->getValue();
4583   if (isASR) {
4584     // Shift amount must be in [1,32]
4585     if (Val < 1 || Val > 32) {
4586       Error(ExLoc, "'asr' shift amount must be in range [1,32]");
4587       return MatchOperand_ParseFail;
4588     }
4589     // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
4590     if (isThumb() && Val == 32) {
4591       Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
4592       return MatchOperand_ParseFail;
4593     }
4594     if (Val == 32) Val = 0;
4595   } else {
4596     // Shift amount must be in [1,32]
4597     if (Val < 0 || Val > 31) {
4598       Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
4599       return MatchOperand_ParseFail;
4600     }
4601   }
4602
4603   Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
4604
4605   return MatchOperand_Success;
4606 }
4607
4608 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
4609 /// of instructions. Legal values are:
4610 ///     ror #n  'n' in {0, 8, 16, 24}
4611 OperandMatchResultTy
4612 ARMAsmParser::parseRotImm(OperandVector &Operands) {
4613   MCAsmParser &Parser = getParser();
4614   const AsmToken &Tok = Parser.getTok();
4615   SMLoc S = Tok.getLoc();
4616   if (Tok.isNot(AsmToken::Identifier))
4617     return MatchOperand_NoMatch;
4618   StringRef ShiftName = Tok.getString();
4619   if (ShiftName != "ror" && ShiftName != "ROR")
4620     return MatchOperand_NoMatch;
4621   Parser.Lex(); // Eat the operator.
4622
4623   // A '#' and a rotate amount.
4624   if (Parser.getTok().isNot(AsmToken::Hash) &&
4625       Parser.getTok().isNot(AsmToken::Dollar)) {
4626     Error(Parser.getTok().getLoc(), "'#' expected");
4627     return MatchOperand_ParseFail;
4628   }
4629   Parser.Lex(); // Eat hash token.
4630   SMLoc ExLoc = Parser.getTok().getLoc();
4631
4632   const MCExpr *ShiftAmount;
4633   SMLoc EndLoc;
4634   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4635     Error(ExLoc, "malformed rotate expression");
4636     return MatchOperand_ParseFail;
4637   }
4638   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4639   if (!CE) {
4640     Error(ExLoc, "rotate amount must be an immediate");
4641     return MatchOperand_ParseFail;
4642   }
4643
4644   int64_t Val = CE->getValue();
4645   // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4646   // normally, zero is represented in asm by omitting the rotate operand
4647   // entirely.
4648   if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4649     Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4650     return MatchOperand_ParseFail;
4651   }
4652
4653   Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4654
4655   return MatchOperand_Success;
4656 }
4657
4658 OperandMatchResultTy
4659 ARMAsmParser::parseModImm(OperandVector &Operands) {
4660   MCAsmParser &Parser = getParser();
4661   MCAsmLexer &Lexer = getLexer();
4662   int64_t Imm1, Imm2;
4663
4664   SMLoc S = Parser.getTok().getLoc();
4665
4666   // 1) A mod_imm operand can appear in the place of a register name:
4667   //   add r0, #mod_imm
4668   //   add r0, r0, #mod_imm
4669   // to correctly handle the latter, we bail out as soon as we see an
4670   // identifier.
4671   //
4672   // 2) Similarly, we do not want to parse into complex operands:
4673   //   mov r0, #mod_imm
4674   //   mov r0, :lower16:(_foo)
4675   if (Parser.getTok().is(AsmToken::Identifier) ||
4676       Parser.getTok().is(AsmToken::Colon))
4677     return MatchOperand_NoMatch;
4678
4679   // Hash (dollar) is optional as per the ARMARM
4680   if (Parser.getTok().is(AsmToken::Hash) ||
4681       Parser.getTok().is(AsmToken::Dollar)) {
4682     // Avoid parsing into complex operands (#:)
4683     if (Lexer.peekTok().is(AsmToken::Colon))
4684       return MatchOperand_NoMatch;
4685
4686     // Eat the hash (dollar)
4687     Parser.Lex();
4688   }
4689
4690   SMLoc Sx1, Ex1;
4691   Sx1 = Parser.getTok().getLoc();
4692   const MCExpr *Imm1Exp;
4693   if (getParser().parseExpression(Imm1Exp, Ex1)) {
4694     Error(Sx1, "malformed expression");
4695     return MatchOperand_ParseFail;
4696   }
4697
4698   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm1Exp);
4699
4700   if (CE) {
4701     // Immediate must fit within 32-bits
4702     Imm1 = CE->getValue();
4703     int Enc = ARM_AM::getSOImmVal(Imm1);
4704     if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) {
4705       // We have a match!
4706       Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF),
4707                                                   (Enc & 0xF00) >> 7,
4708                                                   Sx1, Ex1));
4709       return MatchOperand_Success;
4710     }
4711
4712     // We have parsed an immediate which is not for us, fallback to a plain
4713     // immediate. This can happen for instruction aliases. For an example,
4714     // ARMInstrInfo.td defines the alias [mov <-> mvn] which can transform
4715     // a mov (mvn) with a mod_imm_neg/mod_imm_not operand into the opposite
4716     // instruction with a mod_imm operand. The alias is defined such that the
4717     // parser method is shared, that's why we have to do this here.
4718     if (Parser.getTok().is(AsmToken::EndOfStatement)) {
4719       Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
4720       return MatchOperand_Success;
4721     }
4722   } else {
4723     // Operands like #(l1 - l2) can only be evaluated at a later stage (via an
4724     // MCFixup). Fallback to a plain immediate.
4725     Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
4726     return MatchOperand_Success;
4727   }
4728
4729   // From this point onward, we expect the input to be a (#bits, #rot) pair
4730   if (Parser.getTok().isNot(AsmToken::Comma)) {
4731     Error(Sx1, "expected modified immediate operand: #[0, 255], #even[0-30]");
4732     return MatchOperand_ParseFail;
4733   }
4734
4735   if (Imm1 & ~0xFF) {
4736     Error(Sx1, "immediate operand must a number in the range [0, 255]");
4737     return MatchOperand_ParseFail;
4738   }
4739
4740   // Eat the comma
4741   Parser.Lex();
4742
4743   // Repeat for #rot
4744   SMLoc Sx2, Ex2;
4745   Sx2 = Parser.getTok().getLoc();
4746
4747   // Eat the optional hash (dollar)
4748   if (Parser.getTok().is(AsmToken::Hash) ||
4749       Parser.getTok().is(AsmToken::Dollar))
4750     Parser.Lex();
4751
4752   const MCExpr *Imm2Exp;
4753   if (getParser().parseExpression(Imm2Exp, Ex2)) {
4754     Error(Sx2, "malformed expression");
4755     return MatchOperand_ParseFail;
4756   }
4757
4758   CE = dyn_cast<MCConstantExpr>(Imm2Exp);
4759
4760   if (CE) {
4761     Imm2 = CE->getValue();
4762     if (!(Imm2 & ~0x1E)) {
4763       // We have a match!
4764       Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2));
4765       return MatchOperand_Success;
4766     }
4767     Error(Sx2, "immediate operand must an even number in the range [0, 30]");
4768     return MatchOperand_ParseFail;
4769   } else {
4770     Error(Sx2, "constant expression expected");
4771     return MatchOperand_ParseFail;
4772   }
4773 }
4774
4775 OperandMatchResultTy
4776 ARMAsmParser::parseBitfield(OperandVector &Operands) {
4777   MCAsmParser &Parser = getParser();
4778   SMLoc S = Parser.getTok().getLoc();
4779   // The bitfield descriptor is really two operands, the LSB and the width.
4780   if (Parser.getTok().isNot(AsmToken::Hash) &&
4781       Parser.getTok().isNot(AsmToken::Dollar)) {
4782     Error(Parser.getTok().getLoc(), "'#' expected");
4783     return MatchOperand_ParseFail;
4784   }
4785   Parser.Lex(); // Eat hash token.
4786
4787   const MCExpr *LSBExpr;
4788   SMLoc E = Parser.getTok().getLoc();
4789   if (getParser().parseExpression(LSBExpr)) {
4790     Error(E, "malformed immediate expression");
4791     return MatchOperand_ParseFail;
4792   }
4793   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4794   if (!CE) {
4795     Error(E, "'lsb' operand must be an immediate");
4796     return MatchOperand_ParseFail;
4797   }
4798
4799   int64_t LSB = CE->getValue();
4800   // The LSB must be in the range [0,31]
4801   if (LSB < 0 || LSB > 31) {
4802     Error(E, "'lsb' operand must be in the range [0,31]");
4803     return MatchOperand_ParseFail;
4804   }
4805   E = Parser.getTok().getLoc();
4806
4807   // Expect another immediate operand.
4808   if (Parser.getTok().isNot(AsmToken::Comma)) {
4809     Error(Parser.getTok().getLoc(), "too few operands");
4810     return MatchOperand_ParseFail;
4811   }
4812   Parser.Lex(); // Eat hash token.
4813   if (Parser.getTok().isNot(AsmToken::Hash) &&
4814       Parser.getTok().isNot(AsmToken::Dollar)) {
4815     Error(Parser.getTok().getLoc(), "'#' expected");
4816     return MatchOperand_ParseFail;
4817   }
4818   Parser.Lex(); // Eat hash token.
4819
4820   const MCExpr *WidthExpr;
4821   SMLoc EndLoc;
4822   if (getParser().parseExpression(WidthExpr, EndLoc)) {
4823     Error(E, "malformed immediate expression");
4824     return MatchOperand_ParseFail;
4825   }
4826   CE = dyn_cast<MCConstantExpr>(WidthExpr);
4827   if (!CE) {
4828     Error(E, "'width' operand must be an immediate");
4829     return MatchOperand_ParseFail;
4830   }
4831
4832   int64_t Width = CE->getValue();
4833   // The LSB must be in the range [1,32-lsb]
4834   if (Width < 1 || Width > 32 - LSB) {
4835     Error(E, "'width' operand must be in the range [1,32-lsb]");
4836     return MatchOperand_ParseFail;
4837   }
4838
4839   Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4840
4841   return MatchOperand_Success;
4842 }
4843
4844 OperandMatchResultTy
4845 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
4846   // Check for a post-index addressing register operand. Specifically:
4847   // postidx_reg := '+' register {, shift}
4848   //              | '-' register {, shift}
4849   //              | register {, shift}
4850
4851   // This method must return MatchOperand_NoMatch without consuming any tokens
4852   // in the case where there is no match, as other alternatives take other
4853   // parse methods.
4854   MCAsmParser &Parser = getParser();
4855   AsmToken Tok = Parser.getTok();
4856   SMLoc S = Tok.getLoc();
4857   bool haveEaten = false;
4858   bool isAdd = true;
4859   if (Tok.is(AsmToken::Plus)) {
4860     Parser.Lex(); // Eat the '+' token.
4861     haveEaten = true;
4862   } else if (Tok.is(AsmToken::Minus)) {
4863     Parser.Lex(); // Eat the '-' token.
4864     isAdd = false;
4865     haveEaten = true;
4866   }
4867
4868   SMLoc E = Parser.getTok().getEndLoc();
4869   int Reg = tryParseRegister();
4870   if (Reg == -1) {
4871     if (!haveEaten)
4872       return MatchOperand_NoMatch;
4873     Error(Parser.getTok().getLoc(), "register expected");
4874     return MatchOperand_ParseFail;
4875   }
4876
4877   ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4878   unsigned ShiftImm = 0;
4879   if (Parser.getTok().is(AsmToken::Comma)) {
4880     Parser.Lex(); // Eat the ','.
4881     if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4882       return MatchOperand_ParseFail;
4883
4884     // FIXME: Only approximates end...may include intervening whitespace.
4885     E = Parser.getTok().getLoc();
4886   }
4887
4888   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4889                                                   ShiftImm, S, E));
4890
4891   return MatchOperand_Success;
4892 }
4893
4894 OperandMatchResultTy
4895 ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
4896   // Check for a post-index addressing register operand. Specifically:
4897   // am3offset := '+' register
4898   //              | '-' register
4899   //              | register
4900   //              | # imm
4901   //              | # + imm
4902   //              | # - imm
4903
4904   // This method must return MatchOperand_NoMatch without consuming any tokens
4905   // in the case where there is no match, as other alternatives take other
4906   // parse methods.
4907   MCAsmParser &Parser = getParser();
4908   AsmToken Tok = Parser.getTok();
4909   SMLoc S = Tok.getLoc();
4910
4911   // Do immediates first, as we always parse those if we have a '#'.
4912   if (Parser.getTok().is(AsmToken::Hash) ||
4913       Parser.getTok().is(AsmToken::Dollar)) {
4914     Parser.Lex(); // Eat '#' or '$'.
4915     // Explicitly look for a '-', as we need to encode negative zero
4916     // differently.
4917     bool isNegative = Parser.getTok().is(AsmToken::Minus);
4918     const MCExpr *Offset;
4919     SMLoc E;
4920     if (getParser().parseExpression(Offset, E))
4921       return MatchOperand_ParseFail;
4922     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4923     if (!CE) {
4924       Error(S, "constant expression expected");
4925       return MatchOperand_ParseFail;
4926     }
4927     // Negative zero is encoded as the flag value
4928     // std::numeric_limits<int32_t>::min().
4929     int32_t Val = CE->getValue();
4930     if (isNegative && Val == 0)
4931       Val = std::numeric_limits<int32_t>::min();
4932
4933     Operands.push_back(
4934       ARMOperand::CreateImm(MCConstantExpr::create(Val, getContext()), S, E));
4935
4936     return MatchOperand_Success;
4937   }
4938
4939   bool haveEaten = false;
4940   bool isAdd = true;
4941   if (Tok.is(AsmToken::Plus)) {
4942     Parser.Lex(); // Eat the '+' token.
4943     haveEaten = true;
4944   } else if (Tok.is(AsmToken::Minus)) {
4945     Parser.Lex(); // Eat the '-' token.
4946     isAdd = false;
4947     haveEaten = true;
4948   }
4949
4950   Tok = Parser.getTok();
4951   int Reg = tryParseRegister();
4952   if (Reg == -1) {
4953     if (!haveEaten)
4954       return MatchOperand_NoMatch;
4955     Error(Tok.getLoc(), "register expected");
4956     return MatchOperand_ParseFail;
4957   }
4958
4959   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4960                                                   0, S, Tok.getEndLoc()));
4961
4962   return MatchOperand_Success;
4963 }
4964
4965 /// Convert parsed operands to MCInst.  Needed here because this instruction
4966 /// only has two register operands, but multiplication is commutative so
4967 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4968 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
4969                                     const OperandVector &Operands) {
4970   ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
4971   ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
4972   // If we have a three-operand form, make sure to set Rn to be the operand
4973   // that isn't the same as Rd.
4974   unsigned RegOp = 4;
4975   if (Operands.size() == 6 &&
4976       ((ARMOperand &)*Operands[4]).getReg() ==
4977           ((ARMOperand &)*Operands[3]).getReg())
4978     RegOp = 5;
4979   ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
4980   Inst.addOperand(Inst.getOperand(0));
4981   ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
4982 }
4983
4984 void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
4985                                     const OperandVector &Operands) {
4986   int CondOp = -1, ImmOp = -1;
4987   switch(Inst.getOpcode()) {
4988     case ARM::tB:
4989     case ARM::tBcc:  CondOp = 1; ImmOp = 2; break;
4990
4991     case ARM::t2B:
4992     case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4993
4994     default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4995   }
4996   // first decide whether or not the branch should be conditional
4997   // by looking at it's location relative to an IT block
4998   if(inITBlock()) {
4999     // inside an IT block we cannot have any conditional branches. any
5000     // such instructions needs to be converted to unconditional form
5001     switch(Inst.getOpcode()) {
5002       case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
5003       case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
5004     }
5005   } else {
5006     // outside IT blocks we can only have unconditional branches with AL
5007     // condition code or conditional branches with non-AL condition code
5008     unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode();
5009     switch(Inst.getOpcode()) {
5010       case ARM::tB:
5011       case ARM::tBcc:
5012         Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
5013         break;
5014       case ARM::t2B:
5015       case ARM::t2Bcc:
5016         Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
5017         break;
5018     }
5019   }
5020
5021   // now decide on encoding size based on branch target range
5022   switch(Inst.getOpcode()) {
5023     // classify tB as either t2B or t1B based on range of immediate operand
5024     case ARM::tB: {
5025       ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
5026       if (!op.isSignedOffset<11, 1>() && isThumb() && hasV8MBaseline())
5027         Inst.setOpcode(ARM::t2B);
5028       break;
5029     }
5030     // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
5031     case ARM::tBcc: {
5032       ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
5033       if (!op.isSignedOffset<8, 1>() && isThumb() && hasV8MBaseline())
5034         Inst.setOpcode(ARM::t2Bcc);
5035       break;
5036     }
5037   }
5038   ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
5039   ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
5040 }
5041
5042 /// Parse an ARM memory expression, return false if successful else return true
5043 /// or an error.  The first token must be a '[' when called.
5044 bool ARMAsmParser::parseMemory(OperandVector &Operands) {
5045   MCAsmParser &Parser = getParser();
5046   SMLoc S, E;
5047   if (Parser.getTok().isNot(AsmToken::LBrac))
5048     return TokError("Token is not a Left Bracket");
5049   S = Parser.getTok().getLoc();
5050   Parser.Lex(); // Eat left bracket token.
5051
5052   const AsmToken &BaseRegTok = Parser.getTok();
5053   int BaseRegNum = tryParseRegister();
5054   if (BaseRegNum == -1)
5055     return Error(BaseRegTok.getLoc(), "register expected");
5056
5057   // The next token must either be a comma, a colon or a closing bracket.
5058   const AsmToken &Tok = Parser.getTok();
5059   if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
5060       !Tok.is(AsmToken::RBrac))
5061     return Error(Tok.getLoc(), "malformed memory operand");
5062
5063   if (Tok.is(AsmToken::RBrac)) {
5064     E = Tok.getEndLoc();
5065     Parser.Lex(); // Eat right bracket token.
5066
5067     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
5068                                              ARM_AM::no_shift, 0, 0, false,
5069                                              S, E));
5070
5071     // If there's a pre-indexing writeback marker, '!', just add it as a token
5072     // operand. It's rather odd, but syntactically valid.
5073     if (Parser.getTok().is(AsmToken::Exclaim)) {
5074       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5075       Parser.Lex(); // Eat the '!'.
5076     }
5077
5078     return false;
5079   }
5080
5081   assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
5082          "Lost colon or comma in memory operand?!");
5083   if (Tok.is(AsmToken::Comma)) {
5084     Parser.Lex(); // Eat the comma.
5085   }
5086
5087   // If we have a ':', it's an alignment specifier.
5088   if (Parser.getTok().is(AsmToken::Colon)) {
5089     Parser.Lex(); // Eat the ':'.
5090     E = Parser.getTok().getLoc();
5091     SMLoc AlignmentLoc = Tok.getLoc();
5092
5093     const MCExpr *Expr;
5094     if (getParser().parseExpression(Expr))
5095      return true;
5096
5097     // The expression has to be a constant. Memory references with relocations
5098     // don't come through here, as they use the <label> forms of the relevant
5099     // instructions.
5100     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
5101     if (!CE)
5102       return Error (E, "constant expression expected");
5103
5104     unsigned Align = 0;
5105     switch (CE->getValue()) {
5106     default:
5107       return Error(E,
5108                    "alignment specifier must be 16, 32, 64, 128, or 256 bits");
5109     case 16:  Align = 2; break;
5110     case 32:  Align = 4; break;
5111     case 64:  Align = 8; break;
5112     case 128: Align = 16; break;
5113     case 256: Align = 32; break;
5114     }
5115
5116     // Now we should have the closing ']'
5117     if (Parser.getTok().isNot(AsmToken::RBrac))
5118       return Error(Parser.getTok().getLoc(), "']' expected");
5119     E = Parser.getTok().getEndLoc();
5120     Parser.Lex(); // Eat right bracket token.
5121
5122     // Don't worry about range checking the value here. That's handled by
5123     // the is*() predicates.
5124     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
5125                                              ARM_AM::no_shift, 0, Align,
5126                                              false, S, E, AlignmentLoc));
5127
5128     // If there's a pre-indexing writeback marker, '!', just add it as a token
5129     // operand.
5130     if (Parser.getTok().is(AsmToken::Exclaim)) {
5131       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5132       Parser.Lex(); // Eat the '!'.
5133     }
5134
5135     return false;
5136   }
5137
5138   // If we have a '#', it's an immediate offset, else assume it's a register
5139   // offset. Be friendly and also accept a plain integer (without a leading
5140   // hash) for gas compatibility.
5141   if (Parser.getTok().is(AsmToken::Hash) ||
5142       Parser.getTok().is(AsmToken::Dollar) ||
5143       Parser.getTok().is(AsmToken::Integer)) {
5144     if (Parser.getTok().isNot(AsmToken::Integer))
5145       Parser.Lex(); // Eat '#' or '$'.
5146     E = Parser.getTok().getLoc();
5147
5148     bool isNegative = getParser().getTok().is(AsmToken::Minus);
5149     const MCExpr *Offset;
5150     if (getParser().parseExpression(Offset))
5151      return true;
5152
5153     // The expression has to be a constant. Memory references with relocations
5154     // don't come through here, as they use the <label> forms of the relevant
5155     // instructions.
5156     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
5157     if (!CE)
5158       return Error (E, "constant expression expected");
5159
5160     // If the constant was #-0, represent it as
5161     // std::numeric_limits<int32_t>::min().
5162     int32_t Val = CE->getValue();
5163     if (isNegative && Val == 0)
5164       CE = MCConstantExpr::create(std::numeric_limits<int32_t>::min(),
5165                                   getContext());
5166
5167     // Now we should have the closing ']'
5168     if (Parser.getTok().isNot(AsmToken::RBrac))
5169       return Error(Parser.getTok().getLoc(), "']' expected");
5170     E = Parser.getTok().getEndLoc();
5171     Parser.Lex(); // Eat right bracket token.
5172
5173     // Don't worry about range checking the value here. That's handled by
5174     // the is*() predicates.
5175     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
5176                                              ARM_AM::no_shift, 0, 0,
5177                                              false, S, E));
5178
5179     // If there's a pre-indexing writeback marker, '!', just add it as a token
5180     // operand.
5181     if (Parser.getTok().is(AsmToken::Exclaim)) {
5182       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5183       Parser.Lex(); // Eat the '!'.
5184     }
5185
5186     return false;
5187   }
5188
5189   // The register offset is optionally preceded by a '+' or '-'
5190   bool isNegative = false;
5191   if (Parser.getTok().is(AsmToken::Minus)) {
5192     isNegative = true;
5193     Parser.Lex(); // Eat the '-'.
5194   } else if (Parser.getTok().is(AsmToken::Plus)) {
5195     // Nothing to do.
5196     Parser.Lex(); // Eat the '+'.
5197   }
5198
5199   E = Parser.getTok().getLoc();
5200   int OffsetRegNum = tryParseRegister();
5201   if (OffsetRegNum == -1)
5202     return Error(E, "register expected");
5203
5204   // If there's a shift operator, handle it.
5205   ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
5206   unsigned ShiftImm = 0;
5207   if (Parser.getTok().is(AsmToken::Comma)) {
5208     Parser.Lex(); // Eat the ','.
5209     if (parseMemRegOffsetShift(ShiftType, ShiftImm))
5210       return true;
5211   }
5212
5213   // Now we should have the closing ']'
5214   if (Parser.getTok().isNot(AsmToken::RBrac))
5215     return Error(Parser.getTok().getLoc(), "']' expected");
5216   E = Parser.getTok().getEndLoc();
5217   Parser.Lex(); // Eat right bracket token.
5218
5219   Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
5220                                            ShiftType, ShiftImm, 0, isNegative,
5221                                            S, E));
5222
5223   // If there's a pre-indexing writeback marker, '!', just add it as a token
5224   // operand.
5225   if (Parser.getTok().is(AsmToken::Exclaim)) {
5226     Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5227     Parser.Lex(); // Eat the '!'.
5228   }
5229
5230   return false;
5231 }
5232
5233 /// parseMemRegOffsetShift - one of these two:
5234 ///   ( lsl | lsr | asr | ror ) , # shift_amount
5235 ///   rrx
5236 /// return true if it parses a shift otherwise it returns false.
5237 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
5238                                           unsigned &Amount) {
5239   MCAsmParser &Parser = getParser();
5240   SMLoc Loc = Parser.getTok().getLoc();
5241   const AsmToken &Tok = Parser.getTok();
5242   if (Tok.isNot(AsmToken::Identifier))
5243     return Error(Loc, "illegal shift operator");
5244   StringRef ShiftName = Tok.getString();
5245   if (ShiftName == "lsl" || ShiftName == "LSL" ||
5246       ShiftName == "asl" || ShiftName == "ASL")
5247     St = ARM_AM::lsl;
5248   else if (ShiftName == "lsr" || ShiftName == "LSR")
5249     St = ARM_AM::lsr;
5250   else if (ShiftName == "asr" || ShiftName == "ASR")
5251     St = ARM_AM::asr;
5252   else if (ShiftName == "ror" || ShiftName == "ROR")
5253     St = ARM_AM::ror;
5254   else if (ShiftName == "rrx" || ShiftName == "RRX")
5255     St = ARM_AM::rrx;
5256   else
5257     return Error(Loc, "illegal shift operator");
5258   Parser.Lex(); // Eat shift type token.
5259
5260   // rrx stands alone.
5261   Amount = 0;
5262   if (St != ARM_AM::rrx) {
5263     Loc = Parser.getTok().getLoc();
5264     // A '#' and a shift amount.
5265     const AsmToken &HashTok = Parser.getTok();
5266     if (HashTok.isNot(AsmToken::Hash) &&
5267         HashTok.isNot(AsmToken::Dollar))
5268       return Error(HashTok.getLoc(), "'#' expected");
5269     Parser.Lex(); // Eat hash token.
5270
5271     const MCExpr *Expr;
5272     if (getParser().parseExpression(Expr))
5273       return true;
5274     // Range check the immediate.
5275     // lsl, ror: 0 <= imm <= 31
5276     // lsr, asr: 0 <= imm <= 32
5277     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
5278     if (!CE)
5279       return Error(Loc, "shift amount must be an immediate");
5280     int64_t Imm = CE->getValue();
5281     if (Imm < 0 ||
5282         ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
5283         ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
5284       return Error(Loc, "immediate shift value out of range");
5285     // If <ShiftTy> #0, turn it into a no_shift.
5286     if (Imm == 0)
5287       St = ARM_AM::lsl;
5288     // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
5289     if (Imm == 32)
5290       Imm = 0;
5291     Amount = Imm;
5292   }
5293
5294   return false;
5295 }
5296
5297 /// parseFPImm - A floating point immediate expression operand.
5298 OperandMatchResultTy
5299 ARMAsmParser::parseFPImm(OperandVector &Operands) {
5300   MCAsmParser &Parser = getParser();
5301   // Anything that can accept a floating point constant as an operand
5302   // needs to go through here, as the regular parseExpression is
5303   // integer only.
5304   //
5305   // This routine still creates a generic Immediate operand, containing
5306   // a bitcast of the 64-bit floating point value. The various operands
5307   // that accept floats can check whether the value is valid for them
5308   // via the standard is*() predicates.
5309
5310   SMLoc S = Parser.getTok().getLoc();
5311
5312   if (Parser.getTok().isNot(AsmToken::Hash) &&
5313       Parser.getTok().isNot(AsmToken::Dollar))
5314     return MatchOperand_NoMatch;
5315
5316   // Disambiguate the VMOV forms that can accept an FP immediate.
5317   // vmov.f32 <sreg>, #imm
5318   // vmov.f64 <dreg>, #imm
5319   // vmov.f32 <dreg>, #imm  @ vector f32x2
5320   // vmov.f32 <qreg>, #imm  @ vector f32x4
5321   //
5322   // There are also the NEON VMOV instructions which expect an
5323   // integer constant. Make sure we don't try to parse an FPImm
5324   // for these:
5325   // vmov.i{8|16|32|64} <dreg|qreg>, #imm
5326   ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]);
5327   bool isVmovf = TyOp.isToken() &&
5328                  (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64" ||
5329                   TyOp.getToken() == ".f16");
5330   ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
5331   bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
5332                                          Mnemonic.getToken() == "fconsts");
5333   if (!(isVmovf || isFconst))
5334     return MatchOperand_NoMatch;
5335
5336   Parser.Lex(); // Eat '#' or '$'.
5337
5338   // Handle negation, as that still comes through as a separate token.
5339   bool isNegative = false;
5340   if (Parser.getTok().is(AsmToken::Minus)) {
5341     isNegative = true;
5342     Parser.Lex();
5343   }
5344   const AsmToken &Tok = Parser.getTok();
5345   SMLoc Loc = Tok.getLoc();
5346   if (Tok.is(AsmToken::Real) && isVmovf) {
5347     APFloat RealVal(APFloat::IEEEsingle(), Tok.getString());
5348     uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
5349     // If we had a '-' in front, toggle the sign bit.
5350     IntVal ^= (uint64_t)isNegative << 31;
5351     Parser.Lex(); // Eat the token.
5352     Operands.push_back(ARMOperand::CreateImm(
5353           MCConstantExpr::create(IntVal, getContext()),
5354           S, Parser.getTok().getLoc()));
5355     return MatchOperand_Success;
5356   }
5357   // Also handle plain integers. Instructions which allow floating point
5358   // immediates also allow a raw encoded 8-bit value.
5359   if (Tok.is(AsmToken::Integer) && isFconst) {
5360     int64_t Val = Tok.getIntVal();
5361     Parser.Lex(); // Eat the token.
5362     if (Val > 255 || Val < 0) {
5363       Error(Loc, "encoded floating point value out of range");
5364       return MatchOperand_ParseFail;
5365     }
5366     float RealVal = ARM_AM::getFPImmFloat(Val);
5367     Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
5368
5369     Operands.push_back(ARMOperand::CreateImm(
5370         MCConstantExpr::create(Val, getContext()), S,
5371         Parser.getTok().getLoc()));
5372     return MatchOperand_Success;
5373   }
5374
5375   Error(Loc, "invalid floating point immediate");
5376   return MatchOperand_ParseFail;
5377 }
5378
5379 /// Parse a arm instruction operand.  For now this parses the operand regardless
5380 /// of the mnemonic.
5381 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
5382   MCAsmParser &Parser = getParser();
5383   SMLoc S, E;
5384
5385   // Check if the current operand has a custom associated parser, if so, try to
5386   // custom parse the operand, or fallback to the general approach.
5387   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
5388   if (ResTy == MatchOperand_Success)
5389     return false;
5390   // If there wasn't a custom match, try the generic matcher below. Otherwise,
5391   // there was a match, but an error occurred, in which case, just return that
5392   // the operand parsing failed.
5393   if (ResTy == MatchOperand_ParseFail)
5394     return true;
5395
5396   switch (getLexer().getKind()) {
5397   default:
5398     Error(Parser.getTok().getLoc(), "unexpected token in operand");
5399     return true;
5400   case AsmToken::Identifier: {
5401     // If we've seen a branch mnemonic, the next operand must be a label.  This
5402     // is true even if the label is a register name.  So "br r1" means branch to
5403     // label "r1".
5404     bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
5405     if (!ExpectLabel) {
5406       if (!tryParseRegisterWithWriteBack(Operands))
5407         return false;
5408       int Res = tryParseShiftRegister(Operands);
5409       if (Res == 0) // success
5410         return false;
5411       else if (Res == -1) // irrecoverable error
5412         return true;
5413       // If this is VMRS, check for the apsr_nzcv operand.
5414       if (Mnemonic == "vmrs" &&
5415           Parser.getTok().getString().equals_lower("apsr_nzcv")) {
5416         S = Parser.getTok().getLoc();
5417         Parser.Lex();
5418         Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
5419         return false;
5420       }
5421     }
5422
5423     // Fall though for the Identifier case that is not a register or a
5424     // special name.
5425     LLVM_FALLTHROUGH;
5426   }
5427   case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
5428   case AsmToken::Integer: // things like 1f and 2b as a branch targets
5429   case AsmToken::String:  // quoted label names.
5430   case AsmToken::Dot: {   // . as a branch target
5431     // This was not a register so parse other operands that start with an
5432     // identifier (like labels) as expressions and create them as immediates.
5433     const MCExpr *IdVal;
5434     S = Parser.getTok().getLoc();
5435     if (getParser().parseExpression(IdVal))
5436       return true;
5437     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5438     Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
5439     return false;
5440   }
5441   case AsmToken::LBrac:
5442     return parseMemory(Operands);
5443   case AsmToken::LCurly:
5444     return parseRegisterList(Operands);
5445   case AsmToken::Dollar:
5446   case AsmToken::Hash:
5447     // #42 -> immediate.
5448     S = Parser.getTok().getLoc();
5449     Parser.Lex();
5450
5451     if (Parser.getTok().isNot(AsmToken::Colon)) {
5452       bool isNegative = Parser.getTok().is(AsmToken::Minus);
5453       const MCExpr *ImmVal;
5454       if (getParser().parseExpression(ImmVal))
5455         return true;
5456       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
5457       if (CE) {
5458         int32_t Val = CE->getValue();
5459         if (isNegative && Val == 0)
5460           ImmVal = MCConstantExpr::create(std::numeric_limits<int32_t>::min(),
5461                                           getContext());
5462       }
5463       E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5464       Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
5465
5466       // There can be a trailing '!' on operands that we want as a separate
5467       // '!' Token operand. Handle that here. For example, the compatibility
5468       // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
5469       if (Parser.getTok().is(AsmToken::Exclaim)) {
5470         Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
5471                                                    Parser.getTok().getLoc()));
5472         Parser.Lex(); // Eat exclaim token
5473       }
5474       return false;
5475     }
5476     // w/ a ':' after the '#', it's just like a plain ':'.
5477     LLVM_FALLTHROUGH;
5478
5479   case AsmToken::Colon: {
5480     S = Parser.getTok().getLoc();
5481     // ":lower16:" and ":upper16:" expression prefixes
5482     // FIXME: Check it's an expression prefix,
5483     // e.g. (FOO - :lower16:BAR) isn't legal.
5484     ARMMCExpr::VariantKind RefKind;
5485     if (parsePrefix(RefKind))
5486       return true;
5487
5488     const MCExpr *SubExprVal;
5489     if (getParser().parseExpression(SubExprVal))
5490       return true;
5491
5492     const MCExpr *ExprVal = ARMMCExpr::create(RefKind, SubExprVal,
5493                                               getContext());
5494     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5495     Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
5496     return false;
5497   }
5498   case AsmToken::Equal: {
5499     S = Parser.getTok().getLoc();
5500     if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
5501       return Error(S, "unexpected token in operand");
5502     Parser.Lex(); // Eat '='
5503     const MCExpr *SubExprVal;
5504     if (getParser().parseExpression(SubExprVal))
5505       return true;
5506     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5507
5508     // execute-only: we assume that assembly programmers know what they are
5509     // doing and allow literal pool creation here
5510     Operands.push_back(ARMOperand::CreateConstantPoolImm(SubExprVal, S, E));
5511     return false;
5512   }
5513   }
5514 }
5515
5516 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
5517 //  :lower16: and :upper16:.
5518 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
5519   MCAsmParser &Parser = getParser();
5520   RefKind = ARMMCExpr::VK_ARM_None;
5521
5522   // consume an optional '#' (GNU compatibility)
5523   if (getLexer().is(AsmToken::Hash))
5524     Parser.Lex();
5525
5526   // :lower16: and :upper16: modifiers
5527   assert(getLexer().is(AsmToken::Colon) && "expected a :");
5528   Parser.Lex(); // Eat ':'
5529
5530   if (getLexer().isNot(AsmToken::Identifier)) {
5531     Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
5532     return true;
5533   }
5534
5535   enum {
5536     COFF = (1 << MCObjectFileInfo::IsCOFF),
5537     ELF = (1 << MCObjectFileInfo::IsELF),
5538     MACHO = (1 << MCObjectFileInfo::IsMachO),
5539     WASM = (1 << MCObjectFileInfo::IsWasm),
5540   };
5541   static const struct PrefixEntry {
5542     const char *Spelling;
5543     ARMMCExpr::VariantKind VariantKind;
5544     uint8_t SupportedFormats;
5545   } PrefixEntries[] = {
5546     { "lower16", ARMMCExpr::VK_ARM_LO16, COFF | ELF | MACHO },
5547     { "upper16", ARMMCExpr::VK_ARM_HI16, COFF | ELF | MACHO },
5548   };
5549
5550   StringRef IDVal = Parser.getTok().getIdentifier();
5551
5552   const auto &Prefix =
5553       std::find_if(std::begin(PrefixEntries), std::end(PrefixEntries),
5554                    [&IDVal](const PrefixEntry &PE) {
5555                       return PE.Spelling == IDVal;
5556                    });
5557   if (Prefix == std::end(PrefixEntries)) {
5558     Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
5559     return true;
5560   }
5561
5562   uint8_t CurrentFormat;
5563   switch (getContext().getObjectFileInfo()->getObjectFileType()) {
5564   case MCObjectFileInfo::IsMachO:
5565     CurrentFormat = MACHO;
5566     break;
5567   case MCObjectFileInfo::IsELF:
5568     CurrentFormat = ELF;
5569     break;
5570   case MCObjectFileInfo::IsCOFF:
5571     CurrentFormat = COFF;
5572     break;
5573   case MCObjectFileInfo::IsWasm:
5574     CurrentFormat = WASM;
5575     break;
5576   }
5577
5578   if (~Prefix->SupportedFormats & CurrentFormat) {
5579     Error(Parser.getTok().getLoc(),
5580           "cannot represent relocation in the current file format");
5581     return true;
5582   }
5583
5584   RefKind = Prefix->VariantKind;
5585   Parser.Lex();
5586
5587   if (getLexer().isNot(AsmToken::Colon)) {
5588     Error(Parser.getTok().getLoc(), "unexpected token after prefix");
5589     return true;
5590   }
5591   Parser.Lex(); // Eat the last ':'
5592
5593   return false;
5594 }
5595
5596 /// Given a mnemonic, split out possible predication code and carry
5597 /// setting letters to form a canonical mnemonic and flags.
5598 //
5599 // FIXME: Would be nice to autogen this.
5600 // FIXME: This is a bit of a maze of special cases.
5601 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
5602                                       unsigned &PredicationCode,
5603                                       bool &CarrySetting,
5604                                       unsigned &ProcessorIMod,
5605                                       StringRef &ITMask) {
5606   PredicationCode = ARMCC::AL;
5607   CarrySetting = false;
5608   ProcessorIMod = 0;
5609
5610   // Ignore some mnemonics we know aren't predicated forms.
5611   //
5612   // FIXME: Would be nice to autogen this.
5613   if ((Mnemonic == "movs" && isThumb()) ||
5614       Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
5615       Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
5616       Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
5617       Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
5618       Mnemonic == "vaclt" || Mnemonic == "vacle"  || Mnemonic == "hlt" ||
5619       Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
5620       Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
5621       Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
5622       Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
5623       Mnemonic == "vcvta" || Mnemonic == "vcvtn"  || Mnemonic == "vcvtp" ||
5624       Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
5625       Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" ||
5626       Mnemonic.startswith("vsel") || Mnemonic == "vins" || Mnemonic == "vmovx" ||
5627       Mnemonic == "bxns"  || Mnemonic == "blxns" ||
5628       Mnemonic == "vudot" || Mnemonic == "vsdot" ||
5629       Mnemonic == "vcmla" || Mnemonic == "vcadd")
5630     return Mnemonic;
5631
5632   // First, split out any predication code. Ignore mnemonics we know aren't
5633   // predicated but do have a carry-set and so weren't caught above.
5634   if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
5635       Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
5636       Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
5637       Mnemonic != "sbcs" && Mnemonic != "rscs") {
5638     unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2));
5639     if (CC != ~0U) {
5640       Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
5641       PredicationCode = CC;
5642     }
5643   }
5644
5645   // Next, determine if we have a carry setting bit. We explicitly ignore all
5646   // the instructions we know end in 's'.
5647   if (Mnemonic.endswith("s") &&
5648       !(Mnemonic == "cps" || Mnemonic == "mls" ||
5649         Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
5650         Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
5651         Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
5652         Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
5653         Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
5654         Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
5655         Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
5656         Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
5657         Mnemonic == "bxns" || Mnemonic == "blxns" ||
5658         (Mnemonic == "movs" && isThumb()))) {
5659     Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
5660     CarrySetting = true;
5661   }
5662
5663   // The "cps" instruction can have a interrupt mode operand which is glued into
5664   // the mnemonic. Check if this is the case, split it and parse the imod op
5665   if (Mnemonic.startswith("cps")) {
5666     // Split out any imod code.
5667     unsigned IMod =
5668       StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
5669       .Case("ie", ARM_PROC::IE)
5670       .Case("id", ARM_PROC::ID)
5671       .Default(~0U);
5672     if (IMod != ~0U) {
5673       Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
5674       ProcessorIMod = IMod;
5675     }
5676   }
5677
5678   // The "it" instruction has the condition mask on the end of the mnemonic.
5679   if (Mnemonic.startswith("it")) {
5680     ITMask = Mnemonic.slice(2, Mnemonic.size());
5681     Mnemonic = Mnemonic.slice(0, 2);
5682   }
5683
5684   return Mnemonic;
5685 }
5686
5687 /// Given a canonical mnemonic, determine if the instruction ever allows
5688 /// inclusion of carry set or predication code operands.
5689 //
5690 // FIXME: It would be nice to autogen this.
5691 void ARMAsmParser::getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
5692                                          bool &CanAcceptCarrySet,
5693                                          bool &CanAcceptPredicationCode) {
5694   CanAcceptCarrySet =
5695       Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5696       Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
5697       Mnemonic == "add" || Mnemonic == "adc" || Mnemonic == "mul" ||
5698       Mnemonic == "bic" || Mnemonic == "asr" || Mnemonic == "orr" ||
5699       Mnemonic == "mvn" || Mnemonic == "rsb" || Mnemonic == "rsc" ||
5700       Mnemonic == "orn" || Mnemonic == "sbc" || Mnemonic == "eor" ||
5701       Mnemonic == "neg" || Mnemonic == "vfm" || Mnemonic == "vfnm" ||
5702       (!isThumb() &&
5703        (Mnemonic == "smull" || Mnemonic == "mov" || Mnemonic == "mla" ||
5704         Mnemonic == "smlal" || Mnemonic == "umlal" || Mnemonic == "umull"));
5705
5706   if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
5707       Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
5708       Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" ||
5709       Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") ||
5710       Mnemonic.startswith("vsel") || Mnemonic == "vmaxnm" ||
5711       Mnemonic == "vminnm" || Mnemonic == "vcvta" || Mnemonic == "vcvtn" ||
5712       Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || Mnemonic == "vrinta" ||
5713       Mnemonic == "vrintn" || Mnemonic == "vrintp" || Mnemonic == "vrintm" ||
5714       Mnemonic.startswith("aes") || Mnemonic == "hvc" || Mnemonic == "setpan" ||
5715       Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
5716       (FullInst.startswith("vmull") && FullInst.endswith(".p64")) ||
5717       Mnemonic == "vmovx" || Mnemonic == "vins" ||
5718       Mnemonic == "vudot" || Mnemonic == "vsdot" ||
5719       Mnemonic == "vcmla" || Mnemonic == "vcadd") {
5720     // These mnemonics are never predicable
5721     CanAcceptPredicationCode = false;
5722   } else if (!isThumb()) {
5723     // Some instructions are only predicable in Thumb mode
5724     CanAcceptPredicationCode =
5725         Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
5726         Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
5727         Mnemonic != "dmb" && Mnemonic != "dfb" && Mnemonic != "dsb" &&
5728         Mnemonic != "isb" && Mnemonic != "pld" && Mnemonic != "pli" &&
5729         Mnemonic != "pldw" && Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
5730         Mnemonic != "stc2" && Mnemonic != "stc2l" &&
5731         Mnemonic != "tsb" &&
5732         !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
5733   } else if (isThumbOne()) {
5734     if (hasV6MOps())
5735       CanAcceptPredicationCode = Mnemonic != "movs";
5736     else
5737       CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
5738   } else
5739     CanAcceptPredicationCode = true;
5740 }
5741
5742 // Some Thumb instructions have two operand forms that are not
5743 // available as three operand, convert to two operand form if possible.
5744 //
5745 // FIXME: We would really like to be able to tablegen'erate this.
5746 void ARMAsmParser::tryConvertingToTwoOperandForm(StringRef Mnemonic,
5747                                                  bool CarrySetting,
5748                                                  OperandVector &Operands) {
5749   if (Operands.size() != 6)
5750     return;
5751
5752   const auto &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5753         auto &Op4 = static_cast<ARMOperand &>(*Operands[4]);
5754   if (!Op3.isReg() || !Op4.isReg())
5755     return;
5756
5757   auto Op3Reg = Op3.getReg();
5758   auto Op4Reg = Op4.getReg();
5759
5760   // For most Thumb2 cases we just generate the 3 operand form and reduce
5761   // it in processInstruction(), but the 3 operand form of ADD (t2ADDrr)
5762   // won't accept SP or PC so we do the transformation here taking care
5763   // with immediate range in the 'add sp, sp #imm' case.
5764   auto &Op5 = static_cast<ARMOperand &>(*Operands[5]);
5765   if (isThumbTwo()) {
5766     if (Mnemonic != "add")
5767       return;
5768     bool TryTransform = Op3Reg == ARM::PC || Op4Reg == ARM::PC ||
5769                         (Op5.isReg() && Op5.getReg() == ARM::PC);
5770     if (!TryTransform) {
5771       TryTransform = (Op3Reg == ARM::SP || Op4Reg == ARM::SP ||
5772                       (Op5.isReg() && Op5.getReg() == ARM::SP)) &&
5773                      !(Op3Reg == ARM::SP && Op4Reg == ARM::SP &&
5774                        Op5.isImm() && !Op5.isImm0_508s4());
5775     }
5776     if (!TryTransform)
5777       return;
5778   } else if (!isThumbOne())
5779     return;
5780
5781   if (!(Mnemonic == "add" || Mnemonic == "sub" || Mnemonic == "and" ||
5782         Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5783         Mnemonic == "asr" || Mnemonic == "adc" || Mnemonic == "sbc" ||
5784         Mnemonic == "ror" || Mnemonic == "orr" || Mnemonic == "bic"))
5785     return;
5786
5787   // If first 2 operands of a 3 operand instruction are the same
5788   // then transform to 2 operand version of the same instruction
5789   // e.g. 'adds r0, r0, #1' transforms to 'adds r0, #1'
5790   bool Transform = Op3Reg == Op4Reg;
5791
5792   // For communtative operations, we might be able to transform if we swap
5793   // Op4 and Op5.  The 'ADD Rdm, SP, Rdm' form is already handled specially
5794   // as tADDrsp.
5795   const ARMOperand *LastOp = &Op5;
5796   bool Swap = false;
5797   if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() &&
5798       ((Mnemonic == "add" && Op4Reg != ARM::SP) ||
5799        Mnemonic == "and" || Mnemonic == "eor" ||
5800        Mnemonic == "adc" || Mnemonic == "orr")) {
5801     Swap = true;
5802     LastOp = &Op4;
5803     Transform = true;
5804   }
5805
5806   // If both registers are the same then remove one of them from
5807   // the operand list, with certain exceptions.
5808   if (Transform) {
5809     // Don't transform 'adds Rd, Rd, Rm' or 'sub{s} Rd, Rd, Rm' because the
5810     // 2 operand forms don't exist.
5811     if (((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub") &&
5812         LastOp->isReg())
5813       Transform = false;
5814
5815     // Don't transform 'add/sub{s} Rd, Rd, #imm' if the immediate fits into
5816     // 3-bits because the ARMARM says not to.
5817     if ((Mnemonic == "add" || Mnemonic == "sub") && LastOp->isImm0_7())
5818       Transform = false;
5819   }
5820
5821   if (Transform) {
5822     if (Swap)
5823       std::swap(Op4, Op5);
5824     Operands.erase(Operands.begin() + 3);
5825   }
5826 }
5827
5828 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
5829                                           OperandVector &Operands) {
5830   // FIXME: This is all horribly hacky. We really need a better way to deal
5831   // with optional operands like this in the matcher table.
5832
5833   // The 'mov' mnemonic is special. One variant has a cc_out operand, while
5834   // another does not. Specifically, the MOVW instruction does not. So we
5835   // special case it here and remove the defaulted (non-setting) cc_out
5836   // operand if that's the instruction we're trying to match.
5837   //
5838   // We do this as post-processing of the explicit operands rather than just
5839   // conditionally adding the cc_out in the first place because we need
5840   // to check the type of the parsed immediate operand.
5841   if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
5842       !static_cast<ARMOperand &>(*Operands[4]).isModImm() &&
5843       static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() &&
5844       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5845     return true;
5846
5847   // Register-register 'add' for thumb does not have a cc_out operand
5848   // when there are only two register operands.
5849   if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
5850       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5851       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5852       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5853     return true;
5854   // Register-register 'add' for thumb does not have a cc_out operand
5855   // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
5856   // have to check the immediate range here since Thumb2 has a variant
5857   // that can handle a different range and has a cc_out operand.
5858   if (((isThumb() && Mnemonic == "add") ||
5859        (isThumbTwo() && Mnemonic == "sub")) &&
5860       Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5861       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5862       static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP &&
5863       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5864       ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) ||
5865        static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4()))
5866     return true;
5867   // For Thumb2, add/sub immediate does not have a cc_out operand for the
5868   // imm0_4095 variant. That's the least-preferred variant when
5869   // selecting via the generic "add" mnemonic, so to know that we
5870   // should remove the cc_out operand, we have to explicitly check that
5871   // it's not one of the other variants. Ugh.
5872   if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5873       Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5874       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5875       static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5876     // Nest conditions rather than one big 'if' statement for readability.
5877     //
5878     // If both registers are low, we're in an IT block, and the immediate is
5879     // in range, we should use encoding T1 instead, which has a cc_out.
5880     if (inITBlock() &&
5881         isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) &&
5882         isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) &&
5883         static_cast<ARMOperand &>(*Operands[5]).isImm0_7())
5884       return false;
5885     // Check against T3. If the second register is the PC, this is an
5886     // alternate form of ADR, which uses encoding T4, so check for that too.
5887     if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC &&
5888         static_cast<ARMOperand &>(*Operands[5]).isT2SOImm())
5889       return false;
5890
5891     // Otherwise, we use encoding T4, which does not have a cc_out
5892     // operand.
5893     return true;
5894   }
5895
5896   // The thumb2 multiply instruction doesn't have a CCOut register, so
5897   // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5898   // use the 16-bit encoding or not.
5899   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5900       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5901       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5902       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5903       static_cast<ARMOperand &>(*Operands[5]).isReg() &&
5904       // If the registers aren't low regs, the destination reg isn't the
5905       // same as one of the source regs, or the cc_out operand is zero
5906       // outside of an IT block, we have to use the 32-bit encoding, so
5907       // remove the cc_out operand.
5908       (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5909        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5910        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) ||
5911        !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5912                             static_cast<ARMOperand &>(*Operands[5]).getReg() &&
5913                         static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5914                             static_cast<ARMOperand &>(*Operands[4]).getReg())))
5915     return true;
5916
5917   // Also check the 'mul' syntax variant that doesn't specify an explicit
5918   // destination register.
5919   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5920       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5921       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5922       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5923       // If the registers aren't low regs  or the cc_out operand is zero
5924       // outside of an IT block, we have to use the 32-bit encoding, so
5925       // remove the cc_out operand.
5926       (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5927        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5928        !inITBlock()))
5929     return true;
5930
5931   // Register-register 'add/sub' for thumb does not have a cc_out operand
5932   // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5933   // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5934   // right, this will result in better diagnostics (which operand is off)
5935   // anyway.
5936   if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5937       (Operands.size() == 5 || Operands.size() == 6) &&
5938       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5939       static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP &&
5940       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5941       (static_cast<ARMOperand &>(*Operands[4]).isImm() ||
5942        (Operands.size() == 6 &&
5943         static_cast<ARMOperand &>(*Operands[5]).isImm())))
5944     return true;
5945
5946   return false;
5947 }
5948
5949 bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic,
5950                                               OperandVector &Operands) {
5951   // VRINT{Z, X} have a predicate operand in VFP, but not in NEON
5952   unsigned RegIdx = 3;
5953   if ((Mnemonic == "vrintz" || Mnemonic == "vrintx") &&
5954       (static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32" ||
5955        static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f16")) {
5956     if (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
5957         (static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32" ||
5958          static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f16"))
5959       RegIdx = 4;
5960
5961     if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() &&
5962         (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
5963              static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) ||
5964          ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
5965              static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))
5966       return true;
5967   }
5968   return false;
5969 }
5970
5971 static bool isDataTypeToken(StringRef Tok) {
5972   return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5973     Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5974     Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5975     Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5976     Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5977     Tok == ".f" || Tok == ".d";
5978 }
5979
5980 // FIXME: This bit should probably be handled via an explicit match class
5981 // in the .td files that matches the suffix instead of having it be
5982 // a literal string token the way it is now.
5983 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5984   return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5985 }
5986
5987 static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features,
5988                                  unsigned VariantID);
5989
5990 // The GNU assembler has aliases of ldrd and strd with the second register
5991 // omitted. We don't have a way to do that in tablegen, so fix it up here.
5992 //
5993 // We have to be careful to not emit an invalid Rt2 here, because the rest of
5994 // the assmebly parser could then generate confusing diagnostics refering to
5995 // it. If we do find anything that prevents us from doing the transformation we
5996 // bail out, and let the assembly parser report an error on the instruction as
5997 // it is written.
5998 void ARMAsmParser::fixupGNULDRDAlias(StringRef Mnemonic,
5999                                      OperandVector &Operands) {
6000   if (Mnemonic != "ldrd" && Mnemonic != "strd")
6001     return;
6002   if (Operands.size() < 4)
6003     return;
6004
6005   ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
6006   ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
6007
6008   if (!Op2.isReg())
6009     return;
6010   if (!Op3.isMem())
6011     return;
6012
6013   const MCRegisterClass &GPR = MRI->getRegClass(ARM::GPRRegClassID);
6014   if (!GPR.contains(Op2.getReg()))
6015     return;
6016
6017   unsigned RtEncoding = MRI->getEncodingValue(Op2.getReg());
6018   if (!isThumb() && (RtEncoding & 1)) {
6019     // In ARM mode, the registers must be from an aligned pair, this
6020     // restriction does not apply in Thumb mode.
6021     return;
6022   }
6023   if (Op2.getReg() == ARM::PC)
6024     return;
6025   unsigned PairedReg = GPR.getRegister(RtEncoding + 1);
6026   if (!PairedReg || PairedReg == ARM::PC ||
6027       (PairedReg == ARM::SP && !hasV8Ops()))
6028     return;
6029
6030   Operands.insert(
6031       Operands.begin() + 3,
6032       ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc()));
6033 }
6034
6035 /// Parse an arm instruction mnemonic followed by its operands.
6036 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
6037                                     SMLoc NameLoc, OperandVector &Operands) {
6038   MCAsmParser &Parser = getParser();
6039
6040   // Apply mnemonic aliases before doing anything else, as the destination
6041   // mnemonic may include suffices and we want to handle them normally.
6042   // The generic tblgen'erated code does this later, at the start of
6043   // MatchInstructionImpl(), but that's too late for aliases that include
6044   // any sort of suffix.
6045   uint64_t AvailableFeatures = getAvailableFeatures();
6046   unsigned AssemblerDialect = getParser().getAssemblerDialect();
6047   applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
6048
6049   // First check for the ARM-specific .req directive.
6050   if (Parser.getTok().is(AsmToken::Identifier) &&
6051       Parser.getTok().getIdentifier() == ".req") {
6052     parseDirectiveReq(Name, NameLoc);
6053     // We always return 'error' for this, as we're done with this
6054     // statement and don't need to match the 'instruction."
6055     return true;
6056   }
6057
6058   // Create the leading tokens for the mnemonic, split by '.' characters.
6059   size_t Start = 0, Next = Name.find('.');
6060   StringRef Mnemonic = Name.slice(Start, Next);
6061
6062   // Split out the predication code and carry setting flag from the mnemonic.
6063   unsigned PredicationCode;
6064   unsigned ProcessorIMod;
6065   bool CarrySetting;
6066   StringRef ITMask;
6067   Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
6068                            ProcessorIMod, ITMask);
6069
6070   // In Thumb1, only the branch (B) instruction can be predicated.
6071   if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
6072     return Error(NameLoc, "conditional execution not supported in Thumb1");
6073   }
6074
6075   Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
6076
6077   // Handle the IT instruction ITMask. Convert it to a bitmask. This
6078   // is the mask as it will be for the IT encoding if the conditional
6079   // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
6080   // where the conditional bit0 is zero, the instruction post-processing
6081   // will adjust the mask accordingly.
6082   if (Mnemonic == "it") {
6083     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
6084     if (ITMask.size() > 3) {
6085       return Error(Loc, "too many conditions on IT instruction");
6086     }
6087     unsigned Mask = 8;
6088     for (unsigned i = ITMask.size(); i != 0; --i) {
6089       char pos = ITMask[i - 1];
6090       if (pos != 't' && pos != 'e') {
6091         return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
6092       }
6093       Mask >>= 1;
6094       if (ITMask[i - 1] == 't')
6095         Mask |= 8;
6096     }
6097     Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
6098   }
6099
6100   // FIXME: This is all a pretty gross hack. We should automatically handle
6101   // optional operands like this via tblgen.
6102
6103   // Next, add the CCOut and ConditionCode operands, if needed.
6104   //
6105   // For mnemonics which can ever incorporate a carry setting bit or predication
6106   // code, our matching model involves us always generating CCOut and
6107   // ConditionCode operands to match the mnemonic "as written" and then we let
6108   // the matcher deal with finding the right instruction or generating an
6109   // appropriate error.
6110   bool CanAcceptCarrySet, CanAcceptPredicationCode;
6111   getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
6112
6113   // If we had a carry-set on an instruction that can't do that, issue an
6114   // error.
6115   if (!CanAcceptCarrySet && CarrySetting) {
6116     return Error(NameLoc, "instruction '" + Mnemonic +
6117                  "' can not set flags, but 's' suffix specified");
6118   }
6119   // If we had a predication code on an instruction that can't do that, issue an
6120   // error.
6121   if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
6122     return Error(NameLoc, "instruction '" + Mnemonic +
6123                  "' is not predicable, but condition code specified");
6124   }
6125
6126   // Add the carry setting operand, if necessary.
6127   if (CanAcceptCarrySet) {
6128     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
6129     Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
6130                                                Loc));
6131   }
6132
6133   // Add the predication code operand, if necessary.
6134   if (CanAcceptPredicationCode) {
6135     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
6136                                       CarrySetting);
6137     Operands.push_back(ARMOperand::CreateCondCode(
6138                          ARMCC::CondCodes(PredicationCode), Loc));
6139   }
6140
6141   // Add the processor imod operand, if necessary.
6142   if (ProcessorIMod) {
6143     Operands.push_back(ARMOperand::CreateImm(
6144           MCConstantExpr::create(ProcessorIMod, getContext()),
6145                                  NameLoc, NameLoc));
6146   } else if (Mnemonic == "cps" && isMClass()) {
6147     return Error(NameLoc, "instruction 'cps' requires effect for M-class");
6148   }
6149
6150   // Add the remaining tokens in the mnemonic.
6151   while (Next != StringRef::npos) {
6152     Start = Next;
6153     Next = Name.find('.', Start + 1);
6154     StringRef ExtraToken = Name.slice(Start, Next);
6155
6156     // Some NEON instructions have an optional datatype suffix that is
6157     // completely ignored. Check for that.
6158     if (isDataTypeToken(ExtraToken) &&
6159         doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
6160       continue;
6161
6162     // For for ARM mode generate an error if the .n qualifier is used.
6163     if (ExtraToken == ".n" && !isThumb()) {
6164       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
6165       return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
6166                    "arm mode");
6167     }
6168
6169     // The .n qualifier is always discarded as that is what the tables
6170     // and matcher expect.  In ARM mode the .w qualifier has no effect,
6171     // so discard it to avoid errors that can be caused by the matcher.
6172     if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
6173       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
6174       Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
6175     }
6176   }
6177
6178   // Read the remaining operands.
6179   if (getLexer().isNot(AsmToken::EndOfStatement)) {
6180     // Read the first operand.
6181     if (parseOperand(Operands, Mnemonic)) {
6182       return true;
6183     }
6184
6185     while (parseOptionalToken(AsmToken::Comma)) {
6186       // Parse and remember the operand.
6187       if (parseOperand(Operands, Mnemonic)) {
6188         return true;
6189       }
6190     }
6191   }
6192
6193   if (parseToken(AsmToken::EndOfStatement, "unexpected token in argument list"))
6194     return true;
6195
6196   tryConvertingToTwoOperandForm(Mnemonic, CarrySetting, Operands);
6197
6198   // Some instructions, mostly Thumb, have forms for the same mnemonic that
6199   // do and don't have a cc_out optional-def operand. With some spot-checks
6200   // of the operand list, we can figure out which variant we're trying to
6201   // parse and adjust accordingly before actually matching. We shouldn't ever
6202   // try to remove a cc_out operand that was explicitly set on the
6203   // mnemonic, of course (CarrySetting == true). Reason number #317 the
6204   // table driven matcher doesn't fit well with the ARM instruction set.
6205   if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands))
6206     Operands.erase(Operands.begin() + 1);
6207
6208   // Some instructions have the same mnemonic, but don't always
6209   // have a predicate. Distinguish them here and delete the
6210   // predicate if needed.
6211   if (PredicationCode == ARMCC::AL &&
6212       shouldOmitPredicateOperand(Mnemonic, Operands))
6213     Operands.erase(Operands.begin() + 1);
6214
6215   // ARM mode 'blx' need special handling, as the register operand version
6216   // is predicable, but the label operand version is not. So, we can't rely
6217   // on the Mnemonic based checking to correctly figure out when to put
6218   // a k_CondCode operand in the list. If we're trying to match the label
6219   // version, remove the k_CondCode operand here.
6220   if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
6221       static_cast<ARMOperand &>(*Operands[2]).isImm())
6222     Operands.erase(Operands.begin() + 1);
6223
6224   // Adjust operands of ldrexd/strexd to MCK_GPRPair.
6225   // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
6226   // a single GPRPair reg operand is used in the .td file to replace the two
6227   // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
6228   // expressed as a GPRPair, so we have to manually merge them.
6229   // FIXME: We would really like to be able to tablegen'erate this.
6230   if (!isThumb() && Operands.size() > 4 &&
6231       (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
6232        Mnemonic == "stlexd")) {
6233     bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
6234     unsigned Idx = isLoad ? 2 : 3;
6235     ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]);
6236     ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]);
6237
6238     const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
6239     // Adjust only if Op1 and Op2 are GPRs.
6240     if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) &&
6241         MRC.contains(Op2.getReg())) {
6242       unsigned Reg1 = Op1.getReg();
6243       unsigned Reg2 = Op2.getReg();
6244       unsigned Rt = MRI->getEncodingValue(Reg1);
6245       unsigned Rt2 = MRI->getEncodingValue(Reg2);
6246
6247       // Rt2 must be Rt + 1 and Rt must be even.
6248       if (Rt + 1 != Rt2 || (Rt & 1)) {
6249         return Error(Op2.getStartLoc(),
6250                      isLoad ? "destination operands must be sequential"
6251                             : "source operands must be sequential");
6252       }
6253       unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
6254           &(MRI->getRegClass(ARM::GPRPairRegClassID)));
6255       Operands[Idx] =
6256           ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc());
6257       Operands.erase(Operands.begin() + Idx + 1);
6258     }
6259   }
6260
6261   // GNU Assembler extension (compatibility).
6262   fixupGNULDRDAlias(Mnemonic, Operands);
6263
6264   // FIXME: As said above, this is all a pretty gross hack.  This instruction
6265   // does not fit with other "subs" and tblgen.
6266   // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
6267   // so the Mnemonic is the original name "subs" and delete the predicate
6268   // operand so it will match the table entry.
6269   if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
6270       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6271       static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC &&
6272       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6273       static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR &&
6274       static_cast<ARMOperand &>(*Operands[5]).isImm()) {
6275     Operands.front() = ARMOperand::CreateToken(Name, NameLoc);
6276     Operands.erase(Operands.begin() + 1);
6277   }
6278   return false;
6279 }
6280
6281 // Validate context-sensitive operand constraints.
6282
6283 // return 'true' if register list contains non-low GPR registers,
6284 // 'false' otherwise. If Reg is in the register list or is HiReg, set
6285 // 'containsReg' to true.
6286 static bool checkLowRegisterList(const MCInst &Inst, unsigned OpNo,
6287                                  unsigned Reg, unsigned HiReg,
6288                                  bool &containsReg) {
6289   containsReg = false;
6290   for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
6291     unsigned OpReg = Inst.getOperand(i).getReg();
6292     if (OpReg == Reg)
6293       containsReg = true;
6294     // Anything other than a low register isn't legal here.
6295     if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
6296       return true;
6297   }
6298   return false;
6299 }
6300
6301 // Check if the specified regisgter is in the register list of the inst,
6302 // starting at the indicated operand number.
6303 static bool listContainsReg(const MCInst &Inst, unsigned OpNo, unsigned Reg) {
6304   for (unsigned i = OpNo, e = Inst.getNumOperands(); i < e; ++i) {
6305     unsigned OpReg = Inst.getOperand(i).getReg();
6306     if (OpReg == Reg)
6307       return true;
6308   }
6309   return false;
6310 }
6311
6312 // Return true if instruction has the interesting property of being
6313 // allowed in IT blocks, but not being predicable.
6314 static bool instIsBreakpoint(const MCInst &Inst) {
6315     return Inst.getOpcode() == ARM::tBKPT ||
6316            Inst.getOpcode() == ARM::BKPT ||
6317            Inst.getOpcode() == ARM::tHLT ||
6318            Inst.getOpcode() == ARM::HLT;
6319 }
6320
6321 bool ARMAsmParser::validatetLDMRegList(const MCInst &Inst,
6322                                        const OperandVector &Operands,
6323                                        unsigned ListNo, bool IsARPop) {
6324   const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
6325   bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
6326
6327   bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
6328   bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR);
6329   bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
6330
6331   if (!IsARPop && ListContainsSP)
6332     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6333                  "SP may not be in the register list");
6334   else if (ListContainsPC && ListContainsLR)
6335     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6336                  "PC and LR may not be in the register list simultaneously");
6337   return false;
6338 }
6339
6340 bool ARMAsmParser::validatetSTMRegList(const MCInst &Inst,
6341                                        const OperandVector &Operands,
6342                                        unsigned ListNo) {
6343   const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
6344   bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
6345
6346   bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
6347   bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
6348
6349   if (ListContainsSP && ListContainsPC)
6350     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6351                  "SP and PC may not be in the register list");
6352   else if (ListContainsSP)
6353     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6354                  "SP may not be in the register list");
6355   else if (ListContainsPC)
6356     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6357                  "PC may not be in the register list");
6358   return false;
6359 }
6360
6361 bool ARMAsmParser::validateLDRDSTRD(MCInst &Inst,
6362                                     const OperandVector &Operands,
6363                                     bool Load, bool ARMMode, bool Writeback) {
6364   unsigned RtIndex = Load || !Writeback ? 0 : 1;
6365   unsigned Rt = MRI->getEncodingValue(Inst.getOperand(RtIndex).getReg());
6366   unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(RtIndex + 1).getReg());
6367
6368   if (ARMMode) {
6369     // Rt can't be R14.
6370     if (Rt == 14)
6371       return Error(Operands[3]->getStartLoc(),
6372                   "Rt can't be R14");
6373
6374     // Rt must be even-numbered.
6375     if ((Rt & 1) == 1)
6376       return Error(Operands[3]->getStartLoc(),
6377                    "Rt must be even-numbered");
6378
6379     // Rt2 must be Rt + 1.
6380     if (Rt2 != Rt + 1) {
6381       if (Load)
6382         return Error(Operands[3]->getStartLoc(),
6383                      "destination operands must be sequential");
6384       else
6385         return Error(Operands[3]->getStartLoc(),
6386                      "source operands must be sequential");
6387     }
6388
6389     // FIXME: Diagnose m == 15
6390     // FIXME: Diagnose ldrd with m == t || m == t2.
6391   }
6392
6393   if (!ARMMode && Load) {
6394     if (Rt2 == Rt)
6395       return Error(Operands[3]->getStartLoc(),
6396                    "destination operands can't be identical");
6397   }
6398
6399   if (Writeback) {
6400     unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
6401
6402     if (Rn == Rt || Rn == Rt2) {
6403       if (Load)
6404         return Error(Operands[3]->getStartLoc(),
6405                      "base register needs to be different from destination "
6406                      "registers");
6407       else
6408         return Error(Operands[3]->getStartLoc(),
6409                      "source register and base register can't be identical");
6410     }
6411
6412     // FIXME: Diagnose ldrd/strd with writeback and n == 15.
6413     // (Except the immediate form of ldrd?)
6414   }
6415
6416   return false;
6417 }
6418
6419
6420 // FIXME: We would really like to be able to tablegen'erate this.
6421 bool ARMAsmParser::validateInstruction(MCInst &Inst,
6422                                        const OperandVector &Operands) {
6423   const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
6424   SMLoc Loc = Operands[0]->getStartLoc();
6425
6426   // Check the IT block state first.
6427   // NOTE: BKPT and HLT instructions have the interesting property of being
6428   // allowed in IT blocks, but not being predicable. They just always execute.
6429   if (inITBlock() && !instIsBreakpoint(Inst)) {
6430     // The instruction must be predicable.
6431     if (!MCID.isPredicable())
6432       return Error(Loc, "instructions in IT block must be predicable");
6433     ARMCC::CondCodes Cond = ARMCC::CondCodes(
6434         Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm());
6435     if (Cond != currentITCond()) {
6436       // Find the condition code Operand to get its SMLoc information.
6437       SMLoc CondLoc;
6438       for (unsigned I = 1; I < Operands.size(); ++I)
6439         if (static_cast<ARMOperand &>(*Operands[I]).isCondCode())
6440           CondLoc = Operands[I]->getStartLoc();
6441       return Error(CondLoc, "incorrect condition in IT block; got '" +
6442                                 StringRef(ARMCondCodeToString(Cond)) +
6443                                 "', but expected '" +
6444                                 ARMCondCodeToString(currentITCond()) + "'");
6445     }
6446   // Check for non-'al' condition codes outside of the IT block.
6447   } else if (isThumbTwo() && MCID.isPredicable() &&
6448              Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
6449              ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
6450              Inst.getOpcode() != ARM::t2Bcc) {
6451     return Error(Loc, "predicated instructions must be in IT block");
6452   } else if (!isThumb() && !useImplicitITARM() && MCID.isPredicable() &&
6453              Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
6454                  ARMCC::AL) {
6455     return Warning(Loc, "predicated instructions should be in IT block");
6456   }
6457
6458   // PC-setting instructions in an IT block, but not the last instruction of
6459   // the block, are UNPREDICTABLE.
6460   if (inExplicitITBlock() && !lastInITBlock() && isITBlockTerminator(Inst)) {
6461     return Error(Loc, "instruction must be outside of IT block or the last instruction in an IT block");
6462   }
6463
6464   const unsigned Opcode = Inst.getOpcode();
6465   switch (Opcode) {
6466   case ARM::t2IT: {
6467     // Encoding is unpredictable if it ever results in a notional 'NV'
6468     // predicate. Since we don't parse 'NV' directly this means an 'AL'
6469     // predicate with an "else" mask bit.
6470     unsigned Cond = Inst.getOperand(0).getImm();
6471     unsigned Mask = Inst.getOperand(1).getImm();
6472
6473     // Mask hasn't been modified to the IT instruction encoding yet so
6474     // conditions only allowing a 't' are a block of 1s starting at bit 3
6475     // followed by all 0s. Easiest way is to just list the 4 possibilities.
6476     if (Cond == ARMCC::AL && Mask != 8 && Mask != 12 && Mask != 14 &&
6477         Mask != 15)
6478       return Error(Loc, "unpredictable IT predicate sequence");
6479     break;
6480   }
6481   case ARM::LDRD:
6482     if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/true,
6483                          /*Writeback*/false))
6484       return true;
6485     break;
6486   case ARM::LDRD_PRE:
6487   case ARM::LDRD_POST:
6488     if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/true,
6489                          /*Writeback*/true))
6490       return true;
6491     break;
6492   case ARM::t2LDRDi8:
6493     if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/false,
6494                          /*Writeback*/false))
6495       return true;
6496     break;
6497   case ARM::t2LDRD_PRE:
6498   case ARM::t2LDRD_POST:
6499     if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/false,
6500                          /*Writeback*/true))
6501       return true;
6502     break;
6503   case ARM::t2BXJ: {
6504     const unsigned RmReg = Inst.getOperand(0).getReg();
6505     // Rm = SP is no longer unpredictable in v8-A
6506     if (RmReg == ARM::SP && !hasV8Ops())
6507       return Error(Operands[2]->getStartLoc(),
6508                    "r13 (SP) is an unpredictable operand to BXJ");
6509     return false;
6510   }
6511   case ARM::STRD:
6512     if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/true,
6513                          /*Writeback*/false))
6514       return true;
6515     break;
6516   case ARM::STRD_PRE:
6517   case ARM::STRD_POST:
6518     if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/true,
6519                          /*Writeback*/true))
6520       return true;
6521     break;
6522   case ARM::t2STRD_PRE:
6523   case ARM::t2STRD_POST:
6524     if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/false,
6525                          /*Writeback*/true))
6526       return true;
6527     break;
6528   case ARM::STR_PRE_IMM:
6529   case ARM::STR_PRE_REG:
6530   case ARM::t2STR_PRE:
6531   case ARM::STR_POST_IMM:
6532   case ARM::STR_POST_REG:
6533   case ARM::t2STR_POST:
6534   case ARM::STRH_PRE:
6535   case ARM::t2STRH_PRE:
6536   case ARM::STRH_POST:
6537   case ARM::t2STRH_POST:
6538   case ARM::STRB_PRE_IMM:
6539   case ARM::STRB_PRE_REG:
6540   case ARM::t2STRB_PRE:
6541   case ARM::STRB_POST_IMM:
6542   case ARM::STRB_POST_REG:
6543   case ARM::t2STRB_POST: {
6544     // Rt must be different from Rn.
6545     const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6546     const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6547
6548     if (Rt == Rn)
6549       return Error(Operands[3]->getStartLoc(),
6550                    "source register and base register can't be identical");
6551     return false;
6552   }
6553   case ARM::LDR_PRE_IMM:
6554   case ARM::LDR_PRE_REG:
6555   case ARM::t2LDR_PRE:
6556   case ARM::LDR_POST_IMM:
6557   case ARM::LDR_POST_REG:
6558   case ARM::t2LDR_POST:
6559   case ARM::LDRH_PRE:
6560   case ARM::t2LDRH_PRE:
6561   case ARM::LDRH_POST:
6562   case ARM::t2LDRH_POST:
6563   case ARM::LDRSH_PRE:
6564   case ARM::t2LDRSH_PRE:
6565   case ARM::LDRSH_POST:
6566   case ARM::t2LDRSH_POST:
6567   case ARM::LDRB_PRE_IMM:
6568   case ARM::LDRB_PRE_REG:
6569   case ARM::t2LDRB_PRE:
6570   case ARM::LDRB_POST_IMM:
6571   case ARM::LDRB_POST_REG:
6572   case ARM::t2LDRB_POST:
6573   case ARM::LDRSB_PRE:
6574   case ARM::t2LDRSB_PRE:
6575   case ARM::LDRSB_POST:
6576   case ARM::t2LDRSB_POST: {
6577     // Rt must be different from Rn.
6578     const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6579     const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6580
6581     if (Rt == Rn)
6582       return Error(Operands[3]->getStartLoc(),
6583                    "destination register and base register can't be identical");
6584     return false;
6585   }
6586   case ARM::SBFX:
6587   case ARM::t2SBFX:
6588   case ARM::UBFX:
6589   case ARM::t2UBFX: {
6590     // Width must be in range [1, 32-lsb].
6591     unsigned LSB = Inst.getOperand(2).getImm();
6592     unsigned Widthm1 = Inst.getOperand(3).getImm();
6593     if (Widthm1 >= 32 - LSB)
6594       return Error(Operands[5]->getStartLoc(),
6595                    "bitfield width must be in range [1,32-lsb]");
6596     return false;
6597   }
6598   // Notionally handles ARM::tLDMIA_UPD too.
6599   case ARM::tLDMIA: {
6600     // If we're parsing Thumb2, the .w variant is available and handles
6601     // most cases that are normally illegal for a Thumb1 LDM instruction.
6602     // We'll make the transformation in processInstruction() if necessary.
6603     //
6604     // Thumb LDM instructions are writeback iff the base register is not
6605     // in the register list.
6606     unsigned Rn = Inst.getOperand(0).getReg();
6607     bool HasWritebackToken =
6608         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
6609          static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
6610     bool ListContainsBase;
6611     if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
6612       return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
6613                    "registers must be in range r0-r7");
6614     // If we should have writeback, then there should be a '!' token.
6615     if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
6616       return Error(Operands[2]->getStartLoc(),
6617                    "writeback operator '!' expected");
6618     // If we should not have writeback, there must not be a '!'. This is
6619     // true even for the 32-bit wide encodings.
6620     if (ListContainsBase && HasWritebackToken)
6621       return Error(Operands[3]->getStartLoc(),
6622                    "writeback operator '!' not allowed when base register "
6623                    "in register list");
6624
6625     if (validatetLDMRegList(Inst, Operands, 3))
6626       return true;
6627     break;
6628   }
6629   case ARM::LDMIA_UPD:
6630   case ARM::LDMDB_UPD:
6631   case ARM::LDMIB_UPD:
6632   case ARM::LDMDA_UPD:
6633     // ARM variants loading and updating the same register are only officially
6634     // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
6635     if (!hasV7Ops())
6636       break;
6637     if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
6638       return Error(Operands.back()->getStartLoc(),
6639                    "writeback register not allowed in register list");
6640     break;
6641   case ARM::t2LDMIA:
6642   case ARM::t2LDMDB:
6643     if (validatetLDMRegList(Inst, Operands, 3))
6644       return true;
6645     break;
6646   case ARM::t2STMIA:
6647   case ARM::t2STMDB:
6648     if (validatetSTMRegList(Inst, Operands, 3))
6649       return true;
6650     break;
6651   case ARM::t2LDMIA_UPD:
6652   case ARM::t2LDMDB_UPD:
6653   case ARM::t2STMIA_UPD:
6654   case ARM::t2STMDB_UPD:
6655     if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
6656       return Error(Operands.back()->getStartLoc(),
6657                    "writeback register not allowed in register list");
6658
6659     if (Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) {
6660       if (validatetLDMRegList(Inst, Operands, 3))
6661         return true;
6662     } else {
6663       if (validatetSTMRegList(Inst, Operands, 3))
6664         return true;
6665     }
6666     break;
6667
6668   case ARM::sysLDMIA_UPD:
6669   case ARM::sysLDMDA_UPD:
6670   case ARM::sysLDMDB_UPD:
6671   case ARM::sysLDMIB_UPD:
6672     if (!listContainsReg(Inst, 3, ARM::PC))
6673       return Error(Operands[4]->getStartLoc(),
6674                    "writeback register only allowed on system LDM "
6675                    "if PC in register-list");
6676     break;
6677   case ARM::sysSTMIA_UPD:
6678   case ARM::sysSTMDA_UPD:
6679   case ARM::sysSTMDB_UPD:
6680   case ARM::sysSTMIB_UPD:
6681     return Error(Operands[2]->getStartLoc(),
6682                  "system STM cannot have writeback register");
6683   case ARM::tMUL:
6684     // The second source operand must be the same register as the destination
6685     // operand.
6686     //
6687     // In this case, we must directly check the parsed operands because the
6688     // cvtThumbMultiply() function is written in such a way that it guarantees
6689     // this first statement is always true for the new Inst.  Essentially, the
6690     // destination is unconditionally copied into the second source operand
6691     // without checking to see if it matches what we actually parsed.
6692     if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() !=
6693                                  ((ARMOperand &)*Operands[5]).getReg()) &&
6694         (((ARMOperand &)*Operands[3]).getReg() !=
6695          ((ARMOperand &)*Operands[4]).getReg())) {
6696       return Error(Operands[3]->getStartLoc(),
6697                    "destination register must match source register");
6698     }
6699     break;
6700
6701   // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
6702   // so only issue a diagnostic for thumb1. The instructions will be
6703   // switched to the t2 encodings in processInstruction() if necessary.
6704   case ARM::tPOP: {
6705     bool ListContainsBase;
6706     if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
6707         !isThumbTwo())
6708       return Error(Operands[2]->getStartLoc(),
6709                    "registers must be in range r0-r7 or pc");
6710     if (validatetLDMRegList(Inst, Operands, 2, !isMClass()))
6711       return true;
6712     break;
6713   }
6714   case ARM::tPUSH: {
6715     bool ListContainsBase;
6716     if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
6717         !isThumbTwo())
6718       return Error(Operands[2]->getStartLoc(),
6719                    "registers must be in range r0-r7 or lr");
6720     if (validatetSTMRegList(Inst, Operands, 2))
6721       return true;
6722     break;
6723   }
6724   case ARM::tSTMIA_UPD: {
6725     bool ListContainsBase, InvalidLowList;
6726     InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
6727                                           0, ListContainsBase);
6728     if (InvalidLowList && !isThumbTwo())
6729       return Error(Operands[4]->getStartLoc(),
6730                    "registers must be in range r0-r7");
6731
6732     // This would be converted to a 32-bit stm, but that's not valid if the
6733     // writeback register is in the list.
6734     if (InvalidLowList && ListContainsBase)
6735       return Error(Operands[4]->getStartLoc(),
6736                    "writeback operator '!' not allowed when base register "
6737                    "in register list");
6738
6739     if (validatetSTMRegList(Inst, Operands, 4))
6740       return true;
6741     break;
6742   }
6743   case ARM::tADDrSP:
6744     // If the non-SP source operand and the destination operand are not the
6745     // same, we need thumb2 (for the wide encoding), or we have an error.
6746     if (!isThumbTwo() &&
6747         Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
6748       return Error(Operands[4]->getStartLoc(),
6749                    "source register must be the same as destination");
6750     }
6751     break;
6752
6753   // Final range checking for Thumb unconditional branch instructions.
6754   case ARM::tB:
6755     if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>())
6756       return Error(Operands[2]->getStartLoc(), "branch target out of range");
6757     break;
6758   case ARM::t2B: {
6759     int op = (Operands[2]->isImm()) ? 2 : 3;
6760     if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>())
6761       return Error(Operands[op]->getStartLoc(), "branch target out of range");
6762     break;
6763   }
6764   // Final range checking for Thumb conditional branch instructions.
6765   case ARM::tBcc:
6766     if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>())
6767       return Error(Operands[2]->getStartLoc(), "branch target out of range");
6768     break;
6769   case ARM::t2Bcc: {
6770     int Op = (Operands[2]->isImm()) ? 2 : 3;
6771     if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>())
6772       return Error(Operands[Op]->getStartLoc(), "branch target out of range");
6773     break;
6774   }
6775   case ARM::tCBZ:
6776   case ARM::tCBNZ: {
6777     if (!static_cast<ARMOperand &>(*Operands[2]).isUnsignedOffset<6, 1>())
6778       return Error(Operands[2]->getStartLoc(), "branch target out of range");
6779     break;
6780   }
6781   case ARM::MOVi16:
6782   case ARM::MOVTi16:
6783   case ARM::t2MOVi16:
6784   case ARM::t2MOVTi16:
6785     {
6786     // We want to avoid misleadingly allowing something like "mov r0, <symbol>"
6787     // especially when we turn it into a movw and the expression <symbol> does
6788     // not have a :lower16: or :upper16 as part of the expression.  We don't
6789     // want the behavior of silently truncating, which can be unexpected and
6790     // lead to bugs that are difficult to find since this is an easy mistake
6791     // to make.
6792     int i = (Operands[3]->isImm()) ? 3 : 4;
6793     ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]);
6794     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm());
6795     if (CE) break;
6796     const MCExpr *E = dyn_cast<MCExpr>(Op.getImm());
6797     if (!E) break;
6798     const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
6799     if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
6800                        ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16))
6801       return Error(
6802           Op.getStartLoc(),
6803           "immediate expression for mov requires :lower16: or :upper16");
6804     break;
6805   }
6806   case ARM::HINT:
6807   case ARM::t2HINT: {
6808     unsigned Imm8 = Inst.getOperand(0).getImm();
6809     unsigned Pred = Inst.getOperand(1).getImm();
6810     // ESB is not predicable (pred must be AL). Without the RAS extension, this
6811     // behaves as any other unallocated hint.
6812     if (Imm8 == 0x10 && Pred != ARMCC::AL && hasRAS())
6813       return Error(Operands[1]->getStartLoc(), "instruction 'esb' is not "
6814                                                "predicable, but condition "
6815                                                "code specified");
6816     if (Imm8 == 0x14 && Pred != ARMCC::AL)
6817       return Error(Operands[1]->getStartLoc(), "instruction 'csdb' is not "
6818                                                "predicable, but condition "
6819                                                "code specified");
6820     break;
6821   }
6822   case ARM::VMOVRRS: {
6823     // Source registers must be sequential.
6824     const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6825     const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(3).getReg());
6826     if (Sm1 != Sm + 1)
6827       return Error(Operands[5]->getStartLoc(),
6828                    "source operands must be sequential");
6829     break;
6830   }
6831   case ARM::VMOVSRR: {
6832     // Destination registers must be sequential.
6833     const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6834     const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6835     if (Sm1 != Sm + 1)
6836       return Error(Operands[3]->getStartLoc(),
6837                    "destination operands must be sequential");
6838     break;
6839   }
6840   }
6841
6842   return false;
6843 }
6844
6845 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
6846   switch(Opc) {
6847   default: llvm_unreachable("unexpected opcode!");
6848   // VST1LN
6849   case ARM::VST1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
6850   case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6851   case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6852   case ARM::VST1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
6853   case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6854   case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6855   case ARM::VST1LNdAsm_8:  Spacing = 1; return ARM::VST1LNd8;
6856   case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
6857   case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
6858
6859   // VST2LN
6860   case ARM::VST2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
6861   case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6862   case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6863   case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6864   case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6865
6866   case ARM::VST2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
6867   case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6868   case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6869   case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6870   case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6871
6872   case ARM::VST2LNdAsm_8:  Spacing = 1; return ARM::VST2LNd8;
6873   case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
6874   case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
6875   case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
6876   case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
6877
6878   // VST3LN
6879   case ARM::VST3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
6880   case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6881   case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6882   case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
6883   case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6884   case ARM::VST3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
6885   case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6886   case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6887   case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
6888   case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6889   case ARM::VST3LNdAsm_8:  Spacing = 1; return ARM::VST3LNd8;
6890   case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
6891   case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
6892   case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
6893   case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
6894
6895   // VST3
6896   case ARM::VST3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
6897   case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6898   case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6899   case ARM::VST3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
6900   case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6901   case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6902   case ARM::VST3dWB_register_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
6903   case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6904   case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6905   case ARM::VST3qWB_register_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
6906   case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6907   case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6908   case ARM::VST3dAsm_8:  Spacing = 1; return ARM::VST3d8;
6909   case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
6910   case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
6911   case ARM::VST3qAsm_8:  Spacing = 2; return ARM::VST3q8;
6912   case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
6913   case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
6914
6915   // VST4LN
6916   case ARM::VST4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
6917   case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6918   case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6919   case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
6920   case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6921   case ARM::VST4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
6922   case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6923   case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6924   case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
6925   case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6926   case ARM::VST4LNdAsm_8:  Spacing = 1; return ARM::VST4LNd8;
6927   case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
6928   case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
6929   case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
6930   case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
6931
6932   // VST4
6933   case ARM::VST4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
6934   case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6935   case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6936   case ARM::VST4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
6937   case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6938   case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6939   case ARM::VST4dWB_register_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
6940   case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6941   case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6942   case ARM::VST4qWB_register_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
6943   case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6944   case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6945   case ARM::VST4dAsm_8:  Spacing = 1; return ARM::VST4d8;
6946   case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
6947   case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
6948   case ARM::VST4qAsm_8:  Spacing = 2; return ARM::VST4q8;
6949   case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
6950   case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
6951   }
6952 }
6953
6954 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
6955   switch(Opc) {
6956   default: llvm_unreachable("unexpected opcode!");
6957   // VLD1LN
6958   case ARM::VLD1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
6959   case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6960   case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6961   case ARM::VLD1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
6962   case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6963   case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6964   case ARM::VLD1LNdAsm_8:  Spacing = 1; return ARM::VLD1LNd8;
6965   case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
6966   case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
6967
6968   // VLD2LN
6969   case ARM::VLD2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
6970   case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6971   case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6972   case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
6973   case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6974   case ARM::VLD2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
6975   case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6976   case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6977   case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
6978   case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6979   case ARM::VLD2LNdAsm_8:  Spacing = 1; return ARM::VLD2LNd8;
6980   case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
6981   case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
6982   case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
6983   case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
6984
6985   // VLD3DUP
6986   case ARM::VLD3DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
6987   case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6988   case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6989   case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
6990   case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6991   case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6992   case ARM::VLD3DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
6993   case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6994   case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6995   case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
6996   case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6997   case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6998   case ARM::VLD3DUPdAsm_8:  Spacing = 1; return ARM::VLD3DUPd8;
6999   case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
7000   case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
7001   case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
7002   case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
7003   case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
7004
7005   // VLD3LN
7006   case ARM::VLD3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
7007   case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
7008   case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
7009   case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
7010   case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
7011   case ARM::VLD3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
7012   case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
7013   case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
7014   case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
7015   case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
7016   case ARM::VLD3LNdAsm_8:  Spacing = 1; return ARM::VLD3LNd8;
7017   case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
7018   case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
7019   case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
7020   case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
7021
7022   // VLD3
7023   case ARM::VLD3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
7024   case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
7025   case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
7026   case ARM::VLD3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
7027   case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
7028   case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
7029   case ARM::VLD3dWB_register_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
7030   case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
7031   case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
7032   case ARM::VLD3qWB_register_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
7033   case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
7034   case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
7035   case ARM::VLD3dAsm_8:  Spacing = 1; return ARM::VLD3d8;
7036   case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
7037   case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
7038   case ARM::VLD3qAsm_8:  Spacing = 2; return ARM::VLD3q8;
7039   case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
7040   case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
7041
7042   // VLD4LN
7043   case ARM::VLD4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
7044   case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
7045   case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
7046   case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
7047   case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
7048   case ARM::VLD4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
7049   case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
7050   case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
7051   case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
7052   case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
7053   case ARM::VLD4LNdAsm_8:  Spacing = 1; return ARM::VLD4LNd8;
7054   case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
7055   case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
7056   case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
7057   case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
7058
7059   // VLD4DUP
7060   case ARM::VLD4DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
7061   case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
7062   case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
7063   case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
7064   case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
7065   case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
7066   case ARM::VLD4DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
7067   case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
7068   case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
7069   case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
7070   case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
7071   case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
7072   case ARM::VLD4DUPdAsm_8:  Spacing = 1; return ARM::VLD4DUPd8;
7073   case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
7074   case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
7075   case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
7076   case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
7077   case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
7078
7079   // VLD4
7080   case ARM::VLD4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
7081   case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
7082   case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
7083   case ARM::VLD4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
7084   case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
7085   case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
7086   case ARM::VLD4dWB_register_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
7087   case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
7088   case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
7089   case ARM::VLD4qWB_register_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
7090   case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
7091   case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
7092   case ARM::VLD4dAsm_8:  Spacing = 1; return ARM::VLD4d8;
7093   case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
7094   case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
7095   case ARM::VLD4qAsm_8:  Spacing = 2; return ARM::VLD4q8;
7096   case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
7097   case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
7098   }
7099 }
7100
7101 bool ARMAsmParser::processInstruction(MCInst &Inst,
7102                                       const OperandVector &Operands,
7103                                       MCStreamer &Out) {
7104   // Check if we have the wide qualifier, because if it's present we
7105   // must avoid selecting a 16-bit thumb instruction.
7106   bool HasWideQualifier = false;
7107   for (auto &Op : Operands) {
7108     ARMOperand &ARMOp = static_cast<ARMOperand&>(*Op);
7109     if (ARMOp.isToken() && ARMOp.getToken() == ".w") {
7110       HasWideQualifier = true;
7111       break;
7112     }
7113   }
7114
7115   switch (Inst.getOpcode()) {
7116   // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
7117   case ARM::LDRT_POST:
7118   case ARM::LDRBT_POST: {
7119     const unsigned Opcode =
7120       (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
7121                                            : ARM::LDRBT_POST_IMM;
7122     MCInst TmpInst;
7123     TmpInst.setOpcode(Opcode);
7124     TmpInst.addOperand(Inst.getOperand(0));
7125     TmpInst.addOperand(Inst.getOperand(1));
7126     TmpInst.addOperand(Inst.getOperand(1));
7127     TmpInst.addOperand(MCOperand::createReg(0));
7128     TmpInst.addOperand(MCOperand::createImm(0));
7129     TmpInst.addOperand(Inst.getOperand(2));
7130     TmpInst.addOperand(Inst.getOperand(3));
7131     Inst = TmpInst;
7132     return true;
7133   }
7134   // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
7135   case ARM::STRT_POST:
7136   case ARM::STRBT_POST: {
7137     const unsigned Opcode =
7138       (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
7139                                            : ARM::STRBT_POST_IMM;
7140     MCInst TmpInst;
7141     TmpInst.setOpcode(Opcode);
7142     TmpInst.addOperand(Inst.getOperand(1));
7143     TmpInst.addOperand(Inst.getOperand(0));
7144     TmpInst.addOperand(Inst.getOperand(1));
7145     TmpInst.addOperand(MCOperand::createReg(0));
7146     TmpInst.addOperand(MCOperand::createImm(0));
7147     TmpInst.addOperand(Inst.getOperand(2));
7148     TmpInst.addOperand(Inst.getOperand(3));
7149     Inst = TmpInst;
7150     return true;
7151   }
7152   // Alias for alternate form of 'ADR Rd, #imm' instruction.
7153   case ARM::ADDri: {
7154     if (Inst.getOperand(1).getReg() != ARM::PC ||
7155         Inst.getOperand(5).getReg() != 0 ||
7156         !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm()))
7157       return false;
7158     MCInst TmpInst;
7159     TmpInst.setOpcode(ARM::ADR);
7160     TmpInst.addOperand(Inst.getOperand(0));
7161     if (Inst.getOperand(2).isImm()) {
7162       // Immediate (mod_imm) will be in its encoded form, we must unencode it
7163       // before passing it to the ADR instruction.
7164       unsigned Enc = Inst.getOperand(2).getImm();
7165       TmpInst.addOperand(MCOperand::createImm(
7166         ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7)));
7167     } else {
7168       // Turn PC-relative expression into absolute expression.
7169       // Reading PC provides the start of the current instruction + 8 and
7170       // the transform to adr is biased by that.
7171       MCSymbol *Dot = getContext().createTempSymbol();
7172       Out.EmitLabel(Dot);
7173       const MCExpr *OpExpr = Inst.getOperand(2).getExpr();
7174       const MCExpr *InstPC = MCSymbolRefExpr::create(Dot,
7175                                                      MCSymbolRefExpr::VK_None,
7176                                                      getContext());
7177       const MCExpr *Const8 = MCConstantExpr::create(8, getContext());
7178       const MCExpr *ReadPC = MCBinaryExpr::createAdd(InstPC, Const8,
7179                                                      getContext());
7180       const MCExpr *FixupAddr = MCBinaryExpr::createAdd(ReadPC, OpExpr,
7181                                                         getContext());
7182       TmpInst.addOperand(MCOperand::createExpr(FixupAddr));
7183     }
7184     TmpInst.addOperand(Inst.getOperand(3));
7185     TmpInst.addOperand(Inst.getOperand(4));
7186     Inst = TmpInst;
7187     return true;
7188   }
7189   // Aliases for alternate PC+imm syntax of LDR instructions.
7190   case ARM::t2LDRpcrel:
7191     // Select the narrow version if the immediate will fit.
7192     if (Inst.getOperand(1).getImm() > 0 &&
7193         Inst.getOperand(1).getImm() <= 0xff &&
7194         !HasWideQualifier)
7195       Inst.setOpcode(ARM::tLDRpci);
7196     else
7197       Inst.setOpcode(ARM::t2LDRpci);
7198     return true;
7199   case ARM::t2LDRBpcrel:
7200     Inst.setOpcode(ARM::t2LDRBpci);
7201     return true;
7202   case ARM::t2LDRHpcrel:
7203     Inst.setOpcode(ARM::t2LDRHpci);
7204     return true;
7205   case ARM::t2LDRSBpcrel:
7206     Inst.setOpcode(ARM::t2LDRSBpci);
7207     return true;
7208   case ARM::t2LDRSHpcrel:
7209     Inst.setOpcode(ARM::t2LDRSHpci);
7210     return true;
7211   case ARM::LDRConstPool:
7212   case ARM::tLDRConstPool:
7213   case ARM::t2LDRConstPool: {
7214     // Pseudo instruction ldr rt, =immediate is converted to a
7215     // MOV rt, immediate if immediate is known and representable
7216     // otherwise we create a constant pool entry that we load from.
7217     MCInst TmpInst;
7218     if (Inst.getOpcode() == ARM::LDRConstPool)
7219       TmpInst.setOpcode(ARM::LDRi12);
7220     else if (Inst.getOpcode() == ARM::tLDRConstPool)
7221       TmpInst.setOpcode(ARM::tLDRpci);
7222     else if (Inst.getOpcode() == ARM::t2LDRConstPool)
7223       TmpInst.setOpcode(ARM::t2LDRpci);
7224     const ARMOperand &PoolOperand =
7225       (HasWideQualifier ?
7226        static_cast<ARMOperand &>(*Operands[4]) :
7227        static_cast<ARMOperand &>(*Operands[3]));
7228     const MCExpr *SubExprVal = PoolOperand.getConstantPoolImm();
7229     // If SubExprVal is a constant we may be able to use a MOV
7230     if (isa<MCConstantExpr>(SubExprVal) &&
7231         Inst.getOperand(0).getReg() != ARM::PC &&
7232         Inst.getOperand(0).getReg() != ARM::SP) {
7233       int64_t Value =
7234         (int64_t) (cast<MCConstantExpr>(SubExprVal))->getValue();
7235       bool UseMov  = true;
7236       bool MovHasS = true;
7237       if (Inst.getOpcode() == ARM::LDRConstPool) {
7238         // ARM Constant
7239         if (ARM_AM::getSOImmVal(Value) != -1) {
7240           Value = ARM_AM::getSOImmVal(Value);
7241           TmpInst.setOpcode(ARM::MOVi);
7242         }
7243         else if (ARM_AM::getSOImmVal(~Value) != -1) {
7244           Value = ARM_AM::getSOImmVal(~Value);
7245           TmpInst.setOpcode(ARM::MVNi);
7246         }
7247         else if (hasV6T2Ops() &&
7248                  Value >=0 && Value < 65536) {
7249           TmpInst.setOpcode(ARM::MOVi16);
7250           MovHasS = false;
7251         }
7252         else
7253           UseMov = false;
7254       }
7255       else {
7256         // Thumb/Thumb2 Constant
7257         if (hasThumb2() &&
7258             ARM_AM::getT2SOImmVal(Value) != -1)
7259           TmpInst.setOpcode(ARM::t2MOVi);
7260         else if (hasThumb2() &&
7261                  ARM_AM::getT2SOImmVal(~Value) != -1) {
7262           TmpInst.setOpcode(ARM::t2MVNi);
7263           Value = ~Value;
7264         }
7265         else if (hasV8MBaseline() &&
7266                  Value >=0 && Value < 65536) {
7267           TmpInst.setOpcode(ARM::t2MOVi16);
7268           MovHasS = false;
7269         }
7270         else
7271           UseMov = false;
7272       }
7273       if (UseMov) {
7274         TmpInst.addOperand(Inst.getOperand(0));           // Rt
7275         TmpInst.addOperand(MCOperand::createImm(Value));  // Immediate
7276         TmpInst.addOperand(Inst.getOperand(2));           // CondCode
7277         TmpInst.addOperand(Inst.getOperand(3));           // CondCode
7278         if (MovHasS)
7279           TmpInst.addOperand(MCOperand::createReg(0));    // S
7280         Inst = TmpInst;
7281         return true;
7282       }
7283     }
7284     // No opportunity to use MOV/MVN create constant pool
7285     const MCExpr *CPLoc =
7286       getTargetStreamer().addConstantPoolEntry(SubExprVal,
7287                                                PoolOperand.getStartLoc());
7288     TmpInst.addOperand(Inst.getOperand(0));           // Rt
7289     TmpInst.addOperand(MCOperand::createExpr(CPLoc)); // offset to constpool
7290     if (TmpInst.getOpcode() == ARM::LDRi12)
7291       TmpInst.addOperand(MCOperand::createImm(0));    // unused offset
7292     TmpInst.addOperand(Inst.getOperand(2));           // CondCode
7293     TmpInst.addOperand(Inst.getOperand(3));           // CondCode
7294     Inst = TmpInst;
7295     return true;
7296   }
7297   // Handle NEON VST complex aliases.
7298   case ARM::VST1LNdWB_register_Asm_8:
7299   case ARM::VST1LNdWB_register_Asm_16:
7300   case ARM::VST1LNdWB_register_Asm_32: {
7301     MCInst TmpInst;
7302     // Shuffle the operands around so the lane index operand is in the
7303     // right place.
7304     unsigned Spacing;
7305     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7306     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7307     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7308     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7309     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7310     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7311     TmpInst.addOperand(Inst.getOperand(1)); // lane
7312     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7313     TmpInst.addOperand(Inst.getOperand(6));
7314     Inst = TmpInst;
7315     return true;
7316   }
7317
7318   case ARM::VST2LNdWB_register_Asm_8:
7319   case ARM::VST2LNdWB_register_Asm_16:
7320   case ARM::VST2LNdWB_register_Asm_32:
7321   case ARM::VST2LNqWB_register_Asm_16:
7322   case ARM::VST2LNqWB_register_Asm_32: {
7323     MCInst TmpInst;
7324     // Shuffle the operands around so the lane index operand is in the
7325     // right place.
7326     unsigned Spacing;
7327     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7328     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7329     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7330     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7331     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7332     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7333     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7334                                             Spacing));
7335     TmpInst.addOperand(Inst.getOperand(1)); // lane
7336     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7337     TmpInst.addOperand(Inst.getOperand(6));
7338     Inst = TmpInst;
7339     return true;
7340   }
7341
7342   case ARM::VST3LNdWB_register_Asm_8:
7343   case ARM::VST3LNdWB_register_Asm_16:
7344   case ARM::VST3LNdWB_register_Asm_32:
7345   case ARM::VST3LNqWB_register_Asm_16:
7346   case ARM::VST3LNqWB_register_Asm_32: {
7347     MCInst TmpInst;
7348     // Shuffle the operands around so the lane index operand is in the
7349     // right place.
7350     unsigned Spacing;
7351     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7352     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7353     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7354     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7355     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7356     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7357     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7358                                             Spacing));
7359     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7360                                             Spacing * 2));
7361     TmpInst.addOperand(Inst.getOperand(1)); // lane
7362     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7363     TmpInst.addOperand(Inst.getOperand(6));
7364     Inst = TmpInst;
7365     return true;
7366   }
7367
7368   case ARM::VST4LNdWB_register_Asm_8:
7369   case ARM::VST4LNdWB_register_Asm_16:
7370   case ARM::VST4LNdWB_register_Asm_32:
7371   case ARM::VST4LNqWB_register_Asm_16:
7372   case ARM::VST4LNqWB_register_Asm_32: {
7373     MCInst TmpInst;
7374     // Shuffle the operands around so the lane index operand is in the
7375     // right place.
7376     unsigned Spacing;
7377     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7378     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7379     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7380     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7381     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7382     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7383     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7384                                             Spacing));
7385     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7386                                             Spacing * 2));
7387     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7388                                             Spacing * 3));
7389     TmpInst.addOperand(Inst.getOperand(1)); // lane
7390     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7391     TmpInst.addOperand(Inst.getOperand(6));
7392     Inst = TmpInst;
7393     return true;
7394   }
7395
7396   case ARM::VST1LNdWB_fixed_Asm_8:
7397   case ARM::VST1LNdWB_fixed_Asm_16:
7398   case ARM::VST1LNdWB_fixed_Asm_32: {
7399     MCInst TmpInst;
7400     // Shuffle the operands around so the lane index operand is in the
7401     // right place.
7402     unsigned Spacing;
7403     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7404     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7405     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7406     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7407     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7408     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7409     TmpInst.addOperand(Inst.getOperand(1)); // lane
7410     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7411     TmpInst.addOperand(Inst.getOperand(5));
7412     Inst = TmpInst;
7413     return true;
7414   }
7415
7416   case ARM::VST2LNdWB_fixed_Asm_8:
7417   case ARM::VST2LNdWB_fixed_Asm_16:
7418   case ARM::VST2LNdWB_fixed_Asm_32:
7419   case ARM::VST2LNqWB_fixed_Asm_16:
7420   case ARM::VST2LNqWB_fixed_Asm_32: {
7421     MCInst TmpInst;
7422     // Shuffle the operands around so the lane index operand is in the
7423     // right place.
7424     unsigned Spacing;
7425     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7426     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7427     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7428     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7429     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7430     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7431     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7432                                             Spacing));
7433     TmpInst.addOperand(Inst.getOperand(1)); // lane
7434     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7435     TmpInst.addOperand(Inst.getOperand(5));
7436     Inst = TmpInst;
7437     return true;
7438   }
7439
7440   case ARM::VST3LNdWB_fixed_Asm_8:
7441   case ARM::VST3LNdWB_fixed_Asm_16:
7442   case ARM::VST3LNdWB_fixed_Asm_32:
7443   case ARM::VST3LNqWB_fixed_Asm_16:
7444   case ARM::VST3LNqWB_fixed_Asm_32: {
7445     MCInst TmpInst;
7446     // Shuffle the operands around so the lane index operand is in the
7447     // right place.
7448     unsigned Spacing;
7449     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7450     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7451     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7452     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7453     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7454     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7455     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7456                                             Spacing));
7457     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7458                                             Spacing * 2));
7459     TmpInst.addOperand(Inst.getOperand(1)); // lane
7460     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7461     TmpInst.addOperand(Inst.getOperand(5));
7462     Inst = TmpInst;
7463     return true;
7464   }
7465
7466   case ARM::VST4LNdWB_fixed_Asm_8:
7467   case ARM::VST4LNdWB_fixed_Asm_16:
7468   case ARM::VST4LNdWB_fixed_Asm_32:
7469   case ARM::VST4LNqWB_fixed_Asm_16:
7470   case ARM::VST4LNqWB_fixed_Asm_32: {
7471     MCInst TmpInst;
7472     // Shuffle the operands around so the lane index operand is in the
7473     // right place.
7474     unsigned Spacing;
7475     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7476     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7477     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7478     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7479     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7480     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7481     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7482                                             Spacing));
7483     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7484                                             Spacing * 2));
7485     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7486                                             Spacing * 3));
7487     TmpInst.addOperand(Inst.getOperand(1)); // lane
7488     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7489     TmpInst.addOperand(Inst.getOperand(5));
7490     Inst = TmpInst;
7491     return true;
7492   }
7493
7494   case ARM::VST1LNdAsm_8:
7495   case ARM::VST1LNdAsm_16:
7496   case ARM::VST1LNdAsm_32: {
7497     MCInst TmpInst;
7498     // Shuffle the operands around so the lane index operand is in the
7499     // right place.
7500     unsigned Spacing;
7501     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7502     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7503     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7504     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7505     TmpInst.addOperand(Inst.getOperand(1)); // lane
7506     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7507     TmpInst.addOperand(Inst.getOperand(5));
7508     Inst = TmpInst;
7509     return true;
7510   }
7511
7512   case ARM::VST2LNdAsm_8:
7513   case ARM::VST2LNdAsm_16:
7514   case ARM::VST2LNdAsm_32:
7515   case ARM::VST2LNqAsm_16:
7516   case ARM::VST2LNqAsm_32: {
7517     MCInst TmpInst;
7518     // Shuffle the operands around so the lane index operand is in the
7519     // right place.
7520     unsigned Spacing;
7521     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7522     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7523     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7524     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7525     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7526                                             Spacing));
7527     TmpInst.addOperand(Inst.getOperand(1)); // lane
7528     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7529     TmpInst.addOperand(Inst.getOperand(5));
7530     Inst = TmpInst;
7531     return true;
7532   }
7533
7534   case ARM::VST3LNdAsm_8:
7535   case ARM::VST3LNdAsm_16:
7536   case ARM::VST3LNdAsm_32:
7537   case ARM::VST3LNqAsm_16:
7538   case ARM::VST3LNqAsm_32: {
7539     MCInst TmpInst;
7540     // Shuffle the operands around so the lane index operand is in the
7541     // right place.
7542     unsigned Spacing;
7543     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7544     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7545     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7546     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7547     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7548                                             Spacing));
7549     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7550                                             Spacing * 2));
7551     TmpInst.addOperand(Inst.getOperand(1)); // lane
7552     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7553     TmpInst.addOperand(Inst.getOperand(5));
7554     Inst = TmpInst;
7555     return true;
7556   }
7557
7558   case ARM::VST4LNdAsm_8:
7559   case ARM::VST4LNdAsm_16:
7560   case ARM::VST4LNdAsm_32:
7561   case ARM::VST4LNqAsm_16:
7562   case ARM::VST4LNqAsm_32: {
7563     MCInst TmpInst;
7564     // Shuffle the operands around so the lane index operand is in the
7565     // right place.
7566     unsigned Spacing;
7567     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7568     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7569     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7570     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7571     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7572                                             Spacing));
7573     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7574                                             Spacing * 2));
7575     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7576                                             Spacing * 3));
7577     TmpInst.addOperand(Inst.getOperand(1)); // lane
7578     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7579     TmpInst.addOperand(Inst.getOperand(5));
7580     Inst = TmpInst;
7581     return true;
7582   }
7583
7584   // Handle NEON VLD complex aliases.
7585   case ARM::VLD1LNdWB_register_Asm_8:
7586   case ARM::VLD1LNdWB_register_Asm_16:
7587   case ARM::VLD1LNdWB_register_Asm_32: {
7588     MCInst TmpInst;
7589     // Shuffle the operands around so the lane index operand is in the
7590     // right place.
7591     unsigned Spacing;
7592     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7593     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7594     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7595     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7596     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7597     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7598     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7599     TmpInst.addOperand(Inst.getOperand(1)); // lane
7600     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7601     TmpInst.addOperand(Inst.getOperand(6));
7602     Inst = TmpInst;
7603     return true;
7604   }
7605
7606   case ARM::VLD2LNdWB_register_Asm_8:
7607   case ARM::VLD2LNdWB_register_Asm_16:
7608   case ARM::VLD2LNdWB_register_Asm_32:
7609   case ARM::VLD2LNqWB_register_Asm_16:
7610   case ARM::VLD2LNqWB_register_Asm_32: {
7611     MCInst TmpInst;
7612     // Shuffle the operands around so the lane index operand is in the
7613     // right place.
7614     unsigned Spacing;
7615     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7616     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7617     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7618                                             Spacing));
7619     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7620     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7621     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7622     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7623     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7624     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7625                                             Spacing));
7626     TmpInst.addOperand(Inst.getOperand(1)); // lane
7627     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7628     TmpInst.addOperand(Inst.getOperand(6));
7629     Inst = TmpInst;
7630     return true;
7631   }
7632
7633   case ARM::VLD3LNdWB_register_Asm_8:
7634   case ARM::VLD3LNdWB_register_Asm_16:
7635   case ARM::VLD3LNdWB_register_Asm_32:
7636   case ARM::VLD3LNqWB_register_Asm_16:
7637   case ARM::VLD3LNqWB_register_Asm_32: {
7638     MCInst TmpInst;
7639     // Shuffle the operands around so the lane index operand is in the
7640     // right place.
7641     unsigned Spacing;
7642     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7643     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7644     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7645                                             Spacing));
7646     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7647                                             Spacing * 2));
7648     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7649     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7650     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7651     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7652     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7653     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7654                                             Spacing));
7655     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7656                                             Spacing * 2));
7657     TmpInst.addOperand(Inst.getOperand(1)); // lane
7658     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7659     TmpInst.addOperand(Inst.getOperand(6));
7660     Inst = TmpInst;
7661     return true;
7662   }
7663
7664   case ARM::VLD4LNdWB_register_Asm_8:
7665   case ARM::VLD4LNdWB_register_Asm_16:
7666   case ARM::VLD4LNdWB_register_Asm_32:
7667   case ARM::VLD4LNqWB_register_Asm_16:
7668   case ARM::VLD4LNqWB_register_Asm_32: {
7669     MCInst TmpInst;
7670     // Shuffle the operands around so the lane index operand is in the
7671     // right place.
7672     unsigned Spacing;
7673     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7674     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7675     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7676                                             Spacing));
7677     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7678                                             Spacing * 2));
7679     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7680                                             Spacing * 3));
7681     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7682     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7683     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7684     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7685     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7686     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7687                                             Spacing));
7688     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7689                                             Spacing * 2));
7690     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7691                                             Spacing * 3));
7692     TmpInst.addOperand(Inst.getOperand(1)); // lane
7693     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7694     TmpInst.addOperand(Inst.getOperand(6));
7695     Inst = TmpInst;
7696     return true;
7697   }
7698
7699   case ARM::VLD1LNdWB_fixed_Asm_8:
7700   case ARM::VLD1LNdWB_fixed_Asm_16:
7701   case ARM::VLD1LNdWB_fixed_Asm_32: {
7702     MCInst TmpInst;
7703     // Shuffle the operands around so the lane index operand is in the
7704     // right place.
7705     unsigned Spacing;
7706     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7707     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7708     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7709     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7710     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7711     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7712     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7713     TmpInst.addOperand(Inst.getOperand(1)); // lane
7714     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7715     TmpInst.addOperand(Inst.getOperand(5));
7716     Inst = TmpInst;
7717     return true;
7718   }
7719
7720   case ARM::VLD2LNdWB_fixed_Asm_8:
7721   case ARM::VLD2LNdWB_fixed_Asm_16:
7722   case ARM::VLD2LNdWB_fixed_Asm_32:
7723   case ARM::VLD2LNqWB_fixed_Asm_16:
7724   case ARM::VLD2LNqWB_fixed_Asm_32: {
7725     MCInst TmpInst;
7726     // Shuffle the operands around so the lane index operand is in the
7727     // right place.
7728     unsigned Spacing;
7729     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7730     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7731     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7732                                             Spacing));
7733     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7734     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7735     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7736     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7737     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7738     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7739                                             Spacing));
7740     TmpInst.addOperand(Inst.getOperand(1)); // lane
7741     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7742     TmpInst.addOperand(Inst.getOperand(5));
7743     Inst = TmpInst;
7744     return true;
7745   }
7746
7747   case ARM::VLD3LNdWB_fixed_Asm_8:
7748   case ARM::VLD3LNdWB_fixed_Asm_16:
7749   case ARM::VLD3LNdWB_fixed_Asm_32:
7750   case ARM::VLD3LNqWB_fixed_Asm_16:
7751   case ARM::VLD3LNqWB_fixed_Asm_32: {
7752     MCInst TmpInst;
7753     // Shuffle the operands around so the lane index operand is in the
7754     // right place.
7755     unsigned Spacing;
7756     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7757     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7758     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7759                                             Spacing));
7760     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7761                                             Spacing * 2));
7762     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7763     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7764     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7765     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7766     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7767     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7768                                             Spacing));
7769     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7770                                             Spacing * 2));
7771     TmpInst.addOperand(Inst.getOperand(1)); // lane
7772     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7773     TmpInst.addOperand(Inst.getOperand(5));
7774     Inst = TmpInst;
7775     return true;
7776   }
7777
7778   case ARM::VLD4LNdWB_fixed_Asm_8:
7779   case ARM::VLD4LNdWB_fixed_Asm_16:
7780   case ARM::VLD4LNdWB_fixed_Asm_32:
7781   case ARM::VLD4LNqWB_fixed_Asm_16:
7782   case ARM::VLD4LNqWB_fixed_Asm_32: {
7783     MCInst TmpInst;
7784     // Shuffle the operands around so the lane index operand is in the
7785     // right place.
7786     unsigned Spacing;
7787     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7788     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7789     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7790                                             Spacing));
7791     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7792                                             Spacing * 2));
7793     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7794                                             Spacing * 3));
7795     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7796     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7797     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7798     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7799     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7800     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7801                                             Spacing));
7802     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7803                                             Spacing * 2));
7804     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7805                                             Spacing * 3));
7806     TmpInst.addOperand(Inst.getOperand(1)); // lane
7807     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7808     TmpInst.addOperand(Inst.getOperand(5));
7809     Inst = TmpInst;
7810     return true;
7811   }
7812
7813   case ARM::VLD1LNdAsm_8:
7814   case ARM::VLD1LNdAsm_16:
7815   case ARM::VLD1LNdAsm_32: {
7816     MCInst TmpInst;
7817     // Shuffle the operands around so the lane index operand is in the
7818     // right place.
7819     unsigned Spacing;
7820     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7821     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7822     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7823     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7824     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7825     TmpInst.addOperand(Inst.getOperand(1)); // lane
7826     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7827     TmpInst.addOperand(Inst.getOperand(5));
7828     Inst = TmpInst;
7829     return true;
7830   }
7831
7832   case ARM::VLD2LNdAsm_8:
7833   case ARM::VLD2LNdAsm_16:
7834   case ARM::VLD2LNdAsm_32:
7835   case ARM::VLD2LNqAsm_16:
7836   case ARM::VLD2LNqAsm_32: {
7837     MCInst TmpInst;
7838     // Shuffle the operands around so the lane index operand is in the
7839     // right place.
7840     unsigned Spacing;
7841     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7842     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7843     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7844                                             Spacing));
7845     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7846     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7847     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7848     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7849                                             Spacing));
7850     TmpInst.addOperand(Inst.getOperand(1)); // lane
7851     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7852     TmpInst.addOperand(Inst.getOperand(5));
7853     Inst = TmpInst;
7854     return true;
7855   }
7856
7857   case ARM::VLD3LNdAsm_8:
7858   case ARM::VLD3LNdAsm_16:
7859   case ARM::VLD3LNdAsm_32:
7860   case ARM::VLD3LNqAsm_16:
7861   case ARM::VLD3LNqAsm_32: {
7862     MCInst TmpInst;
7863     // Shuffle the operands around so the lane index operand is in the
7864     // right place.
7865     unsigned Spacing;
7866     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7867     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7868     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7869                                             Spacing));
7870     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7871                                             Spacing * 2));
7872     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7873     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7874     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7875     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7876                                             Spacing));
7877     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7878                                             Spacing * 2));
7879     TmpInst.addOperand(Inst.getOperand(1)); // lane
7880     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7881     TmpInst.addOperand(Inst.getOperand(5));
7882     Inst = TmpInst;
7883     return true;
7884   }
7885
7886   case ARM::VLD4LNdAsm_8:
7887   case ARM::VLD4LNdAsm_16:
7888   case ARM::VLD4LNdAsm_32:
7889   case ARM::VLD4LNqAsm_16:
7890   case ARM::VLD4LNqAsm_32: {
7891     MCInst TmpInst;
7892     // Shuffle the operands around so the lane index operand is in the
7893     // right place.
7894     unsigned Spacing;
7895     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7896     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7897     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7898                                             Spacing));
7899     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7900                                             Spacing * 2));
7901     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7902                                             Spacing * 3));
7903     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7904     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7905     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7906     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7907                                             Spacing));
7908     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7909                                             Spacing * 2));
7910     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7911                                             Spacing * 3));
7912     TmpInst.addOperand(Inst.getOperand(1)); // lane
7913     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7914     TmpInst.addOperand(Inst.getOperand(5));
7915     Inst = TmpInst;
7916     return true;
7917   }
7918
7919   // VLD3DUP single 3-element structure to all lanes instructions.
7920   case ARM::VLD3DUPdAsm_8:
7921   case ARM::VLD3DUPdAsm_16:
7922   case ARM::VLD3DUPdAsm_32:
7923   case ARM::VLD3DUPqAsm_8:
7924   case ARM::VLD3DUPqAsm_16:
7925   case ARM::VLD3DUPqAsm_32: {
7926     MCInst TmpInst;
7927     unsigned Spacing;
7928     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7929     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7930     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7931                                             Spacing));
7932     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7933                                             Spacing * 2));
7934     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7935     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7936     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7937     TmpInst.addOperand(Inst.getOperand(4));
7938     Inst = TmpInst;
7939     return true;
7940   }
7941
7942   case ARM::VLD3DUPdWB_fixed_Asm_8:
7943   case ARM::VLD3DUPdWB_fixed_Asm_16:
7944   case ARM::VLD3DUPdWB_fixed_Asm_32:
7945   case ARM::VLD3DUPqWB_fixed_Asm_8:
7946   case ARM::VLD3DUPqWB_fixed_Asm_16:
7947   case ARM::VLD3DUPqWB_fixed_Asm_32: {
7948     MCInst TmpInst;
7949     unsigned Spacing;
7950     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7951     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7952     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7953                                             Spacing));
7954     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7955                                             Spacing * 2));
7956     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7957     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7958     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7959     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7960     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7961     TmpInst.addOperand(Inst.getOperand(4));
7962     Inst = TmpInst;
7963     return true;
7964   }
7965
7966   case ARM::VLD3DUPdWB_register_Asm_8:
7967   case ARM::VLD3DUPdWB_register_Asm_16:
7968   case ARM::VLD3DUPdWB_register_Asm_32:
7969   case ARM::VLD3DUPqWB_register_Asm_8:
7970   case ARM::VLD3DUPqWB_register_Asm_16:
7971   case ARM::VLD3DUPqWB_register_Asm_32: {
7972     MCInst TmpInst;
7973     unsigned Spacing;
7974     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7975     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7976     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7977                                             Spacing));
7978     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7979                                             Spacing * 2));
7980     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7981     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7982     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7983     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7984     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7985     TmpInst.addOperand(Inst.getOperand(5));
7986     Inst = TmpInst;
7987     return true;
7988   }
7989
7990   // VLD3 multiple 3-element structure instructions.
7991   case ARM::VLD3dAsm_8:
7992   case ARM::VLD3dAsm_16:
7993   case ARM::VLD3dAsm_32:
7994   case ARM::VLD3qAsm_8:
7995   case ARM::VLD3qAsm_16:
7996   case ARM::VLD3qAsm_32: {
7997     MCInst TmpInst;
7998     unsigned Spacing;
7999     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8000     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8001     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8002                                             Spacing));
8003     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8004                                             Spacing * 2));
8005     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8006     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8007     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8008     TmpInst.addOperand(Inst.getOperand(4));
8009     Inst = TmpInst;
8010     return true;
8011   }
8012
8013   case ARM::VLD3dWB_fixed_Asm_8:
8014   case ARM::VLD3dWB_fixed_Asm_16:
8015   case ARM::VLD3dWB_fixed_Asm_32:
8016   case ARM::VLD3qWB_fixed_Asm_8:
8017   case ARM::VLD3qWB_fixed_Asm_16:
8018   case ARM::VLD3qWB_fixed_Asm_32: {
8019     MCInst TmpInst;
8020     unsigned Spacing;
8021     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8022     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8023     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8024                                             Spacing));
8025     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8026                                             Spacing * 2));
8027     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8028     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8029     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8030     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8031     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8032     TmpInst.addOperand(Inst.getOperand(4));
8033     Inst = TmpInst;
8034     return true;
8035   }
8036
8037   case ARM::VLD3dWB_register_Asm_8:
8038   case ARM::VLD3dWB_register_Asm_16:
8039   case ARM::VLD3dWB_register_Asm_32:
8040   case ARM::VLD3qWB_register_Asm_8:
8041   case ARM::VLD3qWB_register_Asm_16:
8042   case ARM::VLD3qWB_register_Asm_32: {
8043     MCInst TmpInst;
8044     unsigned Spacing;
8045     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8046     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8047     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8048                                             Spacing));
8049     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8050                                             Spacing * 2));
8051     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8052     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8053     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8054     TmpInst.addOperand(Inst.getOperand(3)); // Rm
8055     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8056     TmpInst.addOperand(Inst.getOperand(5));
8057     Inst = TmpInst;
8058     return true;
8059   }
8060
8061   // VLD4DUP single 3-element structure to all lanes instructions.
8062   case ARM::VLD4DUPdAsm_8:
8063   case ARM::VLD4DUPdAsm_16:
8064   case ARM::VLD4DUPdAsm_32:
8065   case ARM::VLD4DUPqAsm_8:
8066   case ARM::VLD4DUPqAsm_16:
8067   case ARM::VLD4DUPqAsm_32: {
8068     MCInst TmpInst;
8069     unsigned Spacing;
8070     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8071     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8072     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8073                                             Spacing));
8074     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8075                                             Spacing * 2));
8076     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8077                                             Spacing * 3));
8078     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8079     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8080     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8081     TmpInst.addOperand(Inst.getOperand(4));
8082     Inst = TmpInst;
8083     return true;
8084   }
8085
8086   case ARM::VLD4DUPdWB_fixed_Asm_8:
8087   case ARM::VLD4DUPdWB_fixed_Asm_16:
8088   case ARM::VLD4DUPdWB_fixed_Asm_32:
8089   case ARM::VLD4DUPqWB_fixed_Asm_8:
8090   case ARM::VLD4DUPqWB_fixed_Asm_16:
8091   case ARM::VLD4DUPqWB_fixed_Asm_32: {
8092     MCInst TmpInst;
8093     unsigned Spacing;
8094     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8095     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8096     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8097                                             Spacing));
8098     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8099                                             Spacing * 2));
8100     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8101                                             Spacing * 3));
8102     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8103     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8104     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8105     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8106     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8107     TmpInst.addOperand(Inst.getOperand(4));
8108     Inst = TmpInst;
8109     return true;
8110   }
8111
8112   case ARM::VLD4DUPdWB_register_Asm_8:
8113   case ARM::VLD4DUPdWB_register_Asm_16:
8114   case ARM::VLD4DUPdWB_register_Asm_32:
8115   case ARM::VLD4DUPqWB_register_Asm_8:
8116   case ARM::VLD4DUPqWB_register_Asm_16:
8117   case ARM::VLD4DUPqWB_register_Asm_32: {
8118     MCInst TmpInst;
8119     unsigned Spacing;
8120     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8121     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8122     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8123                                             Spacing));
8124     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8125                                             Spacing * 2));
8126     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8127                                             Spacing * 3));
8128     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8129     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8130     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8131     TmpInst.addOperand(Inst.getOperand(3)); // Rm
8132     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8133     TmpInst.addOperand(Inst.getOperand(5));
8134     Inst = TmpInst;
8135     return true;
8136   }
8137
8138   // VLD4 multiple 4-element structure instructions.
8139   case ARM::VLD4dAsm_8:
8140   case ARM::VLD4dAsm_16:
8141   case ARM::VLD4dAsm_32:
8142   case ARM::VLD4qAsm_8:
8143   case ARM::VLD4qAsm_16:
8144   case ARM::VLD4qAsm_32: {
8145     MCInst TmpInst;
8146     unsigned Spacing;
8147     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8148     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8149     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8150                                             Spacing));
8151     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8152                                             Spacing * 2));
8153     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8154                                             Spacing * 3));
8155     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8156     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8157     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8158     TmpInst.addOperand(Inst.getOperand(4));
8159     Inst = TmpInst;
8160     return true;
8161   }
8162
8163   case ARM::VLD4dWB_fixed_Asm_8:
8164   case ARM::VLD4dWB_fixed_Asm_16:
8165   case ARM::VLD4dWB_fixed_Asm_32:
8166   case ARM::VLD4qWB_fixed_Asm_8:
8167   case ARM::VLD4qWB_fixed_Asm_16:
8168   case ARM::VLD4qWB_fixed_Asm_32: {
8169     MCInst TmpInst;
8170     unsigned Spacing;
8171     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8172     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8173     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8174                                             Spacing));
8175     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8176                                             Spacing * 2));
8177     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8178                                             Spacing * 3));
8179     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8180     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8181     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8182     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8183     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8184     TmpInst.addOperand(Inst.getOperand(4));
8185     Inst = TmpInst;
8186     return true;
8187   }
8188
8189   case ARM::VLD4dWB_register_Asm_8:
8190   case ARM::VLD4dWB_register_Asm_16:
8191   case ARM::VLD4dWB_register_Asm_32:
8192   case ARM::VLD4qWB_register_Asm_8:
8193   case ARM::VLD4qWB_register_Asm_16:
8194   case ARM::VLD4qWB_register_Asm_32: {
8195     MCInst TmpInst;
8196     unsigned Spacing;
8197     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8198     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8199     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8200                                             Spacing));
8201     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8202                                             Spacing * 2));
8203     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8204                                             Spacing * 3));
8205     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8206     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8207     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8208     TmpInst.addOperand(Inst.getOperand(3)); // Rm
8209     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8210     TmpInst.addOperand(Inst.getOperand(5));
8211     Inst = TmpInst;
8212     return true;
8213   }
8214
8215   // VST3 multiple 3-element structure instructions.
8216   case ARM::VST3dAsm_8:
8217   case ARM::VST3dAsm_16:
8218   case ARM::VST3dAsm_32:
8219   case ARM::VST3qAsm_8:
8220   case ARM::VST3qAsm_16:
8221   case ARM::VST3qAsm_32: {
8222     MCInst TmpInst;
8223     unsigned Spacing;
8224     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8225     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8226     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8227     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8228     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8229                                             Spacing));
8230     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8231                                             Spacing * 2));
8232     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8233     TmpInst.addOperand(Inst.getOperand(4));
8234     Inst = TmpInst;
8235     return true;
8236   }
8237
8238   case ARM::VST3dWB_fixed_Asm_8:
8239   case ARM::VST3dWB_fixed_Asm_16:
8240   case ARM::VST3dWB_fixed_Asm_32:
8241   case ARM::VST3qWB_fixed_Asm_8:
8242   case ARM::VST3qWB_fixed_Asm_16:
8243   case ARM::VST3qWB_fixed_Asm_32: {
8244     MCInst TmpInst;
8245     unsigned Spacing;
8246     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8247     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8248     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8249     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8250     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8251     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8252     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8253                                             Spacing));
8254     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8255                                             Spacing * 2));
8256     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8257     TmpInst.addOperand(Inst.getOperand(4));
8258     Inst = TmpInst;
8259     return true;
8260   }
8261
8262   case ARM::VST3dWB_register_Asm_8:
8263   case ARM::VST3dWB_register_Asm_16:
8264   case ARM::VST3dWB_register_Asm_32:
8265   case ARM::VST3qWB_register_Asm_8:
8266   case ARM::VST3qWB_register_Asm_16:
8267   case ARM::VST3qWB_register_Asm_32: {
8268     MCInst TmpInst;
8269     unsigned Spacing;
8270     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8271     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8272     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8273     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8274     TmpInst.addOperand(Inst.getOperand(3)); // Rm
8275     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8276     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8277                                             Spacing));
8278     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8279                                             Spacing * 2));
8280     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8281     TmpInst.addOperand(Inst.getOperand(5));
8282     Inst = TmpInst;
8283     return true;
8284   }
8285
8286   // VST4 multiple 3-element structure instructions.
8287   case ARM::VST4dAsm_8:
8288   case ARM::VST4dAsm_16:
8289   case ARM::VST4dAsm_32:
8290   case ARM::VST4qAsm_8:
8291   case ARM::VST4qAsm_16:
8292   case ARM::VST4qAsm_32: {
8293     MCInst TmpInst;
8294     unsigned Spacing;
8295     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8296     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8297     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8298     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8299     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8300                                             Spacing));
8301     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8302                                             Spacing * 2));
8303     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8304                                             Spacing * 3));
8305     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8306     TmpInst.addOperand(Inst.getOperand(4));
8307     Inst = TmpInst;
8308     return true;
8309   }
8310
8311   case ARM::VST4dWB_fixed_Asm_8:
8312   case ARM::VST4dWB_fixed_Asm_16:
8313   case ARM::VST4dWB_fixed_Asm_32:
8314   case ARM::VST4qWB_fixed_Asm_8:
8315   case ARM::VST4qWB_fixed_Asm_16:
8316   case ARM::VST4qWB_fixed_Asm_32: {
8317     MCInst TmpInst;
8318     unsigned Spacing;
8319     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8320     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8321     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8322     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8323     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8324     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8325     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8326                                             Spacing));
8327     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8328                                             Spacing * 2));
8329     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8330                                             Spacing * 3));
8331     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8332     TmpInst.addOperand(Inst.getOperand(4));
8333     Inst = TmpInst;
8334     return true;
8335   }
8336
8337   case ARM::VST4dWB_register_Asm_8:
8338   case ARM::VST4dWB_register_Asm_16:
8339   case ARM::VST4dWB_register_Asm_32:
8340   case ARM::VST4qWB_register_Asm_8:
8341   case ARM::VST4qWB_register_Asm_16:
8342   case ARM::VST4qWB_register_Asm_32: {
8343     MCInst TmpInst;
8344     unsigned Spacing;
8345     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8346     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8347     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8348     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8349     TmpInst.addOperand(Inst.getOperand(3)); // Rm
8350     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8351     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8352                                             Spacing));
8353     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8354                                             Spacing * 2));
8355     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8356                                             Spacing * 3));
8357     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8358     TmpInst.addOperand(Inst.getOperand(5));
8359     Inst = TmpInst;
8360     return true;
8361   }
8362
8363   // Handle encoding choice for the shift-immediate instructions.
8364   case ARM::t2LSLri:
8365   case ARM::t2LSRri:
8366   case ARM::t2ASRri:
8367     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8368         isARMLowRegister(Inst.getOperand(1).getReg()) &&
8369         Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
8370         !HasWideQualifier) {
8371       unsigned NewOpc;
8372       switch (Inst.getOpcode()) {
8373       default: llvm_unreachable("unexpected opcode");
8374       case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
8375       case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
8376       case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
8377       }
8378       // The Thumb1 operands aren't in the same order. Awesome, eh?
8379       MCInst TmpInst;
8380       TmpInst.setOpcode(NewOpc);
8381       TmpInst.addOperand(Inst.getOperand(0));
8382       TmpInst.addOperand(Inst.getOperand(5));
8383       TmpInst.addOperand(Inst.getOperand(1));
8384       TmpInst.addOperand(Inst.getOperand(2));
8385       TmpInst.addOperand(Inst.getOperand(3));
8386       TmpInst.addOperand(Inst.getOperand(4));
8387       Inst = TmpInst;
8388       return true;
8389     }
8390     return false;
8391
8392   // Handle the Thumb2 mode MOV complex aliases.
8393   case ARM::t2MOVsr:
8394   case ARM::t2MOVSsr: {
8395     // Which instruction to expand to depends on the CCOut operand and
8396     // whether we're in an IT block if the register operands are low
8397     // registers.
8398     bool isNarrow = false;
8399     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8400         isARMLowRegister(Inst.getOperand(1).getReg()) &&
8401         isARMLowRegister(Inst.getOperand(2).getReg()) &&
8402         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
8403         inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr) &&
8404         !HasWideQualifier)
8405       isNarrow = true;
8406     MCInst TmpInst;
8407     unsigned newOpc;
8408     switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
8409     default: llvm_unreachable("unexpected opcode!");
8410     case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
8411     case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
8412     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
8413     case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR   : ARM::t2RORrr; break;
8414     }
8415     TmpInst.setOpcode(newOpc);
8416     TmpInst.addOperand(Inst.getOperand(0)); // Rd
8417     if (isNarrow)
8418       TmpInst.addOperand(MCOperand::createReg(
8419           Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
8420     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8421     TmpInst.addOperand(Inst.getOperand(2)); // Rm
8422     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8423     TmpInst.addOperand(Inst.getOperand(5));
8424     if (!isNarrow)
8425       TmpInst.addOperand(MCOperand::createReg(
8426           Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
8427     Inst = TmpInst;
8428     return true;
8429   }
8430   case ARM::t2MOVsi:
8431   case ARM::t2MOVSsi: {
8432     // Which instruction to expand to depends on the CCOut operand and
8433     // whether we're in an IT block if the register operands are low
8434     // registers.
8435     bool isNarrow = false;
8436     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8437         isARMLowRegister(Inst.getOperand(1).getReg()) &&
8438         inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi) &&
8439         !HasWideQualifier)
8440       isNarrow = true;
8441     MCInst TmpInst;
8442     unsigned newOpc;
8443     unsigned Shift = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
8444     unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
8445     bool isMov = false;
8446     // MOV rd, rm, LSL #0 is actually a MOV instruction
8447     if (Shift == ARM_AM::lsl && Amount == 0) {
8448       isMov = true;
8449       // The 16-bit encoding of MOV rd, rm, LSL #N is explicitly encoding T2 of
8450       // MOV (register) in the ARMv8-A and ARMv8-M manuals, and immediate 0 is
8451       // unpredictable in an IT block so the 32-bit encoding T3 has to be used
8452       // instead.
8453       if (inITBlock()) {
8454         isNarrow = false;
8455       }
8456       newOpc = isNarrow ? ARM::tMOVSr : ARM::t2MOVr;
8457     } else {
8458       switch(Shift) {
8459       default: llvm_unreachable("unexpected opcode!");
8460       case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
8461       case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
8462       case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
8463       case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
8464       case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
8465       }
8466     }
8467     if (Amount == 32) Amount = 0;
8468     TmpInst.setOpcode(newOpc);
8469     TmpInst.addOperand(Inst.getOperand(0)); // Rd
8470     if (isNarrow && !isMov)
8471       TmpInst.addOperand(MCOperand::createReg(
8472           Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
8473     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8474     if (newOpc != ARM::t2RRX && !isMov)
8475       TmpInst.addOperand(MCOperand::createImm(Amount));
8476     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8477     TmpInst.addOperand(Inst.getOperand(4));
8478     if (!isNarrow)
8479       TmpInst.addOperand(MCOperand::createReg(
8480           Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
8481     Inst = TmpInst;
8482     return true;
8483   }
8484   // Handle the ARM mode MOV complex aliases.
8485   case ARM::ASRr:
8486   case ARM::LSRr:
8487   case ARM::LSLr:
8488   case ARM::RORr: {
8489     ARM_AM::ShiftOpc ShiftTy;
8490     switch(Inst.getOpcode()) {
8491     default: llvm_unreachable("unexpected opcode!");
8492     case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
8493     case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
8494     case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
8495     case ARM::RORr: ShiftTy = ARM_AM::ror; break;
8496     }
8497     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
8498     MCInst TmpInst;
8499     TmpInst.setOpcode(ARM::MOVsr);
8500     TmpInst.addOperand(Inst.getOperand(0)); // Rd
8501     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8502     TmpInst.addOperand(Inst.getOperand(2)); // Rm
8503     TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
8504     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8505     TmpInst.addOperand(Inst.getOperand(4));
8506     TmpInst.addOperand(Inst.getOperand(5)); // cc_out
8507     Inst = TmpInst;
8508     return true;
8509   }
8510   case ARM::ASRi:
8511   case ARM::LSRi:
8512   case ARM::LSLi:
8513   case ARM::RORi: {
8514     ARM_AM::ShiftOpc ShiftTy;
8515     switch(Inst.getOpcode()) {
8516     default: llvm_unreachable("unexpected opcode!");
8517     case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
8518     case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
8519     case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
8520     case ARM::RORi: ShiftTy = ARM_AM::ror; break;
8521     }
8522     // A shift by zero is a plain MOVr, not a MOVsi.
8523     unsigned Amt = Inst.getOperand(2).getImm();
8524     unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
8525     // A shift by 32 should be encoded as 0 when permitted
8526     if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
8527       Amt = 0;
8528     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
8529     MCInst TmpInst;
8530     TmpInst.setOpcode(Opc);
8531     TmpInst.addOperand(Inst.getOperand(0)); // Rd
8532     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8533     if (Opc == ARM::MOVsi)
8534       TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
8535     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8536     TmpInst.addOperand(Inst.getOperand(4));
8537     TmpInst.addOperand(Inst.getOperand(5)); // cc_out
8538     Inst = TmpInst;
8539     return true;
8540   }
8541   case ARM::RRXi: {
8542     unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
8543     MCInst TmpInst;
8544     TmpInst.setOpcode(ARM::MOVsi);
8545     TmpInst.addOperand(Inst.getOperand(0)); // Rd
8546     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8547     TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
8548     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8549     TmpInst.addOperand(Inst.getOperand(3));
8550     TmpInst.addOperand(Inst.getOperand(4)); // cc_out
8551     Inst = TmpInst;
8552     return true;
8553   }
8554   case ARM::t2LDMIA_UPD: {
8555     // If this is a load of a single register, then we should use
8556     // a post-indexed LDR instruction instead, per the ARM ARM.
8557     if (Inst.getNumOperands() != 5)
8558       return false;
8559     MCInst TmpInst;
8560     TmpInst.setOpcode(ARM::t2LDR_POST);
8561     TmpInst.addOperand(Inst.getOperand(4)); // Rt
8562     TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8563     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8564     TmpInst.addOperand(MCOperand::createImm(4));
8565     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8566     TmpInst.addOperand(Inst.getOperand(3));
8567     Inst = TmpInst;
8568     return true;
8569   }
8570   case ARM::t2STMDB_UPD: {
8571     // If this is a store of a single register, then we should use
8572     // a pre-indexed STR instruction instead, per the ARM ARM.
8573     if (Inst.getNumOperands() != 5)
8574       return false;
8575     MCInst TmpInst;
8576     TmpInst.setOpcode(ARM::t2STR_PRE);
8577     TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8578     TmpInst.addOperand(Inst.getOperand(4)); // Rt
8579     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8580     TmpInst.addOperand(MCOperand::createImm(-4));
8581     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8582     TmpInst.addOperand(Inst.getOperand(3));
8583     Inst = TmpInst;
8584     return true;
8585   }
8586   case ARM::LDMIA_UPD:
8587     // If this is a load of a single register via a 'pop', then we should use
8588     // a post-indexed LDR instruction instead, per the ARM ARM.
8589     if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" &&
8590         Inst.getNumOperands() == 5) {
8591       MCInst TmpInst;
8592       TmpInst.setOpcode(ARM::LDR_POST_IMM);
8593       TmpInst.addOperand(Inst.getOperand(4)); // Rt
8594       TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8595       TmpInst.addOperand(Inst.getOperand(1)); // Rn
8596       TmpInst.addOperand(MCOperand::createReg(0));  // am2offset
8597       TmpInst.addOperand(MCOperand::createImm(4));
8598       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8599       TmpInst.addOperand(Inst.getOperand(3));
8600       Inst = TmpInst;
8601       return true;
8602     }
8603     break;
8604   case ARM::STMDB_UPD:
8605     // If this is a store of a single register via a 'push', then we should use
8606     // a pre-indexed STR instruction instead, per the ARM ARM.
8607     if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" &&
8608         Inst.getNumOperands() == 5) {
8609       MCInst TmpInst;
8610       TmpInst.setOpcode(ARM::STR_PRE_IMM);
8611       TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8612       TmpInst.addOperand(Inst.getOperand(4)); // Rt
8613       TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
8614       TmpInst.addOperand(MCOperand::createImm(-4));
8615       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8616       TmpInst.addOperand(Inst.getOperand(3));
8617       Inst = TmpInst;
8618     }
8619     break;
8620   case ARM::t2ADDri12:
8621     // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
8622     // mnemonic was used (not "addw"), encoding T3 is preferred.
8623     if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "add" ||
8624         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
8625       break;
8626     Inst.setOpcode(ARM::t2ADDri);
8627     Inst.addOperand(MCOperand::createReg(0)); // cc_out
8628     break;
8629   case ARM::t2SUBri12:
8630     // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
8631     // mnemonic was used (not "subw"), encoding T3 is preferred.
8632     if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "sub" ||
8633         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
8634       break;
8635     Inst.setOpcode(ARM::t2SUBri);
8636     Inst.addOperand(MCOperand::createReg(0)); // cc_out
8637     break;
8638   case ARM::tADDi8:
8639     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
8640     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
8641     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
8642     // to encoding T1 if <Rd> is omitted."
8643     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
8644       Inst.setOpcode(ARM::tADDi3);
8645       return true;
8646     }
8647     break;
8648   case ARM::tSUBi8:
8649     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
8650     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
8651     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
8652     // to encoding T1 if <Rd> is omitted."
8653     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
8654       Inst.setOpcode(ARM::tSUBi3);
8655       return true;
8656     }
8657     break;
8658   case ARM::t2ADDri:
8659   case ARM::t2SUBri: {
8660     // If the destination and first source operand are the same, and
8661     // the flags are compatible with the current IT status, use encoding T2
8662     // instead of T3. For compatibility with the system 'as'. Make sure the
8663     // wide encoding wasn't explicit.
8664     if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
8665         !isARMLowRegister(Inst.getOperand(0).getReg()) ||
8666         (Inst.getOperand(2).isImm() &&
8667          (unsigned)Inst.getOperand(2).getImm() > 255) ||
8668         Inst.getOperand(5).getReg() != (inITBlock() ? 0 : ARM::CPSR) ||
8669         HasWideQualifier)
8670       break;
8671     MCInst TmpInst;
8672     TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
8673                       ARM::tADDi8 : ARM::tSUBi8);
8674     TmpInst.addOperand(Inst.getOperand(0));
8675     TmpInst.addOperand(Inst.getOperand(5));
8676     TmpInst.addOperand(Inst.getOperand(0));
8677     TmpInst.addOperand(Inst.getOperand(2));
8678     TmpInst.addOperand(Inst.getOperand(3));
8679     TmpInst.addOperand(Inst.getOperand(4));
8680     Inst = TmpInst;
8681     return true;
8682   }
8683   case ARM::t2ADDrr: {
8684     // If the destination and first source operand are the same, and
8685     // there's no setting of the flags, use encoding T2 instead of T3.
8686     // Note that this is only for ADD, not SUB. This mirrors the system
8687     // 'as' behaviour.  Also take advantage of ADD being commutative.
8688     // Make sure the wide encoding wasn't explicit.
8689     bool Swap = false;
8690     auto DestReg = Inst.getOperand(0).getReg();
8691     bool Transform = DestReg == Inst.getOperand(1).getReg();
8692     if (!Transform && DestReg == Inst.getOperand(2).getReg()) {
8693       Transform = true;
8694       Swap = true;
8695     }
8696     if (!Transform ||
8697         Inst.getOperand(5).getReg() != 0 ||
8698         HasWideQualifier)
8699       break;
8700     MCInst TmpInst;
8701     TmpInst.setOpcode(ARM::tADDhirr);
8702     TmpInst.addOperand(Inst.getOperand(0));
8703     TmpInst.addOperand(Inst.getOperand(0));
8704     TmpInst.addOperand(Inst.getOperand(Swap ? 1 : 2));
8705     TmpInst.addOperand(Inst.getOperand(3));
8706     TmpInst.addOperand(Inst.getOperand(4));
8707     Inst = TmpInst;
8708     return true;
8709   }
8710   case ARM::tADDrSP:
8711     // If the non-SP source operand and the destination operand are not the
8712     // same, we need to use the 32-bit encoding if it's available.
8713     if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
8714       Inst.setOpcode(ARM::t2ADDrr);
8715       Inst.addOperand(MCOperand::createReg(0)); // cc_out
8716       return true;
8717     }
8718     break;
8719   case ARM::tB:
8720     // A Thumb conditional branch outside of an IT block is a tBcc.
8721     if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
8722       Inst.setOpcode(ARM::tBcc);
8723       return true;
8724     }
8725     break;
8726   case ARM::t2B:
8727     // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
8728     if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
8729       Inst.setOpcode(ARM::t2Bcc);
8730       return true;
8731     }
8732     break;
8733   case ARM::t2Bcc:
8734     // If the conditional is AL or we're in an IT block, we really want t2B.
8735     if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
8736       Inst.setOpcode(ARM::t2B);
8737       return true;
8738     }
8739     break;
8740   case ARM::tBcc:
8741     // If the conditional is AL, we really want tB.
8742     if (Inst.getOperand(1).getImm() == ARMCC::AL) {
8743       Inst.setOpcode(ARM::tB);
8744       return true;
8745     }
8746     break;
8747   case ARM::tLDMIA: {
8748     // If the register list contains any high registers, or if the writeback
8749     // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
8750     // instead if we're in Thumb2. Otherwise, this should have generated
8751     // an error in validateInstruction().
8752     unsigned Rn = Inst.getOperand(0).getReg();
8753     bool hasWritebackToken =
8754         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8755          static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
8756     bool listContainsBase;
8757     if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
8758         (!listContainsBase && !hasWritebackToken) ||
8759         (listContainsBase && hasWritebackToken)) {
8760       // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
8761       assert(isThumbTwo());
8762       Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
8763       // If we're switching to the updating version, we need to insert
8764       // the writeback tied operand.
8765       if (hasWritebackToken)
8766         Inst.insert(Inst.begin(),
8767                     MCOperand::createReg(Inst.getOperand(0).getReg()));
8768       return true;
8769     }
8770     break;
8771   }
8772   case ARM::tSTMIA_UPD: {
8773     // If the register list contains any high registers, we need to use
8774     // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
8775     // should have generated an error in validateInstruction().
8776     unsigned Rn = Inst.getOperand(0).getReg();
8777     bool listContainsBase;
8778     if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
8779       // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
8780       assert(isThumbTwo());
8781       Inst.setOpcode(ARM::t2STMIA_UPD);
8782       return true;
8783     }
8784     break;
8785   }
8786   case ARM::tPOP: {
8787     bool listContainsBase;
8788     // If the register list contains any high registers, we need to use
8789     // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
8790     // should have generated an error in validateInstruction().
8791     if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
8792       return false;
8793     assert(isThumbTwo());
8794     Inst.setOpcode(ARM::t2LDMIA_UPD);
8795     // Add the base register and writeback operands.
8796     Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8797     Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8798     return true;
8799   }
8800   case ARM::tPUSH: {
8801     bool listContainsBase;
8802     if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
8803       return false;
8804     assert(isThumbTwo());
8805     Inst.setOpcode(ARM::t2STMDB_UPD);
8806     // Add the base register and writeback operands.
8807     Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8808     Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8809     return true;
8810   }
8811   case ARM::t2MOVi:
8812     // If we can use the 16-bit encoding and the user didn't explicitly
8813     // request the 32-bit variant, transform it here.
8814     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8815         (Inst.getOperand(1).isImm() &&
8816          (unsigned)Inst.getOperand(1).getImm() <= 255) &&
8817         Inst.getOperand(4).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
8818         !HasWideQualifier) {
8819       // The operands aren't in the same order for tMOVi8...
8820       MCInst TmpInst;
8821       TmpInst.setOpcode(ARM::tMOVi8);
8822       TmpInst.addOperand(Inst.getOperand(0));
8823       TmpInst.addOperand(Inst.getOperand(4));
8824       TmpInst.addOperand(Inst.getOperand(1));
8825       TmpInst.addOperand(Inst.getOperand(2));
8826       TmpInst.addOperand(Inst.getOperand(3));
8827       Inst = TmpInst;
8828       return true;
8829     }
8830     break;
8831
8832   case ARM::t2MOVr:
8833     // If we can use the 16-bit encoding and the user didn't explicitly
8834     // request the 32-bit variant, transform it here.
8835     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8836         isARMLowRegister(Inst.getOperand(1).getReg()) &&
8837         Inst.getOperand(2).getImm() == ARMCC::AL &&
8838         Inst.getOperand(4).getReg() == ARM::CPSR &&
8839         !HasWideQualifier) {
8840       // The operands aren't the same for tMOV[S]r... (no cc_out)
8841       MCInst TmpInst;
8842       TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
8843       TmpInst.addOperand(Inst.getOperand(0));
8844       TmpInst.addOperand(Inst.getOperand(1));
8845       TmpInst.addOperand(Inst.getOperand(2));
8846       TmpInst.addOperand(Inst.getOperand(3));
8847       Inst = TmpInst;
8848       return true;
8849     }
8850     break;
8851
8852   case ARM::t2SXTH:
8853   case ARM::t2SXTB:
8854   case ARM::t2UXTH:
8855   case ARM::t2UXTB:
8856     // If we can use the 16-bit encoding and the user didn't explicitly
8857     // request the 32-bit variant, transform it here.
8858     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8859         isARMLowRegister(Inst.getOperand(1).getReg()) &&
8860         Inst.getOperand(2).getImm() == 0 &&
8861         !HasWideQualifier) {
8862       unsigned NewOpc;
8863       switch (Inst.getOpcode()) {
8864       default: llvm_unreachable("Illegal opcode!");
8865       case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
8866       case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
8867       case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
8868       case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
8869       }
8870       // The operands aren't the same for thumb1 (no rotate operand).
8871       MCInst TmpInst;
8872       TmpInst.setOpcode(NewOpc);
8873       TmpInst.addOperand(Inst.getOperand(0));
8874       TmpInst.addOperand(Inst.getOperand(1));
8875       TmpInst.addOperand(Inst.getOperand(3));
8876       TmpInst.addOperand(Inst.getOperand(4));
8877       Inst = TmpInst;
8878       return true;
8879     }
8880     break;
8881
8882   case ARM::MOVsi: {
8883     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
8884     // rrx shifts and asr/lsr of #32 is encoded as 0
8885     if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
8886       return false;
8887     if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
8888       // Shifting by zero is accepted as a vanilla 'MOVr'
8889       MCInst TmpInst;
8890       TmpInst.setOpcode(ARM::MOVr);
8891       TmpInst.addOperand(Inst.getOperand(0));
8892       TmpInst.addOperand(Inst.getOperand(1));
8893       TmpInst.addOperand(Inst.getOperand(3));
8894       TmpInst.addOperand(Inst.getOperand(4));
8895       TmpInst.addOperand(Inst.getOperand(5));
8896       Inst = TmpInst;
8897       return true;
8898     }
8899     return false;
8900   }
8901   case ARM::ANDrsi:
8902   case ARM::ORRrsi:
8903   case ARM::EORrsi:
8904   case ARM::BICrsi:
8905   case ARM::SUBrsi:
8906   case ARM::ADDrsi: {
8907     unsigned newOpc;
8908     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
8909     if (SOpc == ARM_AM::rrx) return false;
8910     switch (Inst.getOpcode()) {
8911     default: llvm_unreachable("unexpected opcode!");
8912     case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
8913     case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
8914     case ARM::EORrsi: newOpc = ARM::EORrr; break;
8915     case ARM::BICrsi: newOpc = ARM::BICrr; break;
8916     case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
8917     case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
8918     }
8919     // If the shift is by zero, use the non-shifted instruction definition.
8920     // The exception is for right shifts, where 0 == 32
8921     if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
8922         !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
8923       MCInst TmpInst;
8924       TmpInst.setOpcode(newOpc);
8925       TmpInst.addOperand(Inst.getOperand(0));
8926       TmpInst.addOperand(Inst.getOperand(1));
8927       TmpInst.addOperand(Inst.getOperand(2));
8928       TmpInst.addOperand(Inst.getOperand(4));
8929       TmpInst.addOperand(Inst.getOperand(5));
8930       TmpInst.addOperand(Inst.getOperand(6));
8931       Inst = TmpInst;
8932       return true;
8933     }
8934     return false;
8935   }
8936   case ARM::ITasm:
8937   case ARM::t2IT: {
8938     MCOperand &MO = Inst.getOperand(1);
8939     unsigned Mask = MO.getImm();
8940     ARMCC::CondCodes Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
8941
8942     // Set up the IT block state according to the IT instruction we just
8943     // matched.
8944     assert(!inITBlock() && "nested IT blocks?!");
8945     startExplicitITBlock(Cond, Mask);
8946     MO.setImm(getITMaskEncoding());
8947     break;
8948   }
8949   case ARM::t2LSLrr:
8950   case ARM::t2LSRrr:
8951   case ARM::t2ASRrr:
8952   case ARM::t2SBCrr:
8953   case ARM::t2RORrr:
8954   case ARM::t2BICrr:
8955     // Assemblers should use the narrow encodings of these instructions when permissible.
8956     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8957          isARMLowRegister(Inst.getOperand(2).getReg())) &&
8958         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
8959         Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
8960         !HasWideQualifier) {
8961       unsigned NewOpc;
8962       switch (Inst.getOpcode()) {
8963         default: llvm_unreachable("unexpected opcode");
8964         case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
8965         case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
8966         case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
8967         case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
8968         case ARM::t2RORrr: NewOpc = ARM::tROR; break;
8969         case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
8970       }
8971       MCInst TmpInst;
8972       TmpInst.setOpcode(NewOpc);
8973       TmpInst.addOperand(Inst.getOperand(0));
8974       TmpInst.addOperand(Inst.getOperand(5));
8975       TmpInst.addOperand(Inst.getOperand(1));
8976       TmpInst.addOperand(Inst.getOperand(2));
8977       TmpInst.addOperand(Inst.getOperand(3));
8978       TmpInst.addOperand(Inst.getOperand(4));
8979       Inst = TmpInst;
8980       return true;
8981     }
8982     return false;
8983
8984   case ARM::t2ANDrr:
8985   case ARM::t2EORrr:
8986   case ARM::t2ADCrr:
8987   case ARM::t2ORRrr:
8988     // Assemblers should use the narrow encodings of these instructions when permissible.
8989     // These instructions are special in that they are commutable, so shorter encodings
8990     // are available more often.
8991     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8992          isARMLowRegister(Inst.getOperand(2).getReg())) &&
8993         (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
8994          Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
8995         Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
8996         !HasWideQualifier) {
8997       unsigned NewOpc;
8998       switch (Inst.getOpcode()) {
8999         default: llvm_unreachable("unexpected opcode");
9000         case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
9001         case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
9002         case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
9003         case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
9004       }
9005       MCInst TmpInst;
9006       TmpInst.setOpcode(NewOpc);
9007       TmpInst.addOperand(Inst.getOperand(0));
9008       TmpInst.addOperand(Inst.getOperand(5));
9009       if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
9010         TmpInst.addOperand(Inst.getOperand(1));
9011         TmpInst.addOperand(Inst.getOperand(2));
9012       } else {
9013         TmpInst.addOperand(Inst.getOperand(2));
9014         TmpInst.addOperand(Inst.getOperand(1));
9015       }
9016       TmpInst.addOperand(Inst.getOperand(3));
9017       TmpInst.addOperand(Inst.getOperand(4));
9018       Inst = TmpInst;
9019       return true;
9020     }
9021     return false;
9022   }
9023   return false;
9024 }
9025
9026 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
9027   // 16-bit thumb arithmetic instructions either require or preclude the 'S'
9028   // suffix depending on whether they're in an IT block or not.
9029   unsigned Opc = Inst.getOpcode();
9030   const MCInstrDesc &MCID = MII.get(Opc);
9031   if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
9032     assert(MCID.hasOptionalDef() &&
9033            "optionally flag setting instruction missing optional def operand");
9034     assert(MCID.NumOperands == Inst.getNumOperands() &&
9035            "operand count mismatch!");
9036     // Find the optional-def operand (cc_out).
9037     unsigned OpNo;
9038     for (OpNo = 0;
9039          !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
9040          ++OpNo)
9041       ;
9042     // If we're parsing Thumb1, reject it completely.
9043     if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
9044       return Match_RequiresFlagSetting;
9045     // If we're parsing Thumb2, which form is legal depends on whether we're
9046     // in an IT block.
9047     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
9048         !inITBlock())
9049       return Match_RequiresITBlock;
9050     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
9051         inITBlock())
9052       return Match_RequiresNotITBlock;
9053     // LSL with zero immediate is not allowed in an IT block
9054     if (Opc == ARM::tLSLri && Inst.getOperand(3).getImm() == 0 && inITBlock())
9055       return Match_RequiresNotITBlock;
9056   } else if (isThumbOne()) {
9057     // Some high-register supporting Thumb1 encodings only allow both registers
9058     // to be from r0-r7 when in Thumb2.
9059     if (Opc == ARM::tADDhirr && !hasV6MOps() &&
9060         isARMLowRegister(Inst.getOperand(1).getReg()) &&
9061         isARMLowRegister(Inst.getOperand(2).getReg()))
9062       return Match_RequiresThumb2;
9063     // Others only require ARMv6 or later.
9064     else if (Opc == ARM::tMOVr && !hasV6Ops() &&
9065              isARMLowRegister(Inst.getOperand(0).getReg()) &&
9066              isARMLowRegister(Inst.getOperand(1).getReg()))
9067       return Match_RequiresV6;
9068   }
9069
9070   // Before ARMv8 the rules for when SP is allowed in t2MOVr are more complex
9071   // than the loop below can handle, so it uses the GPRnopc register class and
9072   // we do SP handling here.
9073   if (Opc == ARM::t2MOVr && !hasV8Ops())
9074   {
9075     // SP as both source and destination is not allowed
9076     if (Inst.getOperand(0).getReg() == ARM::SP &&
9077         Inst.getOperand(1).getReg() == ARM::SP)
9078       return Match_RequiresV8;
9079     // When flags-setting SP as either source or destination is not allowed
9080     if (Inst.getOperand(4).getReg() == ARM::CPSR &&
9081         (Inst.getOperand(0).getReg() == ARM::SP ||
9082          Inst.getOperand(1).getReg() == ARM::SP))
9083       return Match_RequiresV8;
9084   }
9085
9086   // Use of SP for VMRS/VMSR is only allowed in ARM mode with the exception of
9087   // ARMv8-A.
9088   if ((Inst.getOpcode() == ARM::VMRS || Inst.getOpcode() == ARM::VMSR) &&
9089       Inst.getOperand(0).getReg() == ARM::SP && (isThumb() && !hasV8Ops()))
9090     return Match_InvalidOperand;
9091
9092   for (unsigned I = 0; I < MCID.NumOperands; ++I)
9093     if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) {
9094       // rGPRRegClass excludes PC, and also excluded SP before ARMv8
9095       if ((Inst.getOperand(I).getReg() == ARM::SP) && !hasV8Ops())
9096         return Match_RequiresV8;
9097       else if (Inst.getOperand(I).getReg() == ARM::PC)
9098         return Match_InvalidOperand;
9099     }
9100
9101   return Match_Success;
9102 }
9103
9104 namespace llvm {
9105
9106 template <> inline bool IsCPSRDead<MCInst>(const MCInst *Instr) {
9107   return true; // In an assembly source, no need to second-guess
9108 }
9109
9110 } // end namespace llvm
9111
9112 // Returns true if Inst is unpredictable if it is in and IT block, but is not
9113 // the last instruction in the block.
9114 bool ARMAsmParser::isITBlockTerminator(MCInst &Inst) const {
9115   const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
9116
9117   // All branch & call instructions terminate IT blocks with the exception of
9118   // SVC.
9119   if (MCID.isTerminator() || (MCID.isCall() && Inst.getOpcode() != ARM::tSVC) ||
9120       MCID.isReturn() || MCID.isBranch() || MCID.isIndirectBranch())
9121     return true;
9122
9123   // Any arithmetic instruction which writes to the PC also terminates the IT
9124   // block.
9125   for (unsigned OpIdx = 0; OpIdx < MCID.getNumDefs(); ++OpIdx) {
9126     MCOperand &Op = Inst.getOperand(OpIdx);
9127     if (Op.isReg() && Op.getReg() == ARM::PC)
9128       return true;
9129   }
9130
9131   if (MCID.hasImplicitDefOfPhysReg(ARM::PC, MRI))
9132     return true;
9133
9134   // Instructions with variable operand lists, which write to the variable
9135   // operands. We only care about Thumb instructions here, as ARM instructions
9136   // obviously can't be in an IT block.
9137   switch (Inst.getOpcode()) {
9138   case ARM::tLDMIA:
9139   case ARM::t2LDMIA:
9140   case ARM::t2LDMIA_UPD:
9141   case ARM::t2LDMDB:
9142   case ARM::t2LDMDB_UPD:
9143     if (listContainsReg(Inst, 3, ARM::PC))
9144       return true;
9145     break;
9146   case ARM::tPOP:
9147     if (listContainsReg(Inst, 2, ARM::PC))
9148       return true;
9149     break;
9150   }
9151
9152   return false;
9153 }
9154
9155 unsigned ARMAsmParser::MatchInstruction(OperandVector &Operands, MCInst &Inst,
9156                                           SmallVectorImpl<NearMissInfo> &NearMisses,
9157                                           bool MatchingInlineAsm,
9158                                           bool &EmitInITBlock,
9159                                           MCStreamer &Out) {
9160   // If we can't use an implicit IT block here, just match as normal.
9161   if (inExplicitITBlock() || !isThumbTwo() || !useImplicitITThumb())
9162     return MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm);
9163
9164   // Try to match the instruction in an extension of the current IT block (if
9165   // there is one).
9166   if (inImplicitITBlock()) {
9167     extendImplicitITBlock(ITState.Cond);
9168     if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) ==
9169             Match_Success) {
9170       // The match succeded, but we still have to check that the instruction is
9171       // valid in this implicit IT block.
9172       const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
9173       if (MCID.isPredicable()) {
9174         ARMCC::CondCodes InstCond =
9175             (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())
9176                 .getImm();
9177         ARMCC::CondCodes ITCond = currentITCond();
9178         if (InstCond == ITCond) {
9179           EmitInITBlock = true;
9180           return Match_Success;
9181         } else if (InstCond == ARMCC::getOppositeCondition(ITCond)) {
9182           invertCurrentITCondition();
9183           EmitInITBlock = true;
9184           return Match_Success;
9185         }
9186       }
9187     }
9188     rewindImplicitITPosition();
9189   }
9190
9191   // Finish the current IT block, and try to match outside any IT block.
9192   flushPendingInstructions(Out);
9193   unsigned PlainMatchResult =
9194       MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm);
9195   if (PlainMatchResult == Match_Success) {
9196     const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
9197     if (MCID.isPredicable()) {
9198       ARMCC::CondCodes InstCond =
9199           (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())
9200               .getImm();
9201       // Some forms of the branch instruction have their own condition code
9202       // fields, so can be conditionally executed without an IT block.
9203       if (Inst.getOpcode() == ARM::tBcc || Inst.getOpcode() == ARM::t2Bcc) {
9204         EmitInITBlock = false;
9205         return Match_Success;
9206       }
9207       if (InstCond == ARMCC::AL) {
9208         EmitInITBlock = false;
9209         return Match_Success;
9210       }
9211     } else {
9212       EmitInITBlock = false;
9213       return Match_Success;
9214     }
9215   }
9216
9217   // Try to match in a new IT block. The matcher doesn't check the actual
9218   // condition, so we create an IT block with a dummy condition, and fix it up
9219   // once we know the actual condition.
9220   startImplicitITBlock();
9221   if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) ==
9222       Match_Success) {
9223     const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
9224     if (MCID.isPredicable()) {
9225       ITState.Cond =
9226           (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())
9227               .getImm();
9228       EmitInITBlock = true;
9229       return Match_Success;
9230     }
9231   }
9232   discardImplicitITBlock();
9233
9234   // If none of these succeed, return the error we got when trying to match
9235   // outside any IT blocks.
9236   EmitInITBlock = false;
9237   return PlainMatchResult;
9238 }
9239
9240 static std::string ARMMnemonicSpellCheck(StringRef S, uint64_t FBS,
9241                                          unsigned VariantID = 0);
9242
9243 static const char *getSubtargetFeatureName(uint64_t Val);
9244 bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
9245                                            OperandVector &Operands,
9246                                            MCStreamer &Out, uint64_t &ErrorInfo,
9247                                            bool MatchingInlineAsm) {
9248   MCInst Inst;
9249   unsigned MatchResult;
9250   bool PendConditionalInstruction = false;
9251
9252   SmallVector<NearMissInfo, 4> NearMisses;
9253   MatchResult = MatchInstruction(Operands, Inst, NearMisses, MatchingInlineAsm,
9254                                  PendConditionalInstruction, Out);
9255
9256   switch (MatchResult) {
9257   case Match_Success:
9258     // Context sensitive operand constraints aren't handled by the matcher,
9259     // so check them here.
9260     if (validateInstruction(Inst, Operands)) {
9261       // Still progress the IT block, otherwise one wrong condition causes
9262       // nasty cascading errors.
9263       forwardITPosition();
9264       return true;
9265     }
9266
9267     { // processInstruction() updates inITBlock state, we need to save it away
9268       bool wasInITBlock = inITBlock();
9269
9270       // Some instructions need post-processing to, for example, tweak which
9271       // encoding is selected. Loop on it while changes happen so the
9272       // individual transformations can chain off each other. E.g.,
9273       // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
9274       while (processInstruction(Inst, Operands, Out))
9275         ;
9276
9277       // Only after the instruction is fully processed, we can validate it
9278       if (wasInITBlock && hasV8Ops() && isThumb() &&
9279           !isV8EligibleForIT(&Inst)) {
9280         Warning(IDLoc, "deprecated instruction in IT block");
9281       }
9282     }
9283
9284     // Only move forward at the very end so that everything in validate
9285     // and process gets a consistent answer about whether we're in an IT
9286     // block.
9287     forwardITPosition();
9288
9289     // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
9290     // doesn't actually encode.
9291     if (Inst.getOpcode() == ARM::ITasm)
9292       return false;
9293
9294     Inst.setLoc(IDLoc);
9295     if (PendConditionalInstruction) {
9296       PendingConditionalInsts.push_back(Inst);
9297       if (isITBlockFull() || isITBlockTerminator(Inst))
9298         flushPendingInstructions(Out);
9299     } else {
9300       Out.EmitInstruction(Inst, getSTI());
9301     }
9302     return false;
9303   case Match_NearMisses:
9304     ReportNearMisses(NearMisses, IDLoc, Operands);
9305     return true;
9306   case Match_MnemonicFail: {
9307     uint64_t FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
9308     std::string Suggestion = ARMMnemonicSpellCheck(
9309       ((ARMOperand &)*Operands[0]).getToken(), FBS);
9310     return Error(IDLoc, "invalid instruction" + Suggestion,
9311                  ((ARMOperand &)*Operands[0]).getLocRange());
9312   }
9313   }
9314
9315   llvm_unreachable("Implement any new match types added!");
9316 }
9317
9318 /// parseDirective parses the arm specific directives
9319 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
9320   const MCObjectFileInfo::Environment Format =
9321     getContext().getObjectFileInfo()->getObjectFileType();
9322   bool IsMachO = Format == MCObjectFileInfo::IsMachO;
9323   bool IsCOFF = Format == MCObjectFileInfo::IsCOFF;
9324
9325   StringRef IDVal = DirectiveID.getIdentifier();
9326   if (IDVal == ".word")
9327     parseLiteralValues(4, DirectiveID.getLoc());
9328   else if (IDVal == ".short" || IDVal == ".hword")
9329     parseLiteralValues(2, DirectiveID.getLoc());
9330   else if (IDVal == ".thumb")
9331     parseDirectiveThumb(DirectiveID.getLoc());
9332   else if (IDVal == ".arm")
9333     parseDirectiveARM(DirectiveID.getLoc());
9334   else if (IDVal == ".thumb_func")
9335     parseDirectiveThumbFunc(DirectiveID.getLoc());
9336   else if (IDVal == ".code")
9337     parseDirectiveCode(DirectiveID.getLoc());
9338   else if (IDVal == ".syntax")
9339     parseDirectiveSyntax(DirectiveID.getLoc());
9340   else if (IDVal == ".unreq")
9341     parseDirectiveUnreq(DirectiveID.getLoc());
9342   else if (IDVal == ".fnend")
9343     parseDirectiveFnEnd(DirectiveID.getLoc());
9344   else if (IDVal == ".cantunwind")
9345     parseDirectiveCantUnwind(DirectiveID.getLoc());
9346   else if (IDVal == ".personality")
9347     parseDirectivePersonality(DirectiveID.getLoc());
9348   else if (IDVal == ".handlerdata")
9349     parseDirectiveHandlerData(DirectiveID.getLoc());
9350   else if (IDVal == ".setfp")
9351     parseDirectiveSetFP(DirectiveID.getLoc());
9352   else if (IDVal == ".pad")
9353     parseDirectivePad(DirectiveID.getLoc());
9354   else if (IDVal == ".save")
9355     parseDirectiveRegSave(DirectiveID.getLoc(), false);
9356   else if (IDVal == ".vsave")
9357     parseDirectiveRegSave(DirectiveID.getLoc(), true);
9358   else if (IDVal == ".ltorg" || IDVal == ".pool")
9359     parseDirectiveLtorg(DirectiveID.getLoc());
9360   else if (IDVal == ".even")
9361     parseDirectiveEven(DirectiveID.getLoc());
9362   else if (IDVal == ".personalityindex")
9363     parseDirectivePersonalityIndex(DirectiveID.getLoc());
9364   else if (IDVal == ".unwind_raw")
9365     parseDirectiveUnwindRaw(DirectiveID.getLoc());
9366   else if (IDVal == ".movsp")
9367     parseDirectiveMovSP(DirectiveID.getLoc());
9368   else if (IDVal == ".arch_extension")
9369     parseDirectiveArchExtension(DirectiveID.getLoc());
9370   else if (IDVal == ".align")
9371     return parseDirectiveAlign(DirectiveID.getLoc()); // Use Generic on failure.
9372   else if (IDVal == ".thumb_set")
9373     parseDirectiveThumbSet(DirectiveID.getLoc());
9374   else if (IDVal == ".inst")
9375     parseDirectiveInst(DirectiveID.getLoc());
9376   else if (IDVal == ".inst.n")
9377     parseDirectiveInst(DirectiveID.getLoc(), 'n');
9378   else if (IDVal == ".inst.w")
9379     parseDirectiveInst(DirectiveID.getLoc(), 'w');
9380   else if (!IsMachO && !IsCOFF) {
9381     if (IDVal == ".arch")
9382       parseDirectiveArch(DirectiveID.getLoc());
9383     else if (IDVal == ".cpu")
9384       parseDirectiveCPU(DirectiveID.getLoc());
9385     else if (IDVal == ".eabi_attribute")
9386       parseDirectiveEabiAttr(DirectiveID.getLoc());
9387     else if (IDVal == ".fpu")
9388       parseDirectiveFPU(DirectiveID.getLoc());
9389     else if (IDVal == ".fnstart")
9390       parseDirectiveFnStart(DirectiveID.getLoc());
9391     else if (IDVal == ".object_arch")
9392       parseDirectiveObjectArch(DirectiveID.getLoc());
9393     else if (IDVal == ".tlsdescseq")
9394       parseDirectiveTLSDescSeq(DirectiveID.getLoc());
9395     else
9396       return true;
9397   } else
9398     return true;
9399   return false;
9400 }
9401
9402 /// parseLiteralValues
9403 ///  ::= .hword expression [, expression]*
9404 ///  ::= .short expression [, expression]*
9405 ///  ::= .word expression [, expression]*
9406 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
9407   auto parseOne = [&]() -> bool {
9408     const MCExpr *Value;
9409     if (getParser().parseExpression(Value))
9410       return true;
9411     getParser().getStreamer().EmitValue(Value, Size, L);
9412     return false;
9413   };
9414   return (parseMany(parseOne));
9415 }
9416
9417 /// parseDirectiveThumb
9418 ///  ::= .thumb
9419 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
9420   if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive") ||
9421       check(!hasThumb(), L, "target does not support Thumb mode"))
9422     return true;
9423
9424   if (!isThumb())
9425     SwitchMode();
9426
9427   getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
9428   return false;
9429 }
9430
9431 /// parseDirectiveARM
9432 ///  ::= .arm
9433 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
9434   if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive") ||
9435       check(!hasARM(), L, "target does not support ARM mode"))
9436     return true;
9437
9438   if (isThumb())
9439     SwitchMode();
9440   getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
9441   return false;
9442 }
9443
9444 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
9445   // We need to flush the current implicit IT block on a label, because it is
9446   // not legal to branch into an IT block.
9447   flushPendingInstructions(getStreamer());
9448   if (NextSymbolIsThumb) {
9449     getParser().getStreamer().EmitThumbFunc(Symbol);
9450     NextSymbolIsThumb = false;
9451   }
9452 }
9453
9454 /// parseDirectiveThumbFunc
9455 ///  ::= .thumbfunc symbol_name
9456 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
9457   MCAsmParser &Parser = getParser();
9458   const auto Format = getContext().getObjectFileInfo()->getObjectFileType();
9459   bool IsMachO = Format == MCObjectFileInfo::IsMachO;
9460
9461   // Darwin asm has (optionally) function name after .thumb_func direction
9462   // ELF doesn't
9463
9464   if (IsMachO) {
9465     if (Parser.getTok().is(AsmToken::Identifier) ||
9466         Parser.getTok().is(AsmToken::String)) {
9467       MCSymbol *Func = getParser().getContext().getOrCreateSymbol(
9468           Parser.getTok().getIdentifier());
9469       getParser().getStreamer().EmitThumbFunc(Func);
9470       Parser.Lex();
9471       if (parseToken(AsmToken::EndOfStatement,
9472                      "unexpected token in '.thumb_func' directive"))
9473         return true;
9474       return false;
9475     }
9476   }
9477
9478   if (parseToken(AsmToken::EndOfStatement,
9479                  "unexpected token in '.thumb_func' directive"))
9480     return true;
9481
9482   NextSymbolIsThumb = true;
9483   return false;
9484 }
9485
9486 /// parseDirectiveSyntax
9487 ///  ::= .syntax unified | divided
9488 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
9489   MCAsmParser &Parser = getParser();
9490   const AsmToken &Tok = Parser.getTok();
9491   if (Tok.isNot(AsmToken::Identifier)) {
9492     Error(L, "unexpected token in .syntax directive");
9493     return false;
9494   }
9495
9496   StringRef Mode = Tok.getString();
9497   Parser.Lex();
9498   if (check(Mode == "divided" || Mode == "DIVIDED", L,
9499             "'.syntax divided' arm assembly not supported") ||
9500       check(Mode != "unified" && Mode != "UNIFIED", L,
9501             "unrecognized syntax mode in .syntax directive") ||
9502       parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
9503     return true;
9504
9505   // TODO tell the MC streamer the mode
9506   // getParser().getStreamer().Emit???();
9507   return false;
9508 }
9509
9510 /// parseDirectiveCode
9511 ///  ::= .code 16 | 32
9512 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
9513   MCAsmParser &Parser = getParser();
9514   const AsmToken &Tok = Parser.getTok();
9515   if (Tok.isNot(AsmToken::Integer))
9516     return Error(L, "unexpected token in .code directive");
9517   int64_t Val = Parser.getTok().getIntVal();
9518   if (Val != 16 && Val != 32) {
9519     Error(L, "invalid operand to .code directive");
9520     return false;
9521   }
9522   Parser.Lex();
9523
9524   if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
9525     return true;
9526
9527   if (Val == 16) {
9528     if (!hasThumb())
9529       return Error(L, "target does not support Thumb mode");
9530
9531     if (!isThumb())
9532       SwitchMode();
9533     getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
9534   } else {
9535     if (!hasARM())
9536       return Error(L, "target does not support ARM mode");
9537
9538     if (isThumb())
9539       SwitchMode();
9540     getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
9541   }
9542
9543   return false;
9544 }
9545
9546 /// parseDirectiveReq
9547 ///  ::= name .req registername
9548 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
9549   MCAsmParser &Parser = getParser();
9550   Parser.Lex(); // Eat the '.req' token.
9551   unsigned Reg;
9552   SMLoc SRegLoc, ERegLoc;
9553   if (check(ParseRegister(Reg, SRegLoc, ERegLoc), SRegLoc,
9554             "register name expected") ||
9555       parseToken(AsmToken::EndOfStatement,
9556                  "unexpected input in .req directive."))
9557     return true;
9558
9559   if (RegisterReqs.insert(std::make_pair(Name, Reg)).first->second != Reg)
9560     return Error(SRegLoc,
9561                  "redefinition of '" + Name + "' does not match original.");
9562
9563   return false;
9564 }
9565
9566 /// parseDirectiveUneq
9567 ///  ::= .unreq registername
9568 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
9569   MCAsmParser &Parser = getParser();
9570   if (Parser.getTok().isNot(AsmToken::Identifier))
9571     return Error(L, "unexpected input in .unreq directive.");
9572   RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
9573   Parser.Lex(); // Eat the identifier.
9574   if (parseToken(AsmToken::EndOfStatement,
9575                  "unexpected input in '.unreq' directive"))
9576     return true;
9577   return false;
9578 }
9579
9580 // After changing arch/CPU, try to put the ARM/Thumb mode back to what it was
9581 // before, if supported by the new target, or emit mapping symbols for the mode
9582 // switch.
9583 void ARMAsmParser::FixModeAfterArchChange(bool WasThumb, SMLoc Loc) {
9584   if (WasThumb != isThumb()) {
9585     if (WasThumb && hasThumb()) {
9586       // Stay in Thumb mode
9587       SwitchMode();
9588     } else if (!WasThumb && hasARM()) {
9589       // Stay in ARM mode
9590       SwitchMode();
9591     } else {
9592       // Mode switch forced, because the new arch doesn't support the old mode.
9593       getParser().getStreamer().EmitAssemblerFlag(isThumb() ? MCAF_Code16
9594                                                             : MCAF_Code32);
9595       // Warn about the implcit mode switch. GAS does not switch modes here,
9596       // but instead stays in the old mode, reporting an error on any following
9597       // instructions as the mode does not exist on the target.
9598       Warning(Loc, Twine("new target does not support ") +
9599                        (WasThumb ? "thumb" : "arm") + " mode, switching to " +
9600                        (!WasThumb ? "thumb" : "arm") + " mode");
9601     }
9602   }
9603 }
9604
9605 /// parseDirectiveArch
9606 ///  ::= .arch token
9607 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
9608   StringRef Arch = getParser().parseStringToEndOfStatement().trim();
9609   ARM::ArchKind ID = ARM::parseArch(Arch);
9610
9611   if (ID == ARM::ArchKind::INVALID)
9612     return Error(L, "Unknown arch name");
9613
9614   bool WasThumb = isThumb();
9615   Triple T;
9616   MCSubtargetInfo &STI = copySTI();
9617   STI.setDefaultFeatures("", ("+" + ARM::getArchName(ID)).str());
9618   setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
9619   FixModeAfterArchChange(WasThumb, L);
9620
9621   getTargetStreamer().emitArch(ID);
9622   return false;
9623 }
9624
9625 /// parseDirectiveEabiAttr
9626 ///  ::= .eabi_attribute int, int [, "str"]
9627 ///  ::= .eabi_attribute Tag_name, int [, "str"]
9628 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
9629   MCAsmParser &Parser = getParser();
9630   int64_t Tag;
9631   SMLoc TagLoc;
9632   TagLoc = Parser.getTok().getLoc();
9633   if (Parser.getTok().is(AsmToken::Identifier)) {
9634     StringRef Name = Parser.getTok().getIdentifier();
9635     Tag = ARMBuildAttrs::AttrTypeFromString(Name);
9636     if (Tag == -1) {
9637       Error(TagLoc, "attribute name not recognised: " + Name);
9638       return false;
9639     }
9640     Parser.Lex();
9641   } else {
9642     const MCExpr *AttrExpr;
9643
9644     TagLoc = Parser.getTok().getLoc();
9645     if (Parser.parseExpression(AttrExpr))
9646       return true;
9647
9648     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
9649     if (check(!CE, TagLoc, "expected numeric constant"))
9650       return true;
9651
9652     Tag = CE->getValue();
9653   }
9654
9655   if (Parser.parseToken(AsmToken::Comma, "comma expected"))
9656     return true;
9657
9658   StringRef StringValue = "";
9659   bool IsStringValue = false;
9660
9661   int64_t IntegerValue = 0;
9662   bool IsIntegerValue = false;
9663
9664   if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
9665     IsStringValue = true;
9666   else if (Tag == ARMBuildAttrs::compatibility) {
9667     IsStringValue = true;
9668     IsIntegerValue = true;
9669   } else if (Tag < 32 || Tag % 2 == 0)
9670     IsIntegerValue = true;
9671   else if (Tag % 2 == 1)
9672     IsStringValue = true;
9673   else
9674     llvm_unreachable("invalid tag type");
9675
9676   if (IsIntegerValue) {
9677     const MCExpr *ValueExpr;
9678     SMLoc ValueExprLoc = Parser.getTok().getLoc();
9679     if (Parser.parseExpression(ValueExpr))
9680       return true;
9681
9682     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
9683     if (!CE)
9684       return Error(ValueExprLoc, "expected numeric constant");
9685     IntegerValue = CE->getValue();
9686   }
9687
9688   if (Tag == ARMBuildAttrs::compatibility) {
9689     if (Parser.parseToken(AsmToken::Comma, "comma expected"))
9690       return true;
9691   }
9692
9693   if (IsStringValue) {
9694     if (Parser.getTok().isNot(AsmToken::String))
9695       return Error(Parser.getTok().getLoc(), "bad string constant");
9696
9697     StringValue = Parser.getTok().getStringContents();
9698     Parser.Lex();
9699   }
9700
9701   if (Parser.parseToken(AsmToken::EndOfStatement,
9702                         "unexpected token in '.eabi_attribute' directive"))
9703     return true;
9704
9705   if (IsIntegerValue && IsStringValue) {
9706     assert(Tag == ARMBuildAttrs::compatibility);
9707     getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
9708   } else if (IsIntegerValue)
9709     getTargetStreamer().emitAttribute(Tag, IntegerValue);
9710   else if (IsStringValue)
9711     getTargetStreamer().emitTextAttribute(Tag, StringValue);
9712   return false;
9713 }
9714
9715 /// parseDirectiveCPU
9716 ///  ::= .cpu str
9717 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
9718   StringRef CPU = getParser().parseStringToEndOfStatement().trim();
9719   getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
9720
9721   // FIXME: This is using table-gen data, but should be moved to
9722   // ARMTargetParser once that is table-gen'd.
9723   if (!getSTI().isCPUStringValid(CPU))
9724     return Error(L, "Unknown CPU name");
9725
9726   bool WasThumb = isThumb();
9727   MCSubtargetInfo &STI = copySTI();
9728   STI.setDefaultFeatures(CPU, "");
9729   setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
9730   FixModeAfterArchChange(WasThumb, L);
9731
9732   return false;
9733 }
9734
9735 /// parseDirectiveFPU
9736 ///  ::= .fpu str
9737 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
9738   SMLoc FPUNameLoc = getTok().getLoc();
9739   StringRef FPU = getParser().parseStringToEndOfStatement().trim();
9740
9741   unsigned ID = ARM::parseFPU(FPU);
9742   std::vector<StringRef> Features;
9743   if (!ARM::getFPUFeatures(ID, Features))
9744     return Error(FPUNameLoc, "Unknown FPU name");
9745
9746   MCSubtargetInfo &STI = copySTI();
9747   for (auto Feature : Features)
9748     STI.ApplyFeatureFlag(Feature);
9749   setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
9750
9751   getTargetStreamer().emitFPU(ID);
9752   return false;
9753 }
9754
9755 /// parseDirectiveFnStart
9756 ///  ::= .fnstart
9757 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
9758   if (parseToken(AsmToken::EndOfStatement,
9759                  "unexpected token in '.fnstart' directive"))
9760     return true;
9761
9762   if (UC.hasFnStart()) {
9763     Error(L, ".fnstart starts before the end of previous one");
9764     UC.emitFnStartLocNotes();
9765     return true;
9766   }
9767
9768   // Reset the unwind directives parser state
9769   UC.reset();
9770
9771   getTargetStreamer().emitFnStart();
9772
9773   UC.recordFnStart(L);
9774   return false;
9775 }
9776
9777 /// parseDirectiveFnEnd
9778 ///  ::= .fnend
9779 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
9780   if (parseToken(AsmToken::EndOfStatement,
9781                  "unexpected token in '.fnend' directive"))
9782     return true;
9783   // Check the ordering of unwind directives
9784   if (!UC.hasFnStart())
9785     return Error(L, ".fnstart must precede .fnend directive");
9786
9787   // Reset the unwind directives parser state
9788   getTargetStreamer().emitFnEnd();
9789
9790   UC.reset();
9791   return false;
9792 }
9793
9794 /// parseDirectiveCantUnwind
9795 ///  ::= .cantunwind
9796 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
9797   if (parseToken(AsmToken::EndOfStatement,
9798                  "unexpected token in '.cantunwind' directive"))
9799     return true;
9800
9801   UC.recordCantUnwind(L);
9802   // Check the ordering of unwind directives
9803   if (check(!UC.hasFnStart(), L, ".fnstart must precede .cantunwind directive"))
9804     return true;
9805
9806   if (UC.hasHandlerData()) {
9807     Error(L, ".cantunwind can't be used with .handlerdata directive");
9808     UC.emitHandlerDataLocNotes();
9809     return true;
9810   }
9811   if (UC.hasPersonality()) {
9812     Error(L, ".cantunwind can't be used with .personality directive");
9813     UC.emitPersonalityLocNotes();
9814     return true;
9815   }
9816
9817   getTargetStreamer().emitCantUnwind();
9818   return false;
9819 }
9820
9821 /// parseDirectivePersonality
9822 ///  ::= .personality name
9823 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
9824   MCAsmParser &Parser = getParser();
9825   bool HasExistingPersonality = UC.hasPersonality();
9826
9827   // Parse the name of the personality routine
9828   if (Parser.getTok().isNot(AsmToken::Identifier))
9829     return Error(L, "unexpected input in .personality directive.");
9830   StringRef Name(Parser.getTok().getIdentifier());
9831   Parser.Lex();
9832
9833   if (parseToken(AsmToken::EndOfStatement,
9834                  "unexpected token in '.personality' directive"))
9835     return true;
9836
9837   UC.recordPersonality(L);
9838
9839   // Check the ordering of unwind directives
9840   if (!UC.hasFnStart())
9841     return Error(L, ".fnstart must precede .personality directive");
9842   if (UC.cantUnwind()) {
9843     Error(L, ".personality can't be used with .cantunwind directive");
9844     UC.emitCantUnwindLocNotes();
9845     return true;
9846   }
9847   if (UC.hasHandlerData()) {
9848     Error(L, ".personality must precede .handlerdata directive");
9849     UC.emitHandlerDataLocNotes();
9850     return true;
9851   }
9852   if (HasExistingPersonality) {
9853     Error(L, "multiple personality directives");
9854     UC.emitPersonalityLocNotes();
9855     return true;
9856   }
9857
9858   MCSymbol *PR = getParser().getContext().getOrCreateSymbol(Name);
9859   getTargetStreamer().emitPersonality(PR);
9860   return false;
9861 }
9862
9863 /// parseDirectiveHandlerData
9864 ///  ::= .handlerdata
9865 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
9866   if (parseToken(AsmToken::EndOfStatement,
9867                  "unexpected token in '.handlerdata' directive"))
9868     return true;
9869
9870   UC.recordHandlerData(L);
9871   // Check the ordering of unwind directives
9872   if (!UC.hasFnStart())
9873     return Error(L, ".fnstart must precede .personality directive");
9874   if (UC.cantUnwind()) {
9875     Error(L, ".handlerdata can't be used with .cantunwind directive");
9876     UC.emitCantUnwindLocNotes();
9877     return true;
9878   }
9879
9880   getTargetStreamer().emitHandlerData();
9881   return false;
9882 }
9883
9884 /// parseDirectiveSetFP
9885 ///  ::= .setfp fpreg, spreg [, offset]
9886 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
9887   MCAsmParser &Parser = getParser();
9888   // Check the ordering of unwind directives
9889   if (check(!UC.hasFnStart(), L, ".fnstart must precede .setfp directive") ||
9890       check(UC.hasHandlerData(), L,
9891             ".setfp must precede .handlerdata directive"))
9892     return true;
9893
9894   // Parse fpreg
9895   SMLoc FPRegLoc = Parser.getTok().getLoc();
9896   int FPReg = tryParseRegister();
9897
9898   if (check(FPReg == -1, FPRegLoc, "frame pointer register expected") ||
9899       Parser.parseToken(AsmToken::Comma, "comma expected"))
9900     return true;
9901
9902   // Parse spreg
9903   SMLoc SPRegLoc = Parser.getTok().getLoc();
9904   int SPReg = tryParseRegister();
9905   if (check(SPReg == -1, SPRegLoc, "stack pointer register expected") ||
9906       check(SPReg != ARM::SP && SPReg != UC.getFPReg(), SPRegLoc,
9907             "register should be either $sp or the latest fp register"))
9908     return true;
9909
9910   // Update the frame pointer register
9911   UC.saveFPReg(FPReg);
9912
9913   // Parse offset
9914   int64_t Offset = 0;
9915   if (Parser.parseOptionalToken(AsmToken::Comma)) {
9916     if (Parser.getTok().isNot(AsmToken::Hash) &&
9917         Parser.getTok().isNot(AsmToken::Dollar))
9918       return Error(Parser.getTok().getLoc(), "'#' expected");
9919     Parser.Lex(); // skip hash token.
9920
9921     const MCExpr *OffsetExpr;
9922     SMLoc ExLoc = Parser.getTok().getLoc();
9923     SMLoc EndLoc;
9924     if (getParser().parseExpression(OffsetExpr, EndLoc))
9925       return Error(ExLoc, "malformed setfp offset");
9926     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9927     if (check(!CE, ExLoc, "setfp offset must be an immediate"))
9928       return true;
9929     Offset = CE->getValue();
9930   }
9931
9932   if (Parser.parseToken(AsmToken::EndOfStatement))
9933     return true;
9934
9935   getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
9936                                 static_cast<unsigned>(SPReg), Offset);
9937   return false;
9938 }
9939
9940 /// parseDirective
9941 ///  ::= .pad offset
9942 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
9943   MCAsmParser &Parser = getParser();
9944   // Check the ordering of unwind directives
9945   if (!UC.hasFnStart())
9946     return Error(L, ".fnstart must precede .pad directive");
9947   if (UC.hasHandlerData())
9948     return Error(L, ".pad must precede .handlerdata directive");
9949
9950   // Parse the offset
9951   if (Parser.getTok().isNot(AsmToken::Hash) &&
9952       Parser.getTok().isNot(AsmToken::Dollar))
9953     return Error(Parser.getTok().getLoc(), "'#' expected");
9954   Parser.Lex(); // skip hash token.
9955
9956   const MCExpr *OffsetExpr;
9957   SMLoc ExLoc = Parser.getTok().getLoc();
9958   SMLoc EndLoc;
9959   if (getParser().parseExpression(OffsetExpr, EndLoc))
9960     return Error(ExLoc, "malformed pad offset");
9961   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9962   if (!CE)
9963     return Error(ExLoc, "pad offset must be an immediate");
9964
9965   if (parseToken(AsmToken::EndOfStatement,
9966                  "unexpected token in '.pad' directive"))
9967     return true;
9968
9969   getTargetStreamer().emitPad(CE->getValue());
9970   return false;
9971 }
9972
9973 /// parseDirectiveRegSave
9974 ///  ::= .save  { registers }
9975 ///  ::= .vsave { registers }
9976 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
9977   // Check the ordering of unwind directives
9978   if (!UC.hasFnStart())
9979     return Error(L, ".fnstart must precede .save or .vsave directives");
9980   if (UC.hasHandlerData())
9981     return Error(L, ".save or .vsave must precede .handlerdata directive");
9982
9983   // RAII object to make sure parsed operands are deleted.
9984   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
9985
9986   // Parse the register list
9987   if (parseRegisterList(Operands) ||
9988       parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
9989     return true;
9990   ARMOperand &Op = (ARMOperand &)*Operands[0];
9991   if (!IsVector && !Op.isRegList())
9992     return Error(L, ".save expects GPR registers");
9993   if (IsVector && !Op.isDPRRegList())
9994     return Error(L, ".vsave expects DPR registers");
9995
9996   getTargetStreamer().emitRegSave(Op.getRegList(), IsVector);
9997   return false;
9998 }
9999
10000 /// parseDirectiveInst
10001 ///  ::= .inst opcode [, ...]
10002 ///  ::= .inst.n opcode [, ...]
10003 ///  ::= .inst.w opcode [, ...]
10004 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
10005   int Width = 4;
10006
10007   if (isThumb()) {
10008     switch (Suffix) {
10009     case 'n':
10010       Width = 2;
10011       break;
10012     case 'w':
10013       break;
10014     default:
10015       return Error(Loc, "cannot determine Thumb instruction size, "
10016                         "use inst.n/inst.w instead");
10017     }
10018   } else {
10019     if (Suffix)
10020       return Error(Loc, "width suffixes are invalid in ARM mode");
10021   }
10022
10023   auto parseOne = [&]() -> bool {
10024     const MCExpr *Expr;
10025     if (getParser().parseExpression(Expr))
10026       return true;
10027     const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
10028     if (!Value) {
10029       return Error(Loc, "expected constant expression");
10030     }
10031
10032     switch (Width) {
10033     case 2:
10034       if (Value->getValue() > 0xffff)
10035         return Error(Loc, "inst.n operand is too big, use inst.w instead");
10036       break;
10037     case 4:
10038       if (Value->getValue() > 0xffffffff)
10039         return Error(Loc, StringRef(Suffix ? "inst.w" : "inst") +
10040                               " operand is too big");
10041       break;
10042     default:
10043       llvm_unreachable("only supported widths are 2 and 4");
10044     }
10045
10046     getTargetStreamer().emitInst(Value->getValue(), Suffix);
10047     return false;
10048   };
10049
10050   if (parseOptionalToken(AsmToken::EndOfStatement))
10051     return Error(Loc, "expected expression following directive");
10052   if (parseMany(parseOne))
10053     return true;
10054   return false;
10055 }
10056
10057 /// parseDirectiveLtorg
10058 ///  ::= .ltorg | .pool
10059 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
10060   if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
10061     return true;
10062   getTargetStreamer().emitCurrentConstantPool();
10063   return false;
10064 }
10065
10066 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
10067   const MCSection *Section = getStreamer().getCurrentSectionOnly();
10068
10069   if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
10070     return true;
10071
10072   if (!Section) {
10073     getStreamer().InitSections(false);
10074     Section = getStreamer().getCurrentSectionOnly();
10075   }
10076
10077   assert(Section && "must have section to emit alignment");
10078   if (Section->UseCodeAlign())
10079     getStreamer().EmitCodeAlignment(2);
10080   else
10081     getStreamer().EmitValueToAlignment(2);
10082
10083   return false;
10084 }
10085
10086 /// parseDirectivePersonalityIndex
10087 ///   ::= .personalityindex index
10088 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
10089   MCAsmParser &Parser = getParser();
10090   bool HasExistingPersonality = UC.hasPersonality();
10091
10092   const MCExpr *IndexExpression;
10093   SMLoc IndexLoc = Parser.getTok().getLoc();
10094   if (Parser.parseExpression(IndexExpression) ||
10095       parseToken(AsmToken::EndOfStatement,
10096                  "unexpected token in '.personalityindex' directive")) {
10097     return true;
10098   }
10099
10100   UC.recordPersonalityIndex(L);
10101
10102   if (!UC.hasFnStart()) {
10103     return Error(L, ".fnstart must precede .personalityindex directive");
10104   }
10105   if (UC.cantUnwind()) {
10106     Error(L, ".personalityindex cannot be used with .cantunwind");
10107     UC.emitCantUnwindLocNotes();
10108     return true;
10109   }
10110   if (UC.hasHandlerData()) {
10111     Error(L, ".personalityindex must precede .handlerdata directive");
10112     UC.emitHandlerDataLocNotes();
10113     return true;
10114   }
10115   if (HasExistingPersonality) {
10116     Error(L, "multiple personality directives");
10117     UC.emitPersonalityLocNotes();
10118     return true;
10119   }
10120
10121   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
10122   if (!CE)
10123     return Error(IndexLoc, "index must be a constant number");
10124   if (CE->getValue() < 0 || CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX)
10125     return Error(IndexLoc,
10126                  "personality routine index should be in range [0-3]");
10127
10128   getTargetStreamer().emitPersonalityIndex(CE->getValue());
10129   return false;
10130 }
10131
10132 /// parseDirectiveUnwindRaw
10133 ///   ::= .unwind_raw offset, opcode [, opcode...]
10134 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
10135   MCAsmParser &Parser = getParser();
10136   int64_t StackOffset;
10137   const MCExpr *OffsetExpr;
10138   SMLoc OffsetLoc = getLexer().getLoc();
10139
10140   if (!UC.hasFnStart())
10141     return Error(L, ".fnstart must precede .unwind_raw directives");
10142   if (getParser().parseExpression(OffsetExpr))
10143     return Error(OffsetLoc, "expected expression");
10144
10145   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
10146   if (!CE)
10147     return Error(OffsetLoc, "offset must be a constant");
10148
10149   StackOffset = CE->getValue();
10150
10151   if (Parser.parseToken(AsmToken::Comma, "expected comma"))
10152     return true;
10153
10154   SmallVector<uint8_t, 16> Opcodes;
10155
10156   auto parseOne = [&]() -> bool {
10157     const MCExpr *OE;
10158     SMLoc OpcodeLoc = getLexer().getLoc();
10159     if (check(getLexer().is(AsmToken::EndOfStatement) ||
10160                   Parser.parseExpression(OE),
10161               OpcodeLoc, "expected opcode expression"))
10162       return true;
10163     const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
10164     if (!OC)
10165       return Error(OpcodeLoc, "opcode value must be a constant");
10166     const int64_t Opcode = OC->getValue();
10167     if (Opcode & ~0xff)
10168       return Error(OpcodeLoc, "invalid opcode");
10169     Opcodes.push_back(uint8_t(Opcode));
10170     return false;
10171   };
10172
10173   // Must have at least 1 element
10174   SMLoc OpcodeLoc = getLexer().getLoc();
10175   if (parseOptionalToken(AsmToken::EndOfStatement))
10176     return Error(OpcodeLoc, "expected opcode expression");
10177   if (parseMany(parseOne))
10178     return true;
10179
10180   getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
10181   return false;
10182 }
10183
10184 /// parseDirectiveTLSDescSeq
10185 ///   ::= .tlsdescseq tls-variable
10186 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
10187   MCAsmParser &Parser = getParser();
10188
10189   if (getLexer().isNot(AsmToken::Identifier))
10190     return TokError("expected variable after '.tlsdescseq' directive");
10191
10192   const MCSymbolRefExpr *SRE =
10193     MCSymbolRefExpr::create(Parser.getTok().getIdentifier(),
10194                             MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
10195   Lex();
10196
10197   if (parseToken(AsmToken::EndOfStatement,
10198                  "unexpected token in '.tlsdescseq' directive"))
10199     return true;
10200
10201   getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
10202   return false;
10203 }
10204
10205 /// parseDirectiveMovSP
10206 ///  ::= .movsp reg [, #offset]
10207 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
10208   MCAsmParser &Parser = getParser();
10209   if (!UC.hasFnStart())
10210     return Error(L, ".fnstart must precede .movsp directives");
10211   if (UC.getFPReg() != ARM::SP)
10212     return Error(L, "unexpected .movsp directive");
10213
10214   SMLoc SPRegLoc = Parser.getTok().getLoc();
10215   int SPReg = tryParseRegister();
10216   if (SPReg == -1)
10217     return Error(SPRegLoc, "register expected");
10218   if (SPReg == ARM::SP || SPReg == ARM::PC)
10219     return Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
10220
10221   int64_t Offset = 0;
10222   if (Parser.parseOptionalToken(AsmToken::Comma)) {
10223     if (Parser.parseToken(AsmToken::Hash, "expected #constant"))
10224       return true;
10225
10226     const MCExpr *OffsetExpr;
10227     SMLoc OffsetLoc = Parser.getTok().getLoc();
10228
10229     if (Parser.parseExpression(OffsetExpr))
10230       return Error(OffsetLoc, "malformed offset expression");
10231
10232     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
10233     if (!CE)
10234       return Error(OffsetLoc, "offset must be an immediate constant");
10235
10236     Offset = CE->getValue();
10237   }
10238
10239   if (parseToken(AsmToken::EndOfStatement,
10240                  "unexpected token in '.movsp' directive"))
10241     return true;
10242
10243   getTargetStreamer().emitMovSP(SPReg, Offset);
10244   UC.saveFPReg(SPReg);
10245
10246   return false;
10247 }
10248
10249 /// parseDirectiveObjectArch
10250 ///   ::= .object_arch name
10251 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
10252   MCAsmParser &Parser = getParser();
10253   if (getLexer().isNot(AsmToken::Identifier))
10254     return Error(getLexer().getLoc(), "unexpected token");
10255
10256   StringRef Arch = Parser.getTok().getString();
10257   SMLoc ArchLoc = Parser.getTok().getLoc();
10258   Lex();
10259
10260   ARM::ArchKind ID = ARM::parseArch(Arch);
10261
10262   if (ID == ARM::ArchKind::INVALID)
10263     return Error(ArchLoc, "unknown architecture '" + Arch + "'");
10264   if (parseToken(AsmToken::EndOfStatement))
10265     return true;
10266
10267   getTargetStreamer().emitObjectArch(ID);
10268   return false;
10269 }
10270
10271 /// parseDirectiveAlign
10272 ///   ::= .align
10273 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {
10274   // NOTE: if this is not the end of the statement, fall back to the target
10275   // agnostic handling for this directive which will correctly handle this.
10276   if (parseOptionalToken(AsmToken::EndOfStatement)) {
10277     // '.align' is target specifically handled to mean 2**2 byte alignment.
10278     const MCSection *Section = getStreamer().getCurrentSectionOnly();
10279     assert(Section && "must have section to emit alignment");
10280     if (Section->UseCodeAlign())
10281       getStreamer().EmitCodeAlignment(4, 0);
10282     else
10283       getStreamer().EmitValueToAlignment(4, 0, 1, 0);
10284     return false;
10285   }
10286   return true;
10287 }
10288
10289 /// parseDirectiveThumbSet
10290 ///  ::= .thumb_set name, value
10291 bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) {
10292   MCAsmParser &Parser = getParser();
10293
10294   StringRef Name;
10295   if (check(Parser.parseIdentifier(Name),
10296             "expected identifier after '.thumb_set'") ||
10297       parseToken(AsmToken::Comma, "expected comma after name '" + Name + "'"))
10298     return true;
10299
10300   MCSymbol *Sym;
10301   const MCExpr *Value;
10302   if (MCParserUtils::parseAssignmentExpression(Name, /* allow_redef */ true,
10303                                                Parser, Sym, Value))
10304     return true;
10305
10306   getTargetStreamer().emitThumbSet(Sym, Value);
10307   return false;
10308 }
10309
10310 /// Force static initialization.
10311 extern "C" void LLVMInitializeARMAsmParser() {
10312   RegisterMCAsmParser<ARMAsmParser> X(getTheARMLETarget());
10313   RegisterMCAsmParser<ARMAsmParser> Y(getTheARMBETarget());
10314   RegisterMCAsmParser<ARMAsmParser> A(getTheThumbLETarget());
10315   RegisterMCAsmParser<ARMAsmParser> B(getTheThumbBETarget());
10316 }
10317
10318 #define GET_REGISTER_MATCHER
10319 #define GET_SUBTARGET_FEATURE_NAME
10320 #define GET_MATCHER_IMPLEMENTATION
10321 #define GET_MNEMONIC_SPELL_CHECKER
10322 #include "ARMGenAsmMatcher.inc"
10323
10324 // Some diagnostics need to vary with subtarget features, so they are handled
10325 // here. For example, the DPR class has either 16 or 32 registers, depending
10326 // on the FPU available.
10327 const char *
10328 ARMAsmParser::getCustomOperandDiag(ARMMatchResultTy MatchError) {
10329   switch (MatchError) {
10330   // rGPR contains sp starting with ARMv8.
10331   case Match_rGPR:
10332     return hasV8Ops() ? "operand must be a register in range [r0, r14]"
10333                       : "operand must be a register in range [r0, r12] or r14";
10334   // DPR contains 16 registers for some FPUs, and 32 for others.
10335   case Match_DPR:
10336     return hasD16() ? "operand must be a register in range [d0, d15]"
10337                     : "operand must be a register in range [d0, d31]";
10338   case Match_DPR_RegList:
10339     return hasD16() ? "operand must be a list of registers in range [d0, d15]"
10340                     : "operand must be a list of registers in range [d0, d31]";
10341
10342   // For all other diags, use the static string from tablegen.
10343   default:
10344     return getMatchKindDiag(MatchError);
10345   }
10346 }
10347
10348 // Process the list of near-misses, throwing away ones we don't want to report
10349 // to the user, and converting the rest to a source location and string that
10350 // should be reported.
10351 void
10352 ARMAsmParser::FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn,
10353                                SmallVectorImpl<NearMissMessage> &NearMissesOut,
10354                                SMLoc IDLoc, OperandVector &Operands) {
10355   // TODO: If operand didn't match, sub in a dummy one and run target
10356   // predicate, so that we can avoid reporting near-misses that are invalid?
10357   // TODO: Many operand types dont have SuperClasses set, so we report
10358   // redundant ones.
10359   // TODO: Some operands are superclasses of registers (e.g.
10360   // MCK_RegShiftedImm), we don't have any way to represent that currently.
10361   // TODO: This is not all ARM-specific, can some of it be factored out?
10362
10363   // Record some information about near-misses that we have already seen, so
10364   // that we can avoid reporting redundant ones. For example, if there are
10365   // variants of an instruction that take 8- and 16-bit immediates, we want
10366   // to only report the widest one.
10367   std::multimap<unsigned, unsigned> OperandMissesSeen;
10368   SmallSet<uint64_t, 4> FeatureMissesSeen;
10369   bool ReportedTooFewOperands = false;
10370
10371   // Process the near-misses in reverse order, so that we see more general ones
10372   // first, and so can avoid emitting more specific ones.
10373   for (NearMissInfo &I : reverse(NearMissesIn)) {
10374     switch (I.getKind()) {
10375     case NearMissInfo::NearMissOperand: {
10376       SMLoc OperandLoc =
10377           ((ARMOperand &)*Operands[I.getOperandIndex()]).getStartLoc();
10378       const char *OperandDiag =
10379           getCustomOperandDiag((ARMMatchResultTy)I.getOperandError());
10380
10381       // If we have already emitted a message for a superclass, don't also report
10382       // the sub-class. We consider all operand classes that we don't have a
10383       // specialised diagnostic for to be equal for the propose of this check,
10384       // so that we don't report the generic error multiple times on the same
10385       // operand.
10386       unsigned DupCheckMatchClass = OperandDiag ? I.getOperandClass() : ~0U;
10387       auto PrevReports = OperandMissesSeen.equal_range(I.getOperandIndex());
10388       if (std::any_of(PrevReports.first, PrevReports.second,
10389                       [DupCheckMatchClass](
10390                           const std::pair<unsigned, unsigned> Pair) {
10391             if (DupCheckMatchClass == ~0U || Pair.second == ~0U)
10392               return Pair.second == DupCheckMatchClass;
10393             else
10394               return isSubclass((MatchClassKind)DupCheckMatchClass,
10395                                 (MatchClassKind)Pair.second);
10396           }))
10397         break;
10398       OperandMissesSeen.insert(
10399           std::make_pair(I.getOperandIndex(), DupCheckMatchClass));
10400
10401       NearMissMessage Message;
10402       Message.Loc = OperandLoc;
10403       if (OperandDiag) {
10404         Message.Message = OperandDiag;
10405       } else if (I.getOperandClass() == InvalidMatchClass) {
10406         Message.Message = "too many operands for instruction";
10407       } else {
10408         Message.Message = "invalid operand for instruction";
10409         LLVM_DEBUG(
10410             dbgs() << "Missing diagnostic string for operand class "
10411                    << getMatchClassName((MatchClassKind)I.getOperandClass())
10412                    << I.getOperandClass() << ", error " << I.getOperandError()
10413                    << ", opcode " << MII.getName(I.getOpcode()) << "\n");
10414       }
10415       NearMissesOut.emplace_back(Message);
10416       break;
10417     }
10418     case NearMissInfo::NearMissFeature: {
10419       uint64_t MissingFeatures = I.getFeatures();
10420       // Don't report the same set of features twice.
10421       if (FeatureMissesSeen.count(MissingFeatures))
10422         break;
10423       FeatureMissesSeen.insert(MissingFeatures);
10424
10425       // Special case: don't report a feature set which includes arm-mode for
10426       // targets that don't have ARM mode.
10427       if ((MissingFeatures & Feature_IsARM) && !hasARM())
10428         break;
10429       // Don't report any near-misses that both require switching instruction
10430       // set, and adding other subtarget features.
10431       if (isThumb() && (MissingFeatures & Feature_IsARM) &&
10432           (MissingFeatures & ~Feature_IsARM))
10433         break;
10434       if (!isThumb() && (MissingFeatures & Feature_IsThumb) &&
10435           (MissingFeatures & ~Feature_IsThumb))
10436         break;
10437       if (!isThumb() && (MissingFeatures & Feature_IsThumb2) &&
10438           (MissingFeatures & ~(Feature_IsThumb2 | Feature_IsThumb)))
10439         break;
10440       if (isMClass() && (MissingFeatures & Feature_HasNEON))
10441         break;
10442
10443       NearMissMessage Message;
10444       Message.Loc = IDLoc;
10445       raw_svector_ostream OS(Message.Message);
10446
10447       OS << "instruction requires:";
10448       uint64_t Mask = 1;
10449       for (unsigned MaskPos = 0; MaskPos < (sizeof(MissingFeatures) * 8 - 1);
10450            ++MaskPos) {
10451         if (MissingFeatures & Mask) {
10452           OS << " " << getSubtargetFeatureName(MissingFeatures & Mask);
10453         }
10454         Mask <<= 1;
10455       }
10456       NearMissesOut.emplace_back(Message);
10457
10458       break;
10459     }
10460     case NearMissInfo::NearMissPredicate: {
10461       NearMissMessage Message;
10462       Message.Loc = IDLoc;
10463       switch (I.getPredicateError()) {
10464       case Match_RequiresNotITBlock:
10465         Message.Message = "flag setting instruction only valid outside IT block";
10466         break;
10467       case Match_RequiresITBlock:
10468         Message.Message = "instruction only valid inside IT block";
10469         break;
10470       case Match_RequiresV6:
10471         Message.Message = "instruction variant requires ARMv6 or later";
10472         break;
10473       case Match_RequiresThumb2:
10474         Message.Message = "instruction variant requires Thumb2";
10475         break;
10476       case Match_RequiresV8:
10477         Message.Message = "instruction variant requires ARMv8 or later";
10478         break;
10479       case Match_RequiresFlagSetting:
10480         Message.Message = "no flag-preserving variant of this instruction available";
10481         break;
10482       case Match_InvalidOperand:
10483         Message.Message = "invalid operand for instruction";
10484         break;
10485       default:
10486         llvm_unreachable("Unhandled target predicate error");
10487         break;
10488       }
10489       NearMissesOut.emplace_back(Message);
10490       break;
10491     }
10492     case NearMissInfo::NearMissTooFewOperands: {
10493       if (!ReportedTooFewOperands) {
10494         SMLoc EndLoc = ((ARMOperand &)*Operands.back()).getEndLoc();
10495         NearMissesOut.emplace_back(NearMissMessage{
10496             EndLoc, StringRef("too few operands for instruction")});
10497         ReportedTooFewOperands = true;
10498       }
10499       break;
10500     }
10501     case NearMissInfo::NoNearMiss:
10502       // This should never leave the matcher.
10503       llvm_unreachable("not a near-miss");
10504       break;
10505     }
10506   }
10507 }
10508
10509 void ARMAsmParser::ReportNearMisses(SmallVectorImpl<NearMissInfo> &NearMisses,
10510                                     SMLoc IDLoc, OperandVector &Operands) {
10511   SmallVector<NearMissMessage, 4> Messages;
10512   FilterNearMisses(NearMisses, Messages, IDLoc, Operands);
10513
10514   if (Messages.size() == 0) {
10515     // No near-misses were found, so the best we can do is "invalid
10516     // instruction".
10517     Error(IDLoc, "invalid instruction");
10518   } else if (Messages.size() == 1) {
10519     // One near miss was found, report it as the sole error.
10520     Error(Messages[0].Loc, Messages[0].Message);
10521   } else {
10522     // More than one near miss, so report a generic "invalid instruction"
10523     // error, followed by notes for each of the near-misses.
10524     Error(IDLoc, "invalid instruction, any one of the following would fix this:");
10525     for (auto &M : Messages) {
10526       Note(M.Loc, M.Message);
10527     }
10528   }
10529 }
10530
10531 // FIXME: This structure should be moved inside ARMTargetParser
10532 // when we start to table-generate them, and we can use the ARM
10533 // flags below, that were generated by table-gen.
10534 static const struct {
10535   const unsigned Kind;
10536   const uint64_t ArchCheck;
10537   const FeatureBitset Features;
10538 } Extensions[] = {
10539   { ARM::AEK_CRC, Feature_HasV8, {ARM::FeatureCRC} },
10540   { ARM::AEK_CRYPTO,  Feature_HasV8,
10541     {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8} },
10542   { ARM::AEK_FP, Feature_HasV8, {ARM::FeatureFPARMv8} },
10543   { (ARM::AEK_HWDIVTHUMB | ARM::AEK_HWDIVARM), Feature_HasV7 | Feature_IsNotMClass,
10544     {ARM::FeatureHWDivThumb, ARM::FeatureHWDivARM} },
10545   { ARM::AEK_MP, Feature_HasV7 | Feature_IsNotMClass, {ARM::FeatureMP} },
10546   { ARM::AEK_SIMD, Feature_HasV8, {ARM::FeatureNEON, ARM::FeatureFPARMv8} },
10547   { ARM::AEK_SEC, Feature_HasV6K, {ARM::FeatureTrustZone} },
10548   // FIXME: Only available in A-class, isel not predicated
10549   { ARM::AEK_VIRT, Feature_HasV7, {ARM::FeatureVirtualization} },
10550   { ARM::AEK_FP16, Feature_HasV8_2a, {ARM::FeatureFPARMv8, ARM::FeatureFullFP16} },
10551   { ARM::AEK_RAS, Feature_HasV8, {ARM::FeatureRAS} },
10552   // FIXME: Unsupported extensions.
10553   { ARM::AEK_OS, Feature_None, {} },
10554   { ARM::AEK_IWMMXT, Feature_None, {} },
10555   { ARM::AEK_IWMMXT2, Feature_None, {} },
10556   { ARM::AEK_MAVERICK, Feature_None, {} },
10557   { ARM::AEK_XSCALE, Feature_None, {} },
10558 };
10559
10560 /// parseDirectiveArchExtension
10561 ///   ::= .arch_extension [no]feature
10562 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
10563   MCAsmParser &Parser = getParser();
10564
10565   if (getLexer().isNot(AsmToken::Identifier))
10566     return Error(getLexer().getLoc(), "expected architecture extension name");
10567
10568   StringRef Name = Parser.getTok().getString();
10569   SMLoc ExtLoc = Parser.getTok().getLoc();
10570   Lex();
10571
10572   if (parseToken(AsmToken::EndOfStatement,
10573                  "unexpected token in '.arch_extension' directive"))
10574     return true;
10575
10576   bool EnableFeature = true;
10577   if (Name.startswith_lower("no")) {
10578     EnableFeature = false;
10579     Name = Name.substr(2);
10580   }
10581   unsigned FeatureKind = ARM::parseArchExt(Name);
10582   if (FeatureKind == ARM::AEK_INVALID)
10583     return Error(ExtLoc, "unknown architectural extension: " + Name);
10584
10585   for (const auto &Extension : Extensions) {
10586     if (Extension.Kind != FeatureKind)
10587       continue;
10588
10589     if (Extension.Features.none())
10590       return Error(ExtLoc, "unsupported architectural extension: " + Name);
10591
10592     if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck)
10593       return Error(ExtLoc, "architectural extension '" + Name +
10594                                "' is not "
10595                                "allowed for the current base architecture");
10596
10597     MCSubtargetInfo &STI = copySTI();
10598     FeatureBitset ToggleFeatures = EnableFeature
10599       ? (~STI.getFeatureBits() & Extension.Features)
10600       : ( STI.getFeatureBits() & Extension.Features);
10601
10602     uint64_t Features =
10603         ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures));
10604     setAvailableFeatures(Features);
10605     return false;
10606   }
10607
10608   return Error(ExtLoc, "unknown architectural extension: " + Name);
10609 }
10610
10611 // Define this matcher function after the auto-generated include so we
10612 // have the match class enum definitions.
10613 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
10614                                                   unsigned Kind) {
10615   ARMOperand &Op = static_cast<ARMOperand &>(AsmOp);
10616   // If the kind is a token for a literal immediate, check if our asm
10617   // operand matches. This is for InstAliases which have a fixed-value
10618   // immediate in the syntax.
10619   switch (Kind) {
10620   default: break;
10621   case MCK__35_0:
10622     if (Op.isImm())
10623       if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
10624         if (CE->getValue() == 0)
10625           return Match_Success;
10626     break;
10627   case MCK_ModImm:
10628     if (Op.isImm()) {
10629       const MCExpr *SOExpr = Op.getImm();
10630       int64_t Value;
10631       if (!SOExpr->evaluateAsAbsolute(Value))
10632         return Match_Success;
10633       assert((Value >= std::numeric_limits<int32_t>::min() &&
10634               Value <= std::numeric_limits<uint32_t>::max()) &&
10635              "expression value must be representable in 32 bits");
10636     }
10637     break;
10638   case MCK_rGPR:
10639     if (hasV8Ops() && Op.isReg() && Op.getReg() == ARM::SP)
10640       return Match_Success;
10641     return Match_rGPR;
10642   case MCK_GPRPair:
10643     if (Op.isReg() &&
10644         MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))
10645       return Match_Success;
10646     break;
10647   }
10648   return Match_InvalidOperand;
10649 }