| blob | 1fcc460670e3637ceeb68108d33b2854e7e619d5 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1
3 ; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP
4 ; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP
5 ; RUN: llc < %s -mtriple=armv5t-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMNODPS
6 ; RUN: llc < %s -mtriple=armv5te-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMBASEDSP
7 ; RUN: llc < %s -mtriple=armv6-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMDSP
9 declare i4 @llvm.sadd.sat.i4(i4, i4)
10 declare i8 @llvm.sadd.sat.i8(i8, i8)
11 declare i16 @llvm.sadd.sat.i16(i16, i16)
12 declare i32 @llvm.sadd.sat.i32(i32, i32)
13 declare i64 @llvm.sadd.sat.i64(i64, i64)
15 define i32 @func(i32 %x, i32 %y) nounwind {
16 ; CHECK-T1-LABEL: func:
17 ; CHECK-T1: @ %bb.0:
18 ; CHECK-T1-NEXT: mov r2, r0
19 ; CHECK-T1-NEXT: movs r3, #1
20 ; CHECK-T1-NEXT: adds r0, r0, r1
21 ; CHECK-T1-NEXT: mov r1, r3
22 ; CHECK-T1-NEXT: bmi .LBB0_2
23 ; CHECK-T1-NEXT: @ %bb.1:
24 ; CHECK-T1-NEXT: movs r1, #0
25 ; CHECK-T1-NEXT: .LBB0_2:
26 ; CHECK-T1-NEXT: cmp r1, #0
27 ; CHECK-T1-NEXT: bne .LBB0_4
28 ; CHECK-T1-NEXT: @ %bb.3:
29 ; CHECK-T1-NEXT: lsls r1, r3, #31
30 ; CHECK-T1-NEXT: cmp r0, r2
31 ; CHECK-T1-NEXT: bvs .LBB0_5
32 ; CHECK-T1-NEXT: b .LBB0_6
33 ; CHECK-T1-NEXT: .LBB0_4:
34 ; CHECK-T1-NEXT: ldr r1, .LCPI0_0
35 ; CHECK-T1-NEXT: cmp r0, r2
36 ; CHECK-T1-NEXT: bvc .LBB0_6
37 ; CHECK-T1-NEXT: .LBB0_5:
38 ; CHECK-T1-NEXT: mov r0, r1
39 ; CHECK-T1-NEXT: .LBB0_6:
40 ; CHECK-T1-NEXT: bx lr
41 ; CHECK-T1-NEXT: .p2align 2
42 ; CHECK-T1-NEXT: @ %bb.7:
43 ; CHECK-T1-NEXT: .LCPI0_0:
44 ; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
45 ;
46 ; CHECK-T2-LABEL: func:
47 ; CHECK-T2: @ %bb.0:
48 ; CHECK-T2-NEXT: adds r2, r0, r1
49 ; CHECK-T2-NEXT: mov.w r3, #0
50 ; CHECK-T2-NEXT: mov.w r1, #-2147483648
51 ; CHECK-T2-NEXT: it mi
52 ; CHECK-T2-NEXT: movmi r3, #1
53 ; CHECK-T2-NEXT: cmp r3, #0
54 ; CHECK-T2-NEXT: it ne
55 ; CHECK-T2-NEXT: mvnne r1, #-2147483648
56 ; CHECK-T2-NEXT: cmp r2, r0
57 ; CHECK-T2-NEXT: it vc
58 ; CHECK-T2-NEXT: movvc r1, r2
59 ; CHECK-T2-NEXT: mov r0, r1
60 ; CHECK-T2-NEXT: bx lr
61 ;
62 ; CHECK-ARM-LABEL: func:
63 ; CHECK-ARM: @ %bb.0:
64 ; CHECK-ARM-NEXT: adds r2, r0, r1
65 ; CHECK-ARM-NEXT: mov r3, #0
66 ; CHECK-ARM-NEXT: movmi r3, #1
67 ; CHECK-ARM-NEXT: mov r1, #-2147483648
68 ; CHECK-ARM-NEXT: cmp r3, #0
69 ; CHECK-ARM-NEXT: mvnne r1, #-2147483648
70 ; CHECK-ARM-NEXT: cmp r2, r0
71 ; CHECK-ARM-NEXT: movvc r1, r2
72 ; CHECK-ARM-NEXT: mov r0, r1
73 ; CHECK-ARM-NEXT: bx lr
74 %tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %y)
75 ret i32 %tmp
76 }
78 define i64 @func2(i64 %x, i64 %y) nounwind {
79 ; CHECK-T1-LABEL: func2:
80 ; CHECK-T1: @ %bb.0:
81 ; CHECK-T1-NEXT: .save {r4, r5, r6, r7, lr}
82 ; CHECK-T1-NEXT: push {r4, r5, r6, r7, lr}
83 ; CHECK-T1-NEXT: .pad #4
84 ; CHECK-T1-NEXT: sub sp, #4
85 ; CHECK-T1-NEXT: str r2, [sp] @ 4-byte Spill
86 ; CHECK-T1-NEXT: mov r2, r0
87 ; CHECK-T1-NEXT: movs r4, #1
88 ; CHECK-T1-NEXT: movs r0, #0
89 ; CHECK-T1-NEXT: cmp r3, #0
90 ; CHECK-T1-NEXT: mov r5, r4
91 ; CHECK-T1-NEXT: bge .LBB1_2
92 ; CHECK-T1-NEXT: @ %bb.1:
93 ; CHECK-T1-NEXT: mov r5, r0
94 ; CHECK-T1-NEXT: .LBB1_2:
95 ; CHECK-T1-NEXT: cmp r1, #0
96 ; CHECK-T1-NEXT: mov r7, r4
97 ; CHECK-T1-NEXT: bge .LBB1_4
98 ; CHECK-T1-NEXT: @ %bb.3:
99 ; CHECK-T1-NEXT: mov r7, r0
100 ; CHECK-T1-NEXT: .LBB1_4:
101 ; CHECK-T1-NEXT: subs r6, r7, r5
102 ; CHECK-T1-NEXT: rsbs r5, r6, #0
103 ; CHECK-T1-NEXT: adcs r5, r6
104 ; CHECK-T1-NEXT: ldr r6, [sp] @ 4-byte Reload
105 ; CHECK-T1-NEXT: adds r6, r2, r6
106 ; CHECK-T1-NEXT: adcs r1, r3
107 ; CHECK-T1-NEXT: cmp r1, #0
108 ; CHECK-T1-NEXT: mov r2, r4
109 ; CHECK-T1-NEXT: bge .LBB1_6
110 ; CHECK-T1-NEXT: @ %bb.5:
111 ; CHECK-T1-NEXT: mov r2, r0
112 ; CHECK-T1-NEXT: .LBB1_6:
113 ; CHECK-T1-NEXT: subs r0, r7, r2
114 ; CHECK-T1-NEXT: subs r2, r0, #1
115 ; CHECK-T1-NEXT: sbcs r0, r2
116 ; CHECK-T1-NEXT: ands r5, r0
117 ; CHECK-T1-NEXT: beq .LBB1_8
118 ; CHECK-T1-NEXT: @ %bb.7:
119 ; CHECK-T1-NEXT: asrs r6, r1, #31
120 ; CHECK-T1-NEXT: .LBB1_8:
121 ; CHECK-T1-NEXT: cmp r1, #0
122 ; CHECK-T1-NEXT: bmi .LBB1_10
123 ; CHECK-T1-NEXT: @ %bb.9:
124 ; CHECK-T1-NEXT: lsls r2, r4, #31
125 ; CHECK-T1-NEXT: cmp r5, #0
126 ; CHECK-T1-NEXT: beq .LBB1_11
127 ; CHECK-T1-NEXT: b .LBB1_12
128 ; CHECK-T1-NEXT: .LBB1_10:
129 ; CHECK-T1-NEXT: ldr r2, .LCPI1_0
130 ; CHECK-T1-NEXT: cmp r5, #0
131 ; CHECK-T1-NEXT: bne .LBB1_12
132 ; CHECK-T1-NEXT: .LBB1_11:
133 ; CHECK-T1-NEXT: mov r2, r1
134 ; CHECK-T1-NEXT: .LBB1_12:
135 ; CHECK-T1-NEXT: mov r0, r6
136 ; CHECK-T1-NEXT: mov r1, r2
137 ; CHECK-T1-NEXT: add sp, #4
138 ; CHECK-T1-NEXT: pop {r4, r5, r6, r7, pc}
139 ; CHECK-T1-NEXT: .p2align 2
140 ; CHECK-T1-NEXT: @ %bb.13:
141 ; CHECK-T1-NEXT: .LCPI1_0:
142 ; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
143 ;
144 ; CHECK-T2-LABEL: func2:
145 ; CHECK-T2: @ %bb.0:
146 ; CHECK-T2-NEXT: .save {r7, lr}
147 ; CHECK-T2-NEXT: push {r7, lr}
148 ; CHECK-T2-NEXT: cmp.w r1, #-1
149 ; CHECK-T2-NEXT: mov.w lr, #0
150 ; CHECK-T2-NEXT: it gt
151 ; CHECK-T2-NEXT: movgt.w lr, #1
152 ; CHECK-T2-NEXT: adds r0, r0, r2
153 ; CHECK-T2-NEXT: adc.w r2, r1, r3
154 ; CHECK-T2-NEXT: movs r1, #0
155 ; CHECK-T2-NEXT: cmp.w r2, #-1
156 ; CHECK-T2-NEXT: it gt
157 ; CHECK-T2-NEXT: movgt r1, #1
158 ; CHECK-T2-NEXT: subs.w r1, lr, r1
159 ; CHECK-T2-NEXT: mov.w r12, #0
160 ; CHECK-T2-NEXT: it ne
161 ; CHECK-T2-NEXT: movne r1, #1
162 ; CHECK-T2-NEXT: cmp.w r3, #-1
163 ; CHECK-T2-NEXT: it gt
164 ; CHECK-T2-NEXT: movgt.w r12, #1
165 ; CHECK-T2-NEXT: sub.w r3, lr, r12
166 ; CHECK-T2-NEXT: clz r3, r3
167 ; CHECK-T2-NEXT: lsrs r3, r3, #5
168 ; CHECK-T2-NEXT: ands r3, r1
169 ; CHECK-T2-NEXT: mov.w r1, #-2147483648
170 ; CHECK-T2-NEXT: it ne
171 ; CHECK-T2-NEXT: asrne r0, r2, #31
172 ; CHECK-T2-NEXT: cmp r2, #0
173 ; CHECK-T2-NEXT: it mi
174 ; CHECK-T2-NEXT: mvnmi r1, #-2147483648
175 ; CHECK-T2-NEXT: cmp r3, #0
176 ; CHECK-T2-NEXT: it eq
177 ; CHECK-T2-NEXT: moveq r1, r2
178 ; CHECK-T2-NEXT: pop {r7, pc}
179 ;
180 ; CHECK-ARM-LABEL: func2:
181 ; CHECK-ARM: @ %bb.0:
182 ; CHECK-ARM-NEXT: .save {r11, lr}
183 ; CHECK-ARM-NEXT: push {r11, lr}
184 ; CHECK-ARM-NEXT: cmn r1, #1
185 ; CHECK-ARM-NEXT: mov lr, #0
186 ; CHECK-ARM-NEXT: movgt lr, #1
187 ; CHECK-ARM-NEXT: adds r0, r0, r2
188 ; CHECK-ARM-NEXT: adc r2, r1, r3
189 ; CHECK-ARM-NEXT: mov r1, #0
190 ; CHECK-ARM-NEXT: cmn r2, #1
191 ; CHECK-ARM-NEXT: mov r12, #0
192 ; CHECK-ARM-NEXT: movgt r1, #1
193 ; CHECK-ARM-NEXT: subs r1, lr, r1
194 ; CHECK-ARM-NEXT: movne r1, #1
195 ; CHECK-ARM-NEXT: cmn r3, #1
196 ; CHECK-ARM-NEXT: movgt r12, #1
197 ; CHECK-ARM-NEXT: sub r3, lr, r12
198 ; CHECK-ARM-NEXT: clz r3, r3
199 ; CHECK-ARM-NEXT: lsr r3, r3, #5
200 ; CHECK-ARM-NEXT: ands r3, r3, r1
201 ; CHECK-ARM-NEXT: mov r1, #-2147483648
202 ; CHECK-ARM-NEXT: asrne r0, r2, #31
203 ; CHECK-ARM-NEXT: cmp r2, #0
204 ; CHECK-ARM-NEXT: mvnmi r1, #-2147483648
205 ; CHECK-ARM-NEXT: cmp r3, #0
206 ; CHECK-ARM-NEXT: moveq r1, r2
207 ; CHECK-ARM-NEXT: pop {r11, pc}
208 %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y)
209 ret i64 %tmp
210 }
212 define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
213 ; CHECK-T1-LABEL: func16:
214 ; CHECK-T1: @ %bb.0:
215 ; CHECK-T1-NEXT: adds r0, r0, r1
216 ; CHECK-T1-NEXT: ldr r1, .LCPI2_0
217 ; CHECK-T1-NEXT: cmp r0, r1
218 ; CHECK-T1-NEXT: blt .LBB2_2
219 ; CHECK-T1-NEXT: @ %bb.1:
220 ; CHECK-T1-NEXT: mov r0, r1
221 ; CHECK-T1-NEXT: .LBB2_2:
222 ; CHECK-T1-NEXT: ldr r1, .LCPI2_1
223 ; CHECK-T1-NEXT: cmp r0, r1
224 ; CHECK-T1-NEXT: bgt .LBB2_4
225 ; CHECK-T1-NEXT: @ %bb.3:
226 ; CHECK-T1-NEXT: mov r0, r1
227 ; CHECK-T1-NEXT: .LBB2_4:
228 ; CHECK-T1-NEXT: bx lr
229 ; CHECK-T1-NEXT: .p2align 2
230 ; CHECK-T1-NEXT: @ %bb.5:
231 ; CHECK-T1-NEXT: .LCPI2_0:
232 ; CHECK-T1-NEXT: .long 32767 @ 0x7fff
233 ; CHECK-T1-NEXT: .LCPI2_1:
234 ; CHECK-T1-NEXT: .long 4294934528 @ 0xffff8000
235 ;
236 ; CHECK-T2NODSP-LABEL: func16:
237 ; CHECK-T2NODSP: @ %bb.0:
238 ; CHECK-T2NODSP-NEXT: add r0, r1
239 ; CHECK-T2NODSP-NEXT: movw r1, #32767
240 ; CHECK-T2NODSP-NEXT: cmp r0, r1
241 ; CHECK-T2NODSP-NEXT: it lt
242 ; CHECK-T2NODSP-NEXT: movlt r1, r0
243 ; CHECK-T2NODSP-NEXT: movw r0, #32768
244 ; CHECK-T2NODSP-NEXT: cmn.w r1, #32768
245 ; CHECK-T2NODSP-NEXT: movt r0, #65535
246 ; CHECK-T2NODSP-NEXT: it gt
247 ; CHECK-T2NODSP-NEXT: movgt r0, r1
248 ; CHECK-T2NODSP-NEXT: bx lr
249 ;
250 ; CHECK-T2DSP-LABEL: func16:
251 ; CHECK-T2DSP: @ %bb.0:
252 ; CHECK-T2DSP-NEXT: qadd16 r0, r0, r1
253 ; CHECK-T2DSP-NEXT: sxth r0, r0
254 ; CHECK-T2DSP-NEXT: bx lr
255 ;
256 ; CHECK-ARMNODPS-LABEL: func16:
257 ; CHECK-ARMNODPS: @ %bb.0:
258 ; CHECK-ARMNODPS-NEXT: add r0, r0, r1
259 ; CHECK-ARMNODPS-NEXT: mov r1, #255
260 ; CHECK-ARMNODPS-NEXT: orr r1, r1, #32512
261 ; CHECK-ARMNODPS-NEXT: cmp r0, r1
262 ; CHECK-ARMNODPS-NEXT: movlt r1, r0
263 ; CHECK-ARMNODPS-NEXT: ldr r0, .LCPI2_0
264 ; CHECK-ARMNODPS-NEXT: cmn r1, #32768
265 ; CHECK-ARMNODPS-NEXT: movgt r0, r1
266 ; CHECK-ARMNODPS-NEXT: bx lr
267 ; CHECK-ARMNODPS-NEXT: .p2align 2
268 ; CHECK-ARMNODPS-NEXT: @ %bb.1:
269 ; CHECK-ARMNODPS-NEXT: .LCPI2_0:
270 ; CHECK-ARMNODPS-NEXT: .long 4294934528 @ 0xffff8000
271 ;
272 ; CHECK-ARMBASEDSP-LABEL: func16:
273 ; CHECK-ARMBASEDSP: @ %bb.0:
274 ; CHECK-ARMBASEDSP-NEXT: add r0, r0, r1
275 ; CHECK-ARMBASEDSP-NEXT: mov r1, #255
276 ; CHECK-ARMBASEDSP-NEXT: orr r1, r1, #32512
277 ; CHECK-ARMBASEDSP-NEXT: cmp r0, r1
278 ; CHECK-ARMBASEDSP-NEXT: movlt r1, r0
279 ; CHECK-ARMBASEDSP-NEXT: ldr r0, .LCPI2_0
280 ; CHECK-ARMBASEDSP-NEXT: cmn r1, #32768
281 ; CHECK-ARMBASEDSP-NEXT: movgt r0, r1
282 ; CHECK-ARMBASEDSP-NEXT: bx lr
283 ; CHECK-ARMBASEDSP-NEXT: .p2align 2
284 ; CHECK-ARMBASEDSP-NEXT: @ %bb.1:
285 ; CHECK-ARMBASEDSP-NEXT: .LCPI2_0:
286 ; CHECK-ARMBASEDSP-NEXT: .long 4294934528 @ 0xffff8000
287 ;
288 ; CHECK-ARMDSP-LABEL: func16:
289 ; CHECK-ARMDSP: @ %bb.0:
290 ; CHECK-ARMDSP-NEXT: qadd16 r0, r0, r1
291 ; CHECK-ARMDSP-NEXT: sxth r0, r0
292 ; CHECK-ARMDSP-NEXT: bx lr
293 %tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %y)
294 ret i16 %tmp
295 }
297 define signext i8 @func8(i8 signext %x, i8 signext %y) nounwind {
298 ; CHECK-T1-LABEL: func8:
299 ; CHECK-T1: @ %bb.0:
300 ; CHECK-T1-NEXT: adds r0, r0, r1
301 ; CHECK-T1-NEXT: movs r1, #127
302 ; CHECK-T1-NEXT: cmp r0, #127
303 ; CHECK-T1-NEXT: blt .LBB3_2
304 ; CHECK-T1-NEXT: @ %bb.1:
305 ; CHECK-T1-NEXT: mov r0, r1
306 ; CHECK-T1-NEXT: .LBB3_2:
307 ; CHECK-T1-NEXT: mvns r1, r1
308 ; CHECK-T1-NEXT: cmp r0, r1
309 ; CHECK-T1-NEXT: bgt .LBB3_4
310 ; CHECK-T1-NEXT: @ %bb.3:
311 ; CHECK-T1-NEXT: mov r0, r1
312 ; CHECK-T1-NEXT: .LBB3_4:
313 ; CHECK-T1-NEXT: bx lr
314 ;
315 ; CHECK-T2NODSP-LABEL: func8:
316 ; CHECK-T2NODSP: @ %bb.0:
317 ; CHECK-T2NODSP-NEXT: add r0, r1
318 ; CHECK-T2NODSP-NEXT: cmp r0, #127
319 ; CHECK-T2NODSP-NEXT: it ge
320 ; CHECK-T2NODSP-NEXT: movge r0, #127
321 ; CHECK-T2NODSP-NEXT: cmn.w r0, #128
322 ; CHECK-T2NODSP-NEXT: it le
323 ; CHECK-T2NODSP-NEXT: mvnle r0, #127
324 ; CHECK-T2NODSP-NEXT: bx lr
325 ;
326 ; CHECK-T2DSP-LABEL: func8:
327 ; CHECK-T2DSP: @ %bb.0:
328 ; CHECK-T2DSP-NEXT: qadd8 r0, r0, r1
329 ; CHECK-T2DSP-NEXT: sxtb r0, r0
330 ; CHECK-T2DSP-NEXT: bx lr
331 ;
332 ; CHECK-ARMNODPS-LABEL: func8:
333 ; CHECK-ARMNODPS: @ %bb.0:
334 ; CHECK-ARMNODPS-NEXT: add r0, r0, r1
335 ; CHECK-ARMNODPS-NEXT: cmp r0, #127
336 ; CHECK-ARMNODPS-NEXT: movge r0, #127
337 ; CHECK-ARMNODPS-NEXT: cmn r0, #128
338 ; CHECK-ARMNODPS-NEXT: mvnle r0, #127
339 ; CHECK-ARMNODPS-NEXT: bx lr
340 ;
341 ; CHECK-ARMBASEDSP-LABEL: func8:
342 ; CHECK-ARMBASEDSP: @ %bb.0:
343 ; CHECK-ARMBASEDSP-NEXT: add r0, r0, r1
344 ; CHECK-ARMBASEDSP-NEXT: cmp r0, #127
345 ; CHECK-ARMBASEDSP-NEXT: movge r0, #127
346 ; CHECK-ARMBASEDSP-NEXT: cmn r0, #128
347 ; CHECK-ARMBASEDSP-NEXT: mvnle r0, #127
348 ; CHECK-ARMBASEDSP-NEXT: bx lr
349 ;
350 ; CHECK-ARMDSP-LABEL: func8:
351 ; CHECK-ARMDSP: @ %bb.0:
352 ; CHECK-ARMDSP-NEXT: qadd8 r0, r0, r1
353 ; CHECK-ARMDSP-NEXT: sxtb r0, r0
354 ; CHECK-ARMDSP-NEXT: bx lr
355 %tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %y)
356 ret i8 %tmp
357 }
359 define signext i4 @func3(i4 signext %x, i4 signext %y) nounwind {
360 ; CHECK-T1-LABEL: func3:
361 ; CHECK-T1: @ %bb.0:
362 ; CHECK-T1-NEXT: adds r0, r0, r1
363 ; CHECK-T1-NEXT: movs r1, #7
364 ; CHECK-T1-NEXT: cmp r0, #7
365 ; CHECK-T1-NEXT: blt .LBB4_2
366 ; CHECK-T1-NEXT: @ %bb.1:
367 ; CHECK-T1-NEXT: mov r0, r1
368 ; CHECK-T1-NEXT: .LBB4_2:
369 ; CHECK-T1-NEXT: mvns r1, r1
370 ; CHECK-T1-NEXT: cmp r0, r1
371 ; CHECK-T1-NEXT: bgt .LBB4_4
372 ; CHECK-T1-NEXT: @ %bb.3:
373 ; CHECK-T1-NEXT: mov r0, r1
374 ; CHECK-T1-NEXT: .LBB4_4:
375 ; CHECK-T1-NEXT: bx lr
376 ;
377 ; CHECK-T2-LABEL: func3:
378 ; CHECK-T2: @ %bb.0:
379 ; CHECK-T2-NEXT: add r0, r1
380 ; CHECK-T2-NEXT: cmp r0, #7
381 ; CHECK-T2-NEXT: it ge
382 ; CHECK-T2-NEXT: movge r0, #7
383 ; CHECK-T2-NEXT: cmn.w r0, #8
384 ; CHECK-T2-NEXT: it le
385 ; CHECK-T2-NEXT: mvnle r0, #7
386 ; CHECK-T2-NEXT: bx lr
387 ;
388 ; CHECK-ARM-LABEL: func3:
389 ; CHECK-ARM: @ %bb.0:
390 ; CHECK-ARM-NEXT: add r0, r0, r1
391 ; CHECK-ARM-NEXT: cmp r0, #7
392 ; CHECK-ARM-NEXT: movge r0, #7
393 ; CHECK-ARM-NEXT: cmn r0, #8
394 ; CHECK-ARM-NEXT: mvnle r0, #7
395 ; CHECK-ARM-NEXT: bx lr
396 %tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %y)
397 ret i4 %tmp
398 }