| blob | 370d5d989a88fd7fb796b470cd726a32dd411243 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1
3 ; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP
4 ; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP
5 ; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM
7 declare i4 @llvm.sadd.sat.i4(i4, i4)
8 declare i8 @llvm.sadd.sat.i8(i8, i8)
9 declare i16 @llvm.sadd.sat.i16(i16, i16)
10 declare i32 @llvm.sadd.sat.i32(i32, i32)
11 declare i64 @llvm.sadd.sat.i64(i64, i64)
13 define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
14 ; CHECK-T1-LABEL: func32:
15 ; CHECK-T1: @ %bb.0:
16 ; CHECK-T1-NEXT: mov r3, r0
17 ; CHECK-T1-NEXT: muls r1, r2, r1
18 ; CHECK-T1-NEXT: movs r2, #1
19 ; CHECK-T1-NEXT: adds r0, r0, r1
20 ; CHECK-T1-NEXT: mov r1, r2
21 ; CHECK-T1-NEXT: bmi .LBB0_2
22 ; CHECK-T1-NEXT: @ %bb.1:
23 ; CHECK-T1-NEXT: movs r1, #0
24 ; CHECK-T1-NEXT: .LBB0_2:
25 ; CHECK-T1-NEXT: cmp r1, #0
26 ; CHECK-T1-NEXT: bne .LBB0_4
27 ; CHECK-T1-NEXT: @ %bb.3:
28 ; CHECK-T1-NEXT: lsls r1, r2, #31
29 ; CHECK-T1-NEXT: cmp r0, r3
30 ; CHECK-T1-NEXT: bvs .LBB0_5
31 ; CHECK-T1-NEXT: b .LBB0_6
32 ; CHECK-T1-NEXT: .LBB0_4:
33 ; CHECK-T1-NEXT: ldr r1, .LCPI0_0
34 ; CHECK-T1-NEXT: cmp r0, r3
35 ; CHECK-T1-NEXT: bvc .LBB0_6
36 ; CHECK-T1-NEXT: .LBB0_5:
37 ; CHECK-T1-NEXT: mov r0, r1
38 ; CHECK-T1-NEXT: .LBB0_6:
39 ; CHECK-T1-NEXT: bx lr
40 ; CHECK-T1-NEXT: .p2align 2
41 ; CHECK-T1-NEXT: @ %bb.7:
42 ; CHECK-T1-NEXT: .LCPI0_0:
43 ; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
44 ;
45 ; CHECK-T2-LABEL: func32:
46 ; CHECK-T2: @ %bb.0:
47 ; CHECK-T2-NEXT: mla r2, r1, r2, r0
48 ; CHECK-T2-NEXT: movs r3, #0
49 ; CHECK-T2-NEXT: mov.w r1, #-2147483648
50 ; CHECK-T2-NEXT: cmp r2, #0
51 ; CHECK-T2-NEXT: it mi
52 ; CHECK-T2-NEXT: movmi r3, #1
53 ; CHECK-T2-NEXT: cmp r3, #0
54 ; CHECK-T2-NEXT: it ne
55 ; CHECK-T2-NEXT: mvnne r1, #-2147483648
56 ; CHECK-T2-NEXT: cmp r2, r0
57 ; CHECK-T2-NEXT: it vc
58 ; CHECK-T2-NEXT: movvc r1, r2
59 ; CHECK-T2-NEXT: mov r0, r1
60 ; CHECK-T2-NEXT: bx lr
61 ;
62 ; CHECK-ARM-LABEL: func32:
63 ; CHECK-ARM: @ %bb.0:
64 ; CHECK-ARM-NEXT: mla r2, r1, r2, r0
65 ; CHECK-ARM-NEXT: mov r3, #0
66 ; CHECK-ARM-NEXT: mov r1, #-2147483648
67 ; CHECK-ARM-NEXT: cmp r2, #0
68 ; CHECK-ARM-NEXT: movwmi r3, #1
69 ; CHECK-ARM-NEXT: cmp r3, #0
70 ; CHECK-ARM-NEXT: mvnne r1, #-2147483648
71 ; CHECK-ARM-NEXT: cmp r2, r0
72 ; CHECK-ARM-NEXT: movvc r1, r2
73 ; CHECK-ARM-NEXT: mov r0, r1
74 ; CHECK-ARM-NEXT: bx lr
75 %a = mul i32 %y, %z
76 %tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %a)
77 ret i32 %tmp
78 }
80 define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
81 ; CHECK-T1-LABEL: func64:
82 ; CHECK-T1: @ %bb.0:
83 ; CHECK-T1-NEXT: .save {r4, r5, r6, r7, lr}
84 ; CHECK-T1-NEXT: push {r4, r5, r6, r7, lr}
85 ; CHECK-T1-NEXT: .pad #4
86 ; CHECK-T1-NEXT: sub sp, #4
87 ; CHECK-T1-NEXT: ldr r5, [sp, #28]
88 ; CHECK-T1-NEXT: movs r2, #1
89 ; CHECK-T1-NEXT: movs r4, #0
90 ; CHECK-T1-NEXT: cmp r5, #0
91 ; CHECK-T1-NEXT: mov r3, r2
92 ; CHECK-T1-NEXT: bge .LBB1_2
93 ; CHECK-T1-NEXT: @ %bb.1:
94 ; CHECK-T1-NEXT: mov r3, r4
95 ; CHECK-T1-NEXT: .LBB1_2:
96 ; CHECK-T1-NEXT: cmp r1, #0
97 ; CHECK-T1-NEXT: mov r6, r2
98 ; CHECK-T1-NEXT: bge .LBB1_4
99 ; CHECK-T1-NEXT: @ %bb.3:
100 ; CHECK-T1-NEXT: mov r6, r4
101 ; CHECK-T1-NEXT: .LBB1_4:
102 ; CHECK-T1-NEXT: subs r7, r6, r3
103 ; CHECK-T1-NEXT: rsbs r3, r7, #0
104 ; CHECK-T1-NEXT: adcs r3, r7
105 ; CHECK-T1-NEXT: ldr r7, [sp, #24]
106 ; CHECK-T1-NEXT: adds r0, r0, r7
107 ; CHECK-T1-NEXT: adcs r1, r5
108 ; CHECK-T1-NEXT: cmp r1, #0
109 ; CHECK-T1-NEXT: mov r5, r2
110 ; CHECK-T1-NEXT: bge .LBB1_6
111 ; CHECK-T1-NEXT: @ %bb.5:
112 ; CHECK-T1-NEXT: mov r5, r4
113 ; CHECK-T1-NEXT: .LBB1_6:
114 ; CHECK-T1-NEXT: subs r4, r6, r5
115 ; CHECK-T1-NEXT: subs r5, r4, #1
116 ; CHECK-T1-NEXT: sbcs r4, r5
117 ; CHECK-T1-NEXT: ands r3, r4
118 ; CHECK-T1-NEXT: beq .LBB1_8
119 ; CHECK-T1-NEXT: @ %bb.7:
120 ; CHECK-T1-NEXT: asrs r0, r1, #31
121 ; CHECK-T1-NEXT: .LBB1_8:
122 ; CHECK-T1-NEXT: cmp r1, #0
123 ; CHECK-T1-NEXT: bmi .LBB1_10
124 ; CHECK-T1-NEXT: @ %bb.9:
125 ; CHECK-T1-NEXT: lsls r2, r2, #31
126 ; CHECK-T1-NEXT: cmp r3, #0
127 ; CHECK-T1-NEXT: beq .LBB1_11
128 ; CHECK-T1-NEXT: b .LBB1_12
129 ; CHECK-T1-NEXT: .LBB1_10:
130 ; CHECK-T1-NEXT: ldr r2, .LCPI1_0
131 ; CHECK-T1-NEXT: cmp r3, #0
132 ; CHECK-T1-NEXT: bne .LBB1_12
133 ; CHECK-T1-NEXT: .LBB1_11:
134 ; CHECK-T1-NEXT: mov r2, r1
135 ; CHECK-T1-NEXT: .LBB1_12:
136 ; CHECK-T1-NEXT: mov r1, r2
137 ; CHECK-T1-NEXT: add sp, #4
138 ; CHECK-T1-NEXT: pop {r4, r5, r6, r7, pc}
139 ; CHECK-T1-NEXT: .p2align 2
140 ; CHECK-T1-NEXT: @ %bb.13:
141 ; CHECK-T1-NEXT: .LCPI1_0:
142 ; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
143 ;
144 ; CHECK-T2-LABEL: func64:
145 ; CHECK-T2: @ %bb.0:
146 ; CHECK-T2-NEXT: .save {r7, lr}
147 ; CHECK-T2-NEXT: push {r7, lr}
148 ; CHECK-T2-NEXT: ldrd r2, r12, [sp, #8]
149 ; CHECK-T2-NEXT: cmp.w r1, #-1
150 ; CHECK-T2-NEXT: mov.w r3, #0
151 ; CHECK-T2-NEXT: mov.w lr, #0
152 ; CHECK-T2-NEXT: it gt
153 ; CHECK-T2-NEXT: movgt r3, #1
154 ; CHECK-T2-NEXT: adds r0, r0, r2
155 ; CHECK-T2-NEXT: adc.w r2, r1, r12
156 ; CHECK-T2-NEXT: movs r1, #0
157 ; CHECK-T2-NEXT: cmp.w r2, #-1
158 ; CHECK-T2-NEXT: it gt
159 ; CHECK-T2-NEXT: movgt r1, #1
160 ; CHECK-T2-NEXT: subs r1, r3, r1
161 ; CHECK-T2-NEXT: it ne
162 ; CHECK-T2-NEXT: movne r1, #1
163 ; CHECK-T2-NEXT: cmp.w r12, #-1
164 ; CHECK-T2-NEXT: it gt
165 ; CHECK-T2-NEXT: movgt.w lr, #1
166 ; CHECK-T2-NEXT: sub.w r3, r3, lr
167 ; CHECK-T2-NEXT: clz r3, r3
168 ; CHECK-T2-NEXT: lsrs r3, r3, #5
169 ; CHECK-T2-NEXT: ands r3, r1
170 ; CHECK-T2-NEXT: mov.w r1, #-2147483648
171 ; CHECK-T2-NEXT: it ne
172 ; CHECK-T2-NEXT: asrne r0, r2, #31
173 ; CHECK-T2-NEXT: cmp r2, #0
174 ; CHECK-T2-NEXT: it mi
175 ; CHECK-T2-NEXT: mvnmi r1, #-2147483648
176 ; CHECK-T2-NEXT: cmp r3, #0
177 ; CHECK-T2-NEXT: it eq
178 ; CHECK-T2-NEXT: moveq r1, r2
179 ; CHECK-T2-NEXT: pop {r7, pc}
180 ;
181 ; CHECK-ARM-LABEL: func64:
182 ; CHECK-ARM: @ %bb.0:
183 ; CHECK-ARM-NEXT: .save {r11, lr}
184 ; CHECK-ARM-NEXT: push {r11, lr}
185 ; CHECK-ARM-NEXT: ldr r2, [sp, #8]
186 ; CHECK-ARM-NEXT: mov r3, #0
187 ; CHECK-ARM-NEXT: ldr r12, [sp, #12]
188 ; CHECK-ARM-NEXT: adds r0, r0, r2
189 ; CHECK-ARM-NEXT: mov r2, #0
190 ; CHECK-ARM-NEXT: adc lr, r1, r12
191 ; CHECK-ARM-NEXT: cmn r1, #1
192 ; CHECK-ARM-NEXT: mov r1, #0
193 ; CHECK-ARM-NEXT: movwgt r1, #1
194 ; CHECK-ARM-NEXT: cmn lr, #1
195 ; CHECK-ARM-NEXT: movwgt r2, #1
196 ; CHECK-ARM-NEXT: subs r2, r1, r2
197 ; CHECK-ARM-NEXT: movwne r2, #1
198 ; CHECK-ARM-NEXT: cmn r12, #1
199 ; CHECK-ARM-NEXT: movwgt r3, #1
200 ; CHECK-ARM-NEXT: sub r1, r1, r3
201 ; CHECK-ARM-NEXT: clz r1, r1
202 ; CHECK-ARM-NEXT: lsr r1, r1, #5
203 ; CHECK-ARM-NEXT: ands r2, r1, r2
204 ; CHECK-ARM-NEXT: asrne r0, lr, #31
205 ; CHECK-ARM-NEXT: mov r1, #-2147483648
206 ; CHECK-ARM-NEXT: cmp lr, #0
207 ; CHECK-ARM-NEXT: mvnmi r1, #-2147483648
208 ; CHECK-ARM-NEXT: cmp r2, #0
209 ; CHECK-ARM-NEXT: moveq r1, lr
210 ; CHECK-ARM-NEXT: pop {r11, pc}
211 %a = mul i64 %y, %z
212 %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %z)
213 ret i64 %tmp
214 }
216 define signext i16 @func16(i16 signext %x, i16 signext %y, i16 signext %z) nounwind {
217 ; CHECK-T1-LABEL: func16:
218 ; CHECK-T1: @ %bb.0:
219 ; CHECK-T1-NEXT: muls r1, r2, r1
220 ; CHECK-T1-NEXT: sxth r1, r1
221 ; CHECK-T1-NEXT: adds r0, r0, r1
222 ; CHECK-T1-NEXT: ldr r1, .LCPI2_0
223 ; CHECK-T1-NEXT: cmp r0, r1
224 ; CHECK-T1-NEXT: blt .LBB2_2
225 ; CHECK-T1-NEXT: @ %bb.1:
226 ; CHECK-T1-NEXT: mov r0, r1
227 ; CHECK-T1-NEXT: .LBB2_2:
228 ; CHECK-T1-NEXT: ldr r1, .LCPI2_1
229 ; CHECK-T1-NEXT: cmp r0, r1
230 ; CHECK-T1-NEXT: bgt .LBB2_4
231 ; CHECK-T1-NEXT: @ %bb.3:
232 ; CHECK-T1-NEXT: mov r0, r1
233 ; CHECK-T1-NEXT: .LBB2_4:
234 ; CHECK-T1-NEXT: bx lr
235 ; CHECK-T1-NEXT: .p2align 2
236 ; CHECK-T1-NEXT: @ %bb.5:
237 ; CHECK-T1-NEXT: .LCPI2_0:
238 ; CHECK-T1-NEXT: .long 32767 @ 0x7fff
239 ; CHECK-T1-NEXT: .LCPI2_1:
240 ; CHECK-T1-NEXT: .long 4294934528 @ 0xffff8000
241 ;
242 ; CHECK-T2NODSP-LABEL: func16:
243 ; CHECK-T2NODSP: @ %bb.0:
244 ; CHECK-T2NODSP-NEXT: muls r1, r2, r1
245 ; CHECK-T2NODSP-NEXT: sxth r1, r1
246 ; CHECK-T2NODSP-NEXT: add r0, r1
247 ; CHECK-T2NODSP-NEXT: movw r1, #32767
248 ; CHECK-T2NODSP-NEXT: cmp r0, r1
249 ; CHECK-T2NODSP-NEXT: it lt
250 ; CHECK-T2NODSP-NEXT: movlt r1, r0
251 ; CHECK-T2NODSP-NEXT: movw r0, #32768
252 ; CHECK-T2NODSP-NEXT: movt r0, #65535
253 ; CHECK-T2NODSP-NEXT: cmn.w r1, #32768
254 ; CHECK-T2NODSP-NEXT: it gt
255 ; CHECK-T2NODSP-NEXT: movgt r0, r1
256 ; CHECK-T2NODSP-NEXT: bx lr
257 ;
258 ; CHECK-T2DSP-LABEL: func16:
259 ; CHECK-T2DSP: @ %bb.0:
260 ; CHECK-T2DSP-NEXT: muls r1, r2, r1
261 ; CHECK-T2DSP-NEXT: qadd16 r0, r0, r1
262 ; CHECK-T2DSP-NEXT: sxth r0, r0
263 ; CHECK-T2DSP-NEXT: bx lr
264 ;
265 ; CHECK-ARM-LABEL: func16:
266 ; CHECK-ARM: @ %bb.0:
267 ; CHECK-ARM-NEXT: smulbb r1, r1, r2
268 ; CHECK-ARM-NEXT: qadd16 r0, r0, r1
269 ; CHECK-ARM-NEXT: sxth r0, r0
270 ; CHECK-ARM-NEXT: bx lr
271 %a = mul i16 %y, %z
272 %tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %a)
273 ret i16 %tmp
274 }
276 define signext i8 @func8(i8 signext %x, i8 signext %y, i8 signext %z) nounwind {
277 ; CHECK-T1-LABEL: func8:
278 ; CHECK-T1: @ %bb.0:
279 ; CHECK-T1-NEXT: muls r1, r2, r1
280 ; CHECK-T1-NEXT: sxtb r1, r1
281 ; CHECK-T1-NEXT: adds r0, r0, r1
282 ; CHECK-T1-NEXT: movs r1, #127
283 ; CHECK-T1-NEXT: cmp r0, #127
284 ; CHECK-T1-NEXT: blt .LBB3_2
285 ; CHECK-T1-NEXT: @ %bb.1:
286 ; CHECK-T1-NEXT: mov r0, r1
287 ; CHECK-T1-NEXT: .LBB3_2:
288 ; CHECK-T1-NEXT: mvns r1, r1
289 ; CHECK-T1-NEXT: cmp r0, r1
290 ; CHECK-T1-NEXT: bgt .LBB3_4
291 ; CHECK-T1-NEXT: @ %bb.3:
292 ; CHECK-T1-NEXT: mov r0, r1
293 ; CHECK-T1-NEXT: .LBB3_4:
294 ; CHECK-T1-NEXT: bx lr
295 ;
296 ; CHECK-T2NODSP-LABEL: func8:
297 ; CHECK-T2NODSP: @ %bb.0:
298 ; CHECK-T2NODSP-NEXT: muls r1, r2, r1
299 ; CHECK-T2NODSP-NEXT: sxtb r1, r1
300 ; CHECK-T2NODSP-NEXT: add r0, r1
301 ; CHECK-T2NODSP-NEXT: cmp r0, #127
302 ; CHECK-T2NODSP-NEXT: it ge
303 ; CHECK-T2NODSP-NEXT: movge r0, #127
304 ; CHECK-T2NODSP-NEXT: cmn.w r0, #128
305 ; CHECK-T2NODSP-NEXT: it le
306 ; CHECK-T2NODSP-NEXT: mvnle r0, #127
307 ; CHECK-T2NODSP-NEXT: bx lr
308 ;
309 ; CHECK-T2DSP-LABEL: func8:
310 ; CHECK-T2DSP: @ %bb.0:
311 ; CHECK-T2DSP-NEXT: muls r1, r2, r1
312 ; CHECK-T2DSP-NEXT: qadd8 r0, r0, r1
313 ; CHECK-T2DSP-NEXT: sxtb r0, r0
314 ; CHECK-T2DSP-NEXT: bx lr
315 ;
316 ; CHECK-ARM-LABEL: func8:
317 ; CHECK-ARM: @ %bb.0:
318 ; CHECK-ARM-NEXT: smulbb r1, r1, r2
319 ; CHECK-ARM-NEXT: qadd8 r0, r0, r1
320 ; CHECK-ARM-NEXT: sxtb r0, r0
321 ; CHECK-ARM-NEXT: bx lr
322 %a = mul i8 %y, %z
323 %tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %a)
324 ret i8 %tmp
325 }
327 define signext i4 @func4(i4 signext %x, i4 signext %y, i4 signext %z) nounwind {
328 ; CHECK-T1-LABEL: func4:
329 ; CHECK-T1: @ %bb.0:
330 ; CHECK-T1-NEXT: muls r1, r2, r1
331 ; CHECK-T1-NEXT: lsls r1, r1, #28
332 ; CHECK-T1-NEXT: asrs r1, r1, #28
333 ; CHECK-T1-NEXT: adds r0, r0, r1
334 ; CHECK-T1-NEXT: movs r1, #7
335 ; CHECK-T1-NEXT: cmp r0, #7
336 ; CHECK-T1-NEXT: blt .LBB4_2
337 ; CHECK-T1-NEXT: @ %bb.1:
338 ; CHECK-T1-NEXT: mov r0, r1
339 ; CHECK-T1-NEXT: .LBB4_2:
340 ; CHECK-T1-NEXT: mvns r1, r1
341 ; CHECK-T1-NEXT: cmp r0, r1
342 ; CHECK-T1-NEXT: bgt .LBB4_4
343 ; CHECK-T1-NEXT: @ %bb.3:
344 ; CHECK-T1-NEXT: mov r0, r1
345 ; CHECK-T1-NEXT: .LBB4_4:
346 ; CHECK-T1-NEXT: bx lr
347 ;
348 ; CHECK-T2-LABEL: func4:
349 ; CHECK-T2: @ %bb.0:
350 ; CHECK-T2-NEXT: muls r1, r2, r1
351 ; CHECK-T2-NEXT: lsls r1, r1, #28
352 ; CHECK-T2-NEXT: add.w r0, r0, r1, asr #28
353 ; CHECK-T2-NEXT: cmp r0, #7
354 ; CHECK-T2-NEXT: it ge
355 ; CHECK-T2-NEXT: movge r0, #7
356 ; CHECK-T2-NEXT: cmn.w r0, #8
357 ; CHECK-T2-NEXT: it le
358 ; CHECK-T2-NEXT: mvnle r0, #7
359 ; CHECK-T2-NEXT: bx lr
360 ;
361 ; CHECK-ARM-LABEL: func4:
362 ; CHECK-ARM: @ %bb.0:
363 ; CHECK-ARM-NEXT: smulbb r1, r1, r2
364 ; CHECK-ARM-NEXT: lsl r1, r1, #28
365 ; CHECK-ARM-NEXT: add r0, r0, r1, asr #28
366 ; CHECK-ARM-NEXT: cmp r0, #7
367 ; CHECK-ARM-NEXT: movge r0, #7
368 ; CHECK-ARM-NEXT: cmn r0, #8
369 ; CHECK-ARM-NEXT: mvnle r0, #7
370 ; CHECK-ARM-NEXT: bx lr
371 %a = mul i4 %y, %z
372 %tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %a)
373 ret i4 %tmp
374 }