include/llvm/CodeGen/SelectionDAGISel.h

   1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file implements the SelectionDAGISel class, which is used as the common
  10 // base class for SelectionDAG-based instruction selectors.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H
  15 #define LLVM_CODEGEN_SELECTIONDAGISEL_H
  16
  17 #include "llvm/CodeGen/MachineFunctionPass.h"
  18 #include "llvm/CodeGen/SelectionDAG.h"
  19 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  20 #include "llvm/IR/BasicBlock.h"
  21 #include "llvm/Pass.h"
  22 #include <memory>
  23
  24 namespace llvm {
  25 class AAResults;
  26 class FastISel;
  27 class SelectionDAGBuilder;
  28 class SDValue;
  29 class MachineRegisterInfo;
  30 class MachineBasicBlock;
  31 class MachineFunction;
  32 class MachineInstr;
  33 class OptimizationRemarkEmitter;
  34 class TargetLowering;
  35 class TargetLibraryInfo;
  36 class FunctionLoweringInfo;
  37 class ScheduleHazardRecognizer;
  38 class SwiftErrorValueTracking;
  39 class GCFunctionInfo;
  40 class ScheduleDAGSDNodes;
  41 class LoadInst;
  42
  43 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
  44 /// pattern-matching instruction selectors.
  45 class SelectionDAGISel : public MachineFunctionPass {
  46 public:
  47   TargetMachine &TM;
  48   const TargetLibraryInfo *LibInfo;
  49   FunctionLoweringInfo *FuncInfo;
  50   SwiftErrorValueTracking *SwiftError;
  51   MachineFunction *MF;
  52   MachineRegisterInfo *RegInfo;
  53   SelectionDAG *CurDAG;
  54   SelectionDAGBuilder *SDB;
  55   AAResults *AA;
  56   GCFunctionInfo *GFI;
  57   CodeGenOpt::Level OptLevel;
  58   const TargetInstrInfo *TII;
  59   const TargetLowering *TLI;
  60   bool FastISelFailed;
  61   SmallPtrSet<const Instruction *, 4> ElidedArgCopyInstrs;
  62
  63   /// Current optimization remark emitter.
  64   /// Used to report things like combines and FastISel failures.
  65   std::unique_ptr<OptimizationRemarkEmitter> ORE;
  66
  67   static char ID;
  68
  69   explicit SelectionDAGISel(TargetMachine &tm,
  70                             CodeGenOpt::Level OL = CodeGenOpt::Default);
  71   ~SelectionDAGISel() override;
  72
  73   const TargetLowering *getTargetLowering() const { return TLI; }
  74
  75   void getAnalysisUsage(AnalysisUsage &AU) const override;
  76
  77   bool runOnMachineFunction(MachineFunction &MF) override;
  78
  79   virtual void EmitFunctionEntryCode() {}
  80
  81   /// PreprocessISelDAG - This hook allows targets to hack on the graph before
  82   /// instruction selection starts.
  83   virtual void PreprocessISelDAG() {}
  84
  85   /// PostprocessISelDAG() - This hook allows the target to hack on the graph
  86   /// right after selection.
  87   virtual void PostprocessISelDAG() {}
  88
  89   /// Main hook for targets to transform nodes into machine nodes.
  90   virtual void Select(SDNode *N) = 0;
  91
  92   /// SelectInlineAsmMemoryOperand - Select the specified address as a target
  93   /// addressing mode, according to the specified constraint.  If this does
  94   /// not match or is not implemented, return true.  The resultant operands
  95   /// (which will appear in the machine instruction) should be added to the
  96   /// OutOps vector.
  97   virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
  98                                             unsigned ConstraintID,
  99                                             std::vector<SDValue> &OutOps) {
 100     return true;
 101   }
 102
 103   /// IsProfitableToFold - Returns true if it's profitable to fold the specific
 104   /// operand node N of U during instruction selection that starts at Root.
 105   virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
 106
 107   /// IsLegalToFold - Returns true if the specific operand node N of
 108   /// U can be folded during instruction selection that starts at Root.
 109   /// FIXME: This is a static member function because the MSP430/X86
 110   /// targets, which uses it during isel.  This could become a proper member.
 111   static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
 112                             CodeGenOpt::Level OptLevel,
 113                             bool IgnoreChains = false);
 114
 115   static void InvalidateNodeId(SDNode *N);
 116   static int getUninvalidatedNodeId(SDNode *N);
 117
 118   static void EnforceNodeIdInvariant(SDNode *N);
 119
 120   // Opcodes used by the DAG state machine:
 121   enum BuiltinOpcodes {
 122     OPC_Scope,
 123     OPC_RecordNode,
 124     OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3,
 125     OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7,
 126     OPC_RecordMemRef,
 127     OPC_CaptureGlueInput,
 128     OPC_MoveChild,
 129     OPC_MoveChild0, OPC_MoveChild1, OPC_MoveChild2, OPC_MoveChild3,
 130     OPC_MoveChild4, OPC_MoveChild5, OPC_MoveChild6, OPC_MoveChild7,
 131     OPC_MoveParent,
 132     OPC_CheckSame,
 133     OPC_CheckChild0Same, OPC_CheckChild1Same,
 134     OPC_CheckChild2Same, OPC_CheckChild3Same,
 135     OPC_CheckPatternPredicate,
 136     OPC_CheckPredicate,
 137     OPC_CheckPredicateWithOperands,
 138     OPC_CheckOpcode,
 139     OPC_SwitchOpcode,
 140     OPC_CheckType,
 141     OPC_CheckTypeRes,
 142     OPC_SwitchType,
 143     OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type,
 144     OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type,
 145     OPC_CheckChild6Type, OPC_CheckChild7Type,
 146     OPC_CheckInteger,
 147     OPC_CheckChild0Integer, OPC_CheckChild1Integer, OPC_CheckChild2Integer,
 148     OPC_CheckChild3Integer, OPC_CheckChild4Integer,
 149     OPC_CheckCondCode, OPC_CheckChild2CondCode,
 150     OPC_CheckValueType,
 151     OPC_CheckComplexPat,
 152     OPC_CheckAndImm, OPC_CheckOrImm,
 153     OPC_CheckImmAllOnesV,
 154     OPC_CheckImmAllZerosV,
 155     OPC_CheckFoldableChainNode,
 156
 157     OPC_EmitInteger,
 158     OPC_EmitRegister,
 159     OPC_EmitRegister2,
 160     OPC_EmitConvertToTarget,
 161     OPC_EmitMergeInputChains,
 162     OPC_EmitMergeInputChains1_0,
 163     OPC_EmitMergeInputChains1_1,
 164     OPC_EmitMergeInputChains1_2,
 165     OPC_EmitCopyToReg,
 166     OPC_EmitCopyToReg2,
 167     OPC_EmitNodeXForm,
 168     OPC_EmitNode,
 169     // Space-optimized forms that implicitly encode number of result VTs.
 170     OPC_EmitNode0, OPC_EmitNode1, OPC_EmitNode2,
 171     OPC_MorphNodeTo,
 172     // Space-optimized forms that implicitly encode number of result VTs.
 173     OPC_MorphNodeTo0, OPC_MorphNodeTo1, OPC_MorphNodeTo2,
 174     OPC_CompleteMatch,
 175     // Contains offset in table for pattern being selected
 176     OPC_Coverage
 177   };
 178
 179   enum {
 180     OPFL_None       = 0,  // Node has no chain or glue input and isn't variadic.
 181     OPFL_Chain      = 1,     // Node has a chain input.
 182     OPFL_GlueInput  = 2,     // Node has a glue input.
 183     OPFL_GlueOutput = 4,     // Node has a glue output.
 184     OPFL_MemRefs    = 8,     // Node gets accumulated MemRefs.
 185     OPFL_Variadic0  = 1<<4,  // Node is variadic, root has 0 fixed inputs.
 186     OPFL_Variadic1  = 2<<4,  // Node is variadic, root has 1 fixed inputs.
 187     OPFL_Variadic2  = 3<<4,  // Node is variadic, root has 2 fixed inputs.
 188     OPFL_Variadic3  = 4<<4,  // Node is variadic, root has 3 fixed inputs.
 189     OPFL_Variadic4  = 5<<4,  // Node is variadic, root has 4 fixed inputs.
 190     OPFL_Variadic5  = 6<<4,  // Node is variadic, root has 5 fixed inputs.
 191     OPFL_Variadic6  = 7<<4,  // Node is variadic, root has 6 fixed inputs.
 192
 193     OPFL_VariadicInfo = OPFL_Variadic6
 194   };
 195
 196   /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the
 197   /// number of fixed arity values that should be skipped when copying from the
 198   /// root.
 199   static inline int getNumFixedFromVariadicInfo(unsigned Flags) {
 200     return ((Flags&OPFL_VariadicInfo) >> 4)-1;
 201   }
 202
 203
 204 protected:
 205   /// DAGSize - Size of DAG being instruction selected.
 206   ///
 207   unsigned DAGSize;
 208
 209   /// ReplaceUses - replace all uses of the old node F with the use
 210   /// of the new node T.
 211   void ReplaceUses(SDValue F, SDValue T) {
 212     CurDAG->ReplaceAllUsesOfValueWith(F, T);
 213     EnforceNodeIdInvariant(T.getNode());
 214   }
 215
 216   /// ReplaceUses - replace all uses of the old nodes F with the use
 217   /// of the new nodes T.
 218   void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) {
 219     CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num);
 220     for (unsigned i = 0; i < Num; ++i)
 221       EnforceNodeIdInvariant(T[i].getNode());
 222   }
 223
 224   /// ReplaceUses - replace all uses of the old node F with the use
 225   /// of the new node T.
 226   void ReplaceUses(SDNode *F, SDNode *T) {
 227     CurDAG->ReplaceAllUsesWith(F, T);
 228     EnforceNodeIdInvariant(T);
 229   }
 230
 231   /// Replace all uses of \c F with \c T, then remove \c F from the DAG.
 232   void ReplaceNode(SDNode *F, SDNode *T) {
 233     CurDAG->ReplaceAllUsesWith(F, T);
 234     EnforceNodeIdInvariant(T);
 235     CurDAG->RemoveDeadNode(F);
 236   }
 237
 238   /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
 239   /// by tblgen.  Others should not call it.
 240   void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
 241                                      const SDLoc &DL);
 242
 243   /// getPatternForIndex - Patterns selected by tablegen during ISEL
 244   virtual StringRef getPatternForIndex(unsigned index) {
 245     llvm_unreachable("Tblgen should generate the implementation of this!");
 246   }
 247
 248   /// getIncludePathForIndex - get the td source location of pattern instantiation
 249   virtual StringRef getIncludePathForIndex(unsigned index) {
 250     llvm_unreachable("Tblgen should generate the implementation of this!");
 251   }
 252 public:
 253   // Calls to these predicates are generated by tblgen.
 254   bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
 255                     int64_t DesiredMaskS) const;
 256   bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
 257                     int64_t DesiredMaskS) const;
 258
 259
 260   /// CheckPatternPredicate - This function is generated by tblgen in the
 261   /// target.  It runs the specified pattern predicate and returns true if it
 262   /// succeeds or false if it fails.  The number is a private implementation
 263   /// detail to the code tblgen produces.
 264   virtual bool CheckPatternPredicate(unsigned PredNo) const {
 265     llvm_unreachable("Tblgen should generate the implementation of this!");
 266   }
 267
 268   /// CheckNodePredicate - This function is generated by tblgen in the target.
 269   /// It runs node predicate number PredNo and returns true if it succeeds or
 270   /// false if it fails.  The number is a private implementation
 271   /// detail to the code tblgen produces.
 272   virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {
 273     llvm_unreachable("Tblgen should generate the implementation of this!");
 274   }
 275
 276   /// CheckNodePredicateWithOperands - This function is generated by tblgen in
 277   /// the target.
 278   /// It runs node predicate number PredNo and returns true if it succeeds or
 279   /// false if it fails.  The number is a private implementation detail to the
 280   /// code tblgen produces.
 281   virtual bool CheckNodePredicateWithOperands(
 282       SDNode *N, unsigned PredNo,
 283       const SmallVectorImpl<SDValue> &Operands) const {
 284     llvm_unreachable("Tblgen should generate the implementation of this!");
 285   }
 286
 287   virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N,
 288                                    unsigned PatternNo,
 289                         SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) {
 290     llvm_unreachable("Tblgen should generate the implementation of this!");
 291   }
 292
 293   virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
 294     llvm_unreachable("Tblgen should generate this!");
 295   }
 296
 297   void SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
 298                         unsigned TableSize);
 299
 300   /// Return true if complex patterns for this target can mutate the
 301   /// DAG.
 302   virtual bool ComplexPatternFuncMutatesDAG() const {
 303     return false;
 304   }
 305
 306   bool isOrEquivalentToAdd(const SDNode *N) const;
 307
 308 private:
 309
 310   // Calls to these functions are generated by tblgen.
 311   void Select_INLINEASM(SDNode *N, bool Branch);
 312   void Select_READ_REGISTER(SDNode *Op);
 313   void Select_WRITE_REGISTER(SDNode *Op);
 314   void Select_UNDEF(SDNode *N);
 315   void CannotYetSelect(SDNode *N);
 316
 317 private:
 318   void DoInstructionSelection();
 319   SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
 320                     ArrayRef<SDValue> Ops, unsigned EmitNodeInfo);
 321
 322   SDNode *MutateStrictFPToFP(SDNode *Node, unsigned NewOpc);
 323
 324   /// Prepares the landing pad to take incoming values or do other EH
 325   /// personality specific tasks. Returns true if the block should be
 326   /// instruction selected, false if no code should be emitted for it.
 327   bool PrepareEHLandingPad();
 328
 329   /// Perform instruction selection on all basic blocks in the function.
 330   void SelectAllBasicBlocks(const Function &Fn);
 331
 332   /// Perform instruction selection on a single basic block, for
 333   /// instructions between \p Begin and \p End.  \p HadTailCall will be set
 334   /// to true if a call in the block was translated as a tail call.
 335   void SelectBasicBlock(BasicBlock::const_iterator Begin,
 336                         BasicBlock::const_iterator End,
 337                         bool &HadTailCall);
 338   void FinishBasicBlock();
 339
 340   void CodeGenAndEmitDAG();
 341
 342   /// Generate instructions for lowering the incoming arguments of the
 343   /// given function.
 344   void LowerArguments(const Function &F);
 345
 346   void ComputeLiveOutVRegInfo();
 347
 348   /// Create the scheduler. If a specific scheduler was specified
 349   /// via the SchedulerRegistry, use it, otherwise select the
 350   /// one preferred by the target.
 351   ///
 352   ScheduleDAGSDNodes *CreateScheduler();
 353
 354   /// OpcodeOffset - This is a cache used to dispatch efficiently into isel
 355   /// state machines that start with a OPC_SwitchOpcode node.
 356   std::vector<unsigned> OpcodeOffset;
 357
 358   void UpdateChains(SDNode *NodeToMatch, SDValue InputChain,
 359                     SmallVectorImpl<SDNode *> &ChainNodesMatched,
 360                     bool isMorphNodeTo);
 361 };
 362
 363 }
 364
 365 #endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */