include/llvm/IR/IntrinsicsRISCV.td

   1 //===- IntrinsicsRISCV.td - Defines RISCV intrinsics -------*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines all of the RISCV-specific intrinsics.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 let TargetPrefix = "riscv" in {
  14
  15 //===----------------------------------------------------------------------===//
  16 // Atomics
  17
  18 class MaskedAtomicRMW32Intrinsic
  19     : Intrinsic<[llvm_i32_ty],
  20                 [llvm_anyptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
  21                 [IntrArgMemOnly, NoCapture<0>, ImmArg<3>]>;
  22
  23 class MaskedAtomicRMW32WithSextIntrinsic
  24     : Intrinsic<[llvm_i32_ty],
  25                 [llvm_anyptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  26                  llvm_i32_ty],
  27                 [IntrArgMemOnly, NoCapture<0>, ImmArg<4>]>;
  28
  29 def int_riscv_masked_atomicrmw_xchg_i32 : MaskedAtomicRMW32Intrinsic;
  30 def int_riscv_masked_atomicrmw_add_i32  : MaskedAtomicRMW32Intrinsic;
  31 def int_riscv_masked_atomicrmw_sub_i32  : MaskedAtomicRMW32Intrinsic;
  32 def int_riscv_masked_atomicrmw_nand_i32 : MaskedAtomicRMW32Intrinsic;
  33 def int_riscv_masked_atomicrmw_max_i32  : MaskedAtomicRMW32WithSextIntrinsic;
  34 def int_riscv_masked_atomicrmw_min_i32  : MaskedAtomicRMW32WithSextIntrinsic;
  35 def int_riscv_masked_atomicrmw_umax_i32 : MaskedAtomicRMW32Intrinsic;
  36 def int_riscv_masked_atomicrmw_umin_i32 : MaskedAtomicRMW32Intrinsic;
  37
  38 def int_riscv_masked_cmpxchg_i32
  39     : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty, llvm_i32_ty, llvm_i32_ty,
  40                                 llvm_i32_ty, llvm_i32_ty],
  41                 [IntrArgMemOnly, NoCapture<0>, ImmArg<4>]>;
  42
  43 class MaskedAtomicRMW64Intrinsic
  44     : Intrinsic<[llvm_i64_ty],
  45                 [llvm_anyptr_ty, llvm_i64_ty, llvm_i64_ty, llvm_i64_ty],
  46                 [IntrArgMemOnly, NoCapture<0>, ImmArg<3>]>;
  47
  48 class MaskedAtomicRMW64WithSextIntrinsic
  49     : Intrinsic<[llvm_i64_ty],
  50                 [llvm_anyptr_ty, llvm_i64_ty, llvm_i64_ty, llvm_i64_ty,
  51                  llvm_i64_ty],
  52                 [IntrArgMemOnly, NoCapture<0>, ImmArg<4>]>;
  53
  54 def int_riscv_masked_atomicrmw_xchg_i64 : MaskedAtomicRMW64Intrinsic;
  55 def int_riscv_masked_atomicrmw_add_i64  : MaskedAtomicRMW64Intrinsic;
  56 def int_riscv_masked_atomicrmw_sub_i64  : MaskedAtomicRMW64Intrinsic;
  57 def int_riscv_masked_atomicrmw_nand_i64 : MaskedAtomicRMW64Intrinsic;
  58 def int_riscv_masked_atomicrmw_max_i64  : MaskedAtomicRMW64WithSextIntrinsic;
  59 def int_riscv_masked_atomicrmw_min_i64  : MaskedAtomicRMW64WithSextIntrinsic;
  60 def int_riscv_masked_atomicrmw_umax_i64 : MaskedAtomicRMW64Intrinsic;
  61 def int_riscv_masked_atomicrmw_umin_i64 : MaskedAtomicRMW64Intrinsic;
  62
  63 def int_riscv_masked_cmpxchg_i64
  64     : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty, llvm_i64_ty, llvm_i64_ty,
  65                                 llvm_i64_ty, llvm_i64_ty],
  66                 [IntrArgMemOnly, NoCapture<0>, ImmArg<4>]>;
  67
  68 } // TargetPrefix = "riscv"