1 //===-- llvm
/Support
/TargetOpcodes.def
- Target Indep Opcodes
---*- C
++ -*-===//
3 // Part of the LLVM Project
, under the Apache License v2.0 with LLVM Exceptions.
4 // See https
://llvm.org
/LICENSE.txt for license information.
5 // SPDX
-License
-Identifier
: Apache
-2.0 WITH LLVM
-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the target independent instruction opcodes.
11 //===----------------------------------------------------------------------===//
13 // NOTE
: NO INCLUDE GUARD DESIRED
!
15 /// HANDLE_TARGET_OPCODE defines an opcode and its associated enum value.
17 #ifndef HANDLE_TARGET_OPCODE
18 #define
HANDLE_TARGET_OPCODE(OPC
, NUM
)
21 /// HANDLE_TARGET_OPCODE_MARKER defines an alternative identifier for an opcode.
23 #ifndef HANDLE_TARGET_OPCODE_MARKER
24 #define
HANDLE_TARGET_OPCODE_MARKER(IDENT
, OPC
)
27 /// Every instruction defined here must also appear in Target.td.
29 HANDLE_TARGET_OPCODE(PHI
)
30 HANDLE_TARGET_OPCODE(INLINEASM
)
31 HANDLE_TARGET_OPCODE(INLINEASM_BR
)
32 HANDLE_TARGET_OPCODE(CFI_INSTRUCTION
)
33 HANDLE_TARGET_OPCODE(EH_LABEL
)
34 HANDLE_TARGET_OPCODE(GC_LABEL
)
35 HANDLE_TARGET_OPCODE(ANNOTATION_LABEL
)
37 /// KILL
- This instruction is a noop that is used only to adjust the
38 /// liveness of registers. This can be useful when dealing with
40 HANDLE_TARGET_OPCODE(KILL
)
42 /// EXTRACT_SUBREG
- This instruction takes two operands
: a register
43 /// that has subregisters
, and a subregister index. It returns the
44 /// extracted subregister value. This is commonly used to implement
45 /// truncation operations on target architectures which support it.
46 HANDLE_TARGET_OPCODE(EXTRACT_SUBREG
)
48 /// INSERT_SUBREG
- This instruction takes three operands
: a register that
49 /// has subregisters
, a register providing an insert value
, and a
50 /// subregister index. It returns the value of the first register with the
51 /// value of the second register inserted. The first register is often
52 /// defined by an IMPLICIT_DEF
, because it is commonly used to implement
53 /// anyext operations on target architectures which support it.
54 HANDLE_TARGET_OPCODE(INSERT_SUBREG
)
56 /// IMPLICIT_DEF
- This is the MachineInstr
-level equivalent of undef.
57 HANDLE_TARGET_OPCODE(IMPLICIT_DEF
)
59 /// SUBREG_TO_REG
- Assert the value of bits in a super register.
60 /// The result of this instruction is the value of the second operand inserted
61 /// into the subregister specified by the third operand. All other bits are
62 /// assumed to be equal to the bits in the immediate integer constant in the
63 /// first operand. This instruction just communicates information
; No code
64 /// should be generated.
65 /// This is typically used after an instruction where the write to a subregister
66 /// implicitly cleared the bits in the super registers.
67 HANDLE_TARGET_OPCODE(SUBREG_TO_REG
)
69 /// COPY_TO_REGCLASS
- This instruction is a placeholder for a plain
70 /// register
-to
-register copy into a specific register class. This is only
71 /// used between instruction selection and MachineInstr creation
, before
72 /// virtual registers have been created for all the instructions
, and it
's
73 /// only needed in cases where the register classes implied by the
74 /// instructions are insufficient. It is emitted as a COPY MachineInstr.
75 HANDLE_TARGET_OPCODE(COPY_TO_REGCLASS)
77 /// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic
78 HANDLE_TARGET_OPCODE(DBG_VALUE)
80 /// DBG_LABEL - a mapping of the llvm.dbg.label intrinsic
81 HANDLE_TARGET_OPCODE(DBG_LABEL)
83 /// REG_SEQUENCE - This variadic instruction is used to form a register that
84 /// represents a consecutive sequence of sub-registers. It's used as a
85 /// register coalescing
/ allocation aid and must be eliminated before code
87 // In SDNode form
, the first operand encodes the register class created by
88 // the REG_SEQUENCE
, while each subsequent pair names a vreg
+ subreg index
89 // pair. Once it has been lowered to a MachineInstr
, the regclass operand
90 // is no longer present.
91 /// e.g. v1027
= REG_SEQUENCE v1024
, 3, v1025
, 4, v1026
, 5
92 /// After register coalescing references of v1024 should be replace with
93 /// v1027
:3, v1025 with v1027
:4, etc.
94 HANDLE_TARGET_OPCODE(REG_SEQUENCE
)
96 /// COPY
- Target
-independent register copy. This instruction can also be
97 /// used to copy between subregisters of virtual registers.
98 HANDLE_TARGET_OPCODE(COPY
)
100 /// BUNDLE
- This instruction represents an instruction bundle. Instructions
101 /// which immediately follow a BUNDLE instruction which are marked with
102 /// 'InsideBundle' flag are inside the bundle.
103 HANDLE_TARGET_OPCODE(BUNDLE
)
105 /// Lifetime markers.
106 HANDLE_TARGET_OPCODE(LIFETIME_START
)
107 HANDLE_TARGET_OPCODE(LIFETIME_END
)
109 /// A Stackmap instruction captures the location of live variables at its
110 /// position in the instruction stream. It is followed by a shadow of bytes
111 /// that must lie within the function and not contain another stackmap.
112 HANDLE_TARGET_OPCODE(STACKMAP
)
114 /// FEntry all
- This is a marker instruction which gets translated into a raw fentry call.
115 HANDLE_TARGET_OPCODE(FENTRY_CALL
)
117 /// Patchable call instruction
- this instruction represents a call to a
118 /// constant address
, followed by a series of NOPs. It is intended to
119 /// support optimizations for dynamic
languages (such as javascript
) that
120 /// rewrite calls to runtimes with more efficient code sequences.
121 /// This also implies a stack map.
122 HANDLE_TARGET_OPCODE(PATCHPOINT
)
124 /// This pseudo
-instruction loads the stack guard value. Targets which need
125 /// to prevent the stack guard value or address from being spilled to the
126 /// stack should override TargetLowering
::emitLoadStackGuardNode and
127 /// additionally expand this pseudo after register allocation.
128 HANDLE_TARGET_OPCODE(LOAD_STACK_GUARD
)
130 /// Call instruction with associated vm state for deoptimization and list
131 /// of live pointers for relocation by the garbage collector. It is
132 /// intended to support garbage collection with fully precise relocating
133 /// collectors and deoptimizations in either the callee or caller.
134 HANDLE_TARGET_OPCODE(STATEPOINT
)
136 /// Instruction that records the offset of a local stack allocation passed to
137 /// llvm.localescape. It has two arguments
: the symbol for the label and the
138 /// frame index of the local stack allocation.
139 HANDLE_TARGET_OPCODE(LOCAL_ESCAPE
)
141 /// Wraps a machine instruction which can fault
, bundled with associated
142 /// information on how to handle such a fault.
143 /// For example loading instruction that may page fault
, bundled with associated
144 /// information on how to handle such a page fault. It is intended to support
145 /// "zero cost" null checks in managed languages by allowing LLVM to fold
146 /// comparisons into existing memory operations.
147 HANDLE_TARGET_OPCODE(FAULTING_OP
)
149 /// Wraps a machine instruction to add patchability constraints. An
150 /// instruction wrapped in PATCHABLE_OP has to either have a minimum
151 /// size or be preceded with a nop of that size. The first operand is
152 /// an immediate denoting the minimum size of the instruction
, the
153 /// second operand is an immediate denoting the opcode of the original
154 /// instruction. The rest of the operands are the operands of the
155 /// original instruction.
156 HANDLE_TARGET_OPCODE(PATCHABLE_OP
)
158 /// This is a marker instruction which gets translated into a nop sled
, useful
159 /// for inserting instrumentation instructions at runtime.
160 HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_ENTER
)
162 /// Wraps a return instruction and its operands to enable adding nop sleds
163 /// either before or after the return. The nop sleds are useful for inserting
164 /// instrumentation instructions at runtime.
165 /// The patch here replaces the return instruction.
166 HANDLE_TARGET_OPCODE(PATCHABLE_RET
)
168 /// This is a marker instruction which gets translated into a nop sled
, useful
169 /// for inserting instrumentation instructions at runtime.
170 /// The patch here prepends the return instruction.
171 /// The same thing as in x86_64 is not possible for ARM because it has multiple
172 /// return instructions. Furthermore
, CPU allows parametrized and even
173 /// conditional return instructions. In the current ARM implementation we are
174 /// making use of the fact that currently LLVM doesn
't seem to generate
175 /// conditional return instructions.
176 /// On ARM, the same instruction can be used for popping multiple registers
177 /// from the stack and returning (it just pops pc register too), and LLVM
178 /// generates it sometimes. So we can't insert the sled between this stack
179 /// adjustment and the return without splitting the original instruction into
2
180 /// instructions. So on ARM
, rather than jumping into the exit trampoline
, we
181 /// call it
, it does the tracing
, preserves the stack and returns.
182 HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_EXIT
)
184 /// Wraps a tail call instruction and its operands to enable adding nop sleds
185 /// either before or after the tail exit. We use this as a disambiguation from
186 /// PATCHABLE_RET which specifically only works for return instructions.
187 HANDLE_TARGET_OPCODE(PATCHABLE_TAIL_CALL
)
189 /// Wraps a logging call and its arguments with nop sleds. At runtime
, this can
190 /// be patched to insert instrumentation instructions.
191 HANDLE_TARGET_OPCODE(PATCHABLE_EVENT_CALL
)
193 /// Wraps a typed logging call and its argument with nop sleds. At runtime
, this
194 /// can be patched to insert instrumentation instructions.
195 HANDLE_TARGET_OPCODE(PATCHABLE_TYPED_EVENT_CALL
)
197 HANDLE_TARGET_OPCODE(ICALL_BRANCH_FUNNEL
)
199 /// The following generic opcodes are not supposed to appear after ISel.
200 /// This is something we might want to relax
, but for now
, this is convenient
201 /// to produce diagnostics.
203 /// Generic ADD instruction. This is an integer add.
204 HANDLE_TARGET_OPCODE(G_ADD
)
205 HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START
, G_ADD
)
207 /// Generic SUB instruction. This is an integer sub.
208 HANDLE_TARGET_OPCODE(G_SUB
)
210 // Generic multiply instruction.
211 HANDLE_TARGET_OPCODE(G_MUL
)
213 // Generic signed division instruction.
214 HANDLE_TARGET_OPCODE(G_SDIV
)
216 // Generic unsigned division instruction.
217 HANDLE_TARGET_OPCODE(G_UDIV
)
219 // Generic signed remainder instruction.
220 HANDLE_TARGET_OPCODE(G_SREM
)
222 // Generic unsigned remainder instruction.
223 HANDLE_TARGET_OPCODE(G_UREM
)
225 /// Generic bitwise and instruction.
226 HANDLE_TARGET_OPCODE(G_AND
)
228 /// Generic bitwise or instruction.
229 HANDLE_TARGET_OPCODE(G_OR
)
231 /// Generic bitwise exclusive
-or instruction.
232 HANDLE_TARGET_OPCODE(G_XOR
)
235 HANDLE_TARGET_OPCODE(G_IMPLICIT_DEF
)
237 /// Generic PHI instruction with types.
238 HANDLE_TARGET_OPCODE(G_PHI
)
240 /// Generic instruction to materialize the address of an alloca or other
241 /// stack
-based object.
242 HANDLE_TARGET_OPCODE(G_FRAME_INDEX
)
244 /// Generic reference to global value.
245 HANDLE_TARGET_OPCODE(G_GLOBAL_VALUE
)
247 /// Generic instruction to extract blocks of bits from the register given
248 /// (typically a sub
-register COPY after instruction selection
).
249 HANDLE_TARGET_OPCODE(G_EXTRACT
)
251 HANDLE_TARGET_OPCODE(G_UNMERGE_VALUES
)
253 /// Generic instruction to insert blocks of bits from the registers given into
255 HANDLE_TARGET_OPCODE(G_INSERT
)
257 /// Generic instruction to paste a variable number of components together into a
259 HANDLE_TARGET_OPCODE(G_MERGE_VALUES
)
261 /// Generic instruction to create a vector value from a number of scalar
263 HANDLE_TARGET_OPCODE(G_BUILD_VECTOR
)
265 /// Generic instruction to create a vector value from a number of scalar
266 /// components
, which have types larger than the result vector elt type.
267 HANDLE_TARGET_OPCODE(G_BUILD_VECTOR_TRUNC
)
269 /// Generic instruction to create a vector by concatenating multiple vectors.
270 HANDLE_TARGET_OPCODE(G_CONCAT_VECTORS
)
272 /// Generic pointer to int conversion.
273 HANDLE_TARGET_OPCODE(G_PTRTOINT
)
275 /// Generic int to pointer conversion.
276 HANDLE_TARGET_OPCODE(G_INTTOPTR
)
278 /// Generic bitcast. The source and destination types must be different
, or a
279 /// COPY is the relevant instruction.
280 HANDLE_TARGET_OPCODE(G_BITCAST
)
282 /// INTRINSIC trunc intrinsic.
283 HANDLE_TARGET_OPCODE(G_INTRINSIC_TRUNC
)
285 /// INTRINSIC round intrinsic.
286 HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUND
)
288 /// Generic
load (including anyext load
)
289 HANDLE_TARGET_OPCODE(G_LOAD
)
291 /// Generic signext load
292 HANDLE_TARGET_OPCODE(G_SEXTLOAD
)
294 /// Generic zeroext load
295 HANDLE_TARGET_OPCODE(G_ZEXTLOAD
)
297 /// Generic indexed
load (including anyext load
)
298 HANDLE_TARGET_OPCODE(G_INDEXED_LOAD
)
300 /// Generic indexed signext load
301 HANDLE_TARGET_OPCODE(G_INDEXED_SEXTLOAD
)
303 /// Generic indexed zeroext load
304 HANDLE_TARGET_OPCODE(G_INDEXED_ZEXTLOAD
)
307 HANDLE_TARGET_OPCODE(G_STORE
)
309 /// Generic indexed store.
310 HANDLE_TARGET_OPCODE(G_INDEXED_STORE
)
312 /// Generic atomic cmpxchg with internal success check.
313 HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG_WITH_SUCCESS
)
315 /// Generic atomic cmpxchg.
316 HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG
)
318 /// Generic atomicrmw.
319 HANDLE_TARGET_OPCODE(G_ATOMICRMW_XCHG
)
320 HANDLE_TARGET_OPCODE(G_ATOMICRMW_ADD
)
321 HANDLE_TARGET_OPCODE(G_ATOMICRMW_SUB
)
322 HANDLE_TARGET_OPCODE(G_ATOMICRMW_AND
)
323 HANDLE_TARGET_OPCODE(G_ATOMICRMW_NAND
)
324 HANDLE_TARGET_OPCODE(G_ATOMICRMW_OR
)
325 HANDLE_TARGET_OPCODE(G_ATOMICRMW_XOR
)
326 HANDLE_TARGET_OPCODE(G_ATOMICRMW_MAX
)
327 HANDLE_TARGET_OPCODE(G_ATOMICRMW_MIN
)
328 HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMAX
)
329 HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMIN
)
330 HANDLE_TARGET_OPCODE(G_ATOMICRMW_FADD
)
331 HANDLE_TARGET_OPCODE(G_ATOMICRMW_FSUB
)
333 // Generic atomic fence
334 HANDLE_TARGET_OPCODE(G_FENCE
)
336 /// Generic conditional branch instruction.
337 HANDLE_TARGET_OPCODE(G_BRCOND
)
339 /// Generic indirect branch instruction.
340 HANDLE_TARGET_OPCODE(G_BRINDIRECT
)
342 /// Generic intrinsic
use (without side effects
).
343 HANDLE_TARGET_OPCODE(G_INTRINSIC
)
345 /// Generic intrinsic
use (with side effects
).
346 HANDLE_TARGET_OPCODE(G_INTRINSIC_W_SIDE_EFFECTS
)
348 /// Generic extension allowing rubbish in high bits.
349 HANDLE_TARGET_OPCODE(G_ANYEXT
)
351 /// Generic instruction to discard the high bits of a register. This differs
352 /// from (G_EXTRACT val
, 0) on its action on vectors
: G_TRUNC will truncate
353 /// each element individually
, G_EXTRACT will typically discard the high
354 /// elements of the vector.
355 HANDLE_TARGET_OPCODE(G_TRUNC
)
357 /// Generic integer constant.
358 HANDLE_TARGET_OPCODE(G_CONSTANT
)
360 /// Generic floating constant.
361 HANDLE_TARGET_OPCODE(G_FCONSTANT
)
363 /// Generic va_start instruction. Stores to its one pointer operand.
364 HANDLE_TARGET_OPCODE(G_VASTART
)
366 /// Generic va_start instruction. Stores to its one pointer operand.
367 HANDLE_TARGET_OPCODE(G_VAARG
)
369 // Generic sign extend
370 HANDLE_TARGET_OPCODE(G_SEXT
)
371 HANDLE_TARGET_OPCODE(G_SEXT_INREG
)
373 // Generic zero extend
374 HANDLE_TARGET_OPCODE(G_ZEXT
)
376 // Generic left
-shift
377 HANDLE_TARGET_OPCODE(G_SHL
)
379 // Generic logical right
-shift
380 HANDLE_TARGET_OPCODE(G_LSHR
)
382 // Generic arithmetic right
-shift
383 HANDLE_TARGET_OPCODE(G_ASHR
)
385 /// Generic integer
-base comparison
, also applicable to vectors of integers.
386 HANDLE_TARGET_OPCODE(G_ICMP
)
388 /// Generic floating
-point comparison
, also applicable to vectors.
389 HANDLE_TARGET_OPCODE(G_FCMP
)
392 HANDLE_TARGET_OPCODE(G_SELECT
)
394 /// Generic unsigned add instruction
, consuming the normal operands and
395 /// producing the result and a carry flag.
396 HANDLE_TARGET_OPCODE(G_UADDO
)
398 /// Generic unsigned add instruction
, consuming the normal operands plus a carry
399 /// flag
, and similarly producing the result and a carry flag.
400 HANDLE_TARGET_OPCODE(G_UADDE
)
402 /// Generic unsigned sub instruction
, consuming the normal operands and
403 /// producing the result and a carry flag.
404 HANDLE_TARGET_OPCODE(G_USUBO
)
406 /// Generic unsigned subtract instruction
, consuming the normal operands plus a
407 /// carry flag
, and similarly producing the result and a carry flag.
408 HANDLE_TARGET_OPCODE(G_USUBE
)
410 /// Generic signed add instruction
, producing the result and a signed overflow
412 HANDLE_TARGET_OPCODE(G_SADDO
)
414 /// Generic signed add instruction
, consuming the normal operands plus a carry
415 /// flag
, and similarly producing the result and a carry flag.
416 HANDLE_TARGET_OPCODE(G_SADDE
)
418 /// Generic signed subtract instruction
, producing the result and a signed
420 HANDLE_TARGET_OPCODE(G_SSUBO
)
422 /// Generic signed sub instruction
, consuming the normal operands plus a carry
423 /// flag
, and similarly producing the result and a carry flag.
424 HANDLE_TARGET_OPCODE(G_SSUBE
)
426 /// Generic unsigned multiply instruction
, producing the result and a signed
428 HANDLE_TARGET_OPCODE(G_UMULO
)
430 /// Generic signed multiply instruction
, producing the result and a signed
432 HANDLE_TARGET_OPCODE(G_SMULO
)
434 // Multiply two numbers at twice the incoming bit
width (unsigned
) and return
435 // the high half of the result.
436 HANDLE_TARGET_OPCODE(G_UMULH
)
438 // Multiply two numbers at twice the incoming bit
width (signed
) and return
439 // the high half of the result.
440 HANDLE_TARGET_OPCODE(G_SMULH
)
442 /// Generic FP addition.
443 HANDLE_TARGET_OPCODE(G_FADD
)
445 /// Generic FP subtraction.
446 HANDLE_TARGET_OPCODE(G_FSUB
)
448 /// Generic FP multiplication.
449 HANDLE_TARGET_OPCODE(G_FMUL
)
451 /// Generic FMA multiplication. Behaves like llvm fma intrinsic
452 HANDLE_TARGET_OPCODE(G_FMA
)
454 /// Generic FP multiply and add. Behaves as separate fmul and fadd.
455 HANDLE_TARGET_OPCODE(G_FMAD
)
457 /// Generic FP division.
458 HANDLE_TARGET_OPCODE(G_FDIV
)
460 /// Generic FP remainder.
461 HANDLE_TARGET_OPCODE(G_FREM
)
463 /// Generic FP exponentiation.
464 HANDLE_TARGET_OPCODE(G_FPOW
)
466 /// Generic base
-e exponential of a value.
467 HANDLE_TARGET_OPCODE(G_FEXP
)
469 /// Generic base
-2 exponential of a value.
470 HANDLE_TARGET_OPCODE(G_FEXP2
)
472 /// Floating point base
-e logarithm of a value.
473 HANDLE_TARGET_OPCODE(G_FLOG
)
475 /// Floating point base
-2 logarithm of a value.
476 HANDLE_TARGET_OPCODE(G_FLOG2
)
478 /// Floating point base
-10 logarithm of a value.
479 HANDLE_TARGET_OPCODE(G_FLOG10
)
481 /// Generic FP negation.
482 HANDLE_TARGET_OPCODE(G_FNEG
)
484 /// Generic FP extension.
485 HANDLE_TARGET_OPCODE(G_FPEXT
)
487 /// Generic float to signed
-int conversion
488 HANDLE_TARGET_OPCODE(G_FPTRUNC
)
490 /// Generic float to signed
-int conversion
491 HANDLE_TARGET_OPCODE(G_FPTOSI
)
493 /// Generic float to unsigned
-int conversion
494 HANDLE_TARGET_OPCODE(G_FPTOUI
)
496 /// Generic signed
-int to float conversion
497 HANDLE_TARGET_OPCODE(G_SITOFP
)
499 /// Generic unsigned
-int to float conversion
500 HANDLE_TARGET_OPCODE(G_UITOFP
)
502 /// Generic FP absolute value.
503 HANDLE_TARGET_OPCODE(G_FABS
)
505 /// FCOPYSIGN(X
, Y
) - Return the value of X with the sign of Y. NOTE
: This does
506 /// not require that X and Y have the same type
, just that they are both
507 /// floating point. X and the result must have the same type.
FCOPYSIGN(f32
,
509 HANDLE_TARGET_OPCODE(G_FCOPYSIGN
)
511 /// Generic FP canonicalize value.
512 HANDLE_TARGET_OPCODE(G_FCANONICALIZE
)
514 /// FP min
/max matching libm
's fmin/fmax
515 HANDLE_TARGET_OPCODE(G_FMINNUM)
516 HANDLE_TARGET_OPCODE(G_FMAXNUM)
518 /// FP min/max matching IEEE-754 2008's minnum
/maxnum semantics.
519 HANDLE_TARGET_OPCODE(G_FMINNUM_IEEE
)
520 HANDLE_TARGET_OPCODE(G_FMAXNUM_IEEE
)
522 /// FP min
/max matching IEEE
-754 2018 draft semantics.
523 HANDLE_TARGET_OPCODE(G_FMINIMUM
)
524 HANDLE_TARGET_OPCODE(G_FMAXIMUM
)
526 /// Generic pointer offset
527 HANDLE_TARGET_OPCODE(G_GEP
)
529 /// Clear the specified number of low bits in a pointer. This rounds the value
530 /// *down
* to the given alignment.
531 HANDLE_TARGET_OPCODE(G_PTR_MASK
)
533 /// Generic signed integer minimum.
534 HANDLE_TARGET_OPCODE(G_SMIN
)
536 /// Generic signed integer maximum.
537 HANDLE_TARGET_OPCODE(G_SMAX
)
539 /// Generic unsigned integer maximum.
540 HANDLE_TARGET_OPCODE(G_UMIN
)
542 /// Generic unsigned integer maximum.
543 HANDLE_TARGET_OPCODE(G_UMAX
)
545 /// Generic BRANCH instruction. This is an unconditional branch.
546 HANDLE_TARGET_OPCODE(G_BR
)
548 /// Generic branch to jump table entry.
549 HANDLE_TARGET_OPCODE(G_BRJT
)
551 /// Generic insertelement.
552 HANDLE_TARGET_OPCODE(G_INSERT_VECTOR_ELT
)
554 /// Generic extractelement.
555 HANDLE_TARGET_OPCODE(G_EXTRACT_VECTOR_ELT
)
557 /// Generic shufflevector.
558 HANDLE_TARGET_OPCODE(G_SHUFFLE_VECTOR
)
560 /// Generic count trailing zeroes.
561 HANDLE_TARGET_OPCODE(G_CTTZ
)
563 /// Same as above
, undefined for zero inputs.
564 HANDLE_TARGET_OPCODE(G_CTTZ_ZERO_UNDEF
)
566 /// Generic count leading zeroes.
567 HANDLE_TARGET_OPCODE(G_CTLZ
)
569 /// Same as above
, undefined for zero inputs.
570 HANDLE_TARGET_OPCODE(G_CTLZ_ZERO_UNDEF
)
572 /// Generic count bits.
573 HANDLE_TARGET_OPCODE(G_CTPOP
)
575 /// Generic byte swap.
576 HANDLE_TARGET_OPCODE(G_BSWAP
)
578 /// Generic bit reverse.
579 HANDLE_TARGET_OPCODE(G_BITREVERSE
)
581 /// Floating point ceil.
582 HANDLE_TARGET_OPCODE(G_FCEIL
)
584 /// Floating point cosine.
585 HANDLE_TARGET_OPCODE(G_FCOS
)
587 /// Floating point sine.
588 HANDLE_TARGET_OPCODE(G_FSIN
)
590 /// Floating point square root.
591 HANDLE_TARGET_OPCODE(G_FSQRT
)
593 /// Floating point floor.
594 HANDLE_TARGET_OPCODE(G_FFLOOR
)
596 /// Floating point round to next integer.
597 HANDLE_TARGET_OPCODE(G_FRINT
)
599 /// Floating point round to nearest integer.
600 HANDLE_TARGET_OPCODE(G_FNEARBYINT
)
602 /// Generic AddressSpaceCast.
603 HANDLE_TARGET_OPCODE(G_ADDRSPACE_CAST
)
605 /// Generic block address
606 HANDLE_TARGET_OPCODE(G_BLOCK_ADDR
)
608 /// Generic jump table address
609 HANDLE_TARGET_OPCODE(G_JUMP_TABLE
)
611 /// Generic dynamic stack allocation.
612 HANDLE_TARGET_OPCODE(G_DYN_STACKALLOC
)
614 // TODO
: Add more generic opcodes as we move along.
616 /// Marker for the end of the generic opcode.
617 /// This is used to check if an opcode is in the range of the
619 HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END
, G_DYN_STACKALLOC
)
621 /// BUILTIN_OP_END
- This must be the last enum value in this list.
622 /// The target
-specific post
-isel opcode values start here.
623 HANDLE_TARGET_OPCODE_MARKER(GENERIC_OP_END
, PRE_ISEL_GENERIC_OPCODE_END
)